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1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/ide-dma.c Version 4.10 June 9, 2000 | |
3 | * | |
4 | * Copyright (c) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * May be copied or modified under the terms of the GNU General Public License | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Special Thanks to Mark for his Six years of work. | |
10 | * | |
11 | * Copyright (c) 1995-1998 Mark Lord | |
12 | * May be copied or modified under the terms of the GNU General Public License | |
13 | */ | |
14 | ||
15 | /* | |
16 | * This module provides support for the bus-master IDE DMA functions | |
17 | * of various PCI chipsets, including the Intel PIIX (i82371FB for | |
18 | * the 430 FX chipset), the PIIX3 (i82371SB for the 430 HX/VX and | |
19 | * 440 chipsets), and the PIIX4 (i82371AB for the 430 TX chipset) | |
20 | * ("PIIX" stands for "PCI ISA IDE Xcellerator"). | |
21 | * | |
22 | * Pretty much the same code works for other IDE PCI bus-mastering chipsets. | |
23 | * | |
24 | * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). | |
25 | * | |
26 | * By default, DMA support is prepared for use, but is currently enabled only | |
27 | * for drives which already have DMA enabled (UltraDMA or mode 2 multi/single), | |
28 | * or which are recognized as "good" (see table below). Drives with only mode0 | |
29 | * or mode1 (multi/single) DMA should also work with this chipset/driver | |
30 | * (eg. MC2112A) but are not enabled by default. | |
31 | * | |
32 | * Use "hdparm -i" to view modes supported by a given drive. | |
33 | * | |
34 | * The hdparm-3.5 (or later) utility can be used for manually enabling/disabling | |
35 | * DMA support, but must be (re-)compiled against this kernel version or later. | |
36 | * | |
37 | * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting. | |
38 | * If problems arise, ide.c will disable DMA operation after a few retries. | |
39 | * This error recovery mechanism works and has been extremely well exercised. | |
40 | * | |
41 | * IDE drives, depending on their vintage, may support several different modes | |
42 | * of DMA operation. The boot-time modes are indicated with a "*" in | |
43 | * the "hdparm -i" listing, and can be changed with *knowledgeable* use of | |
44 | * the "hdparm -X" feature. There is seldom a need to do this, as drives | |
45 | * normally power-up with their "best" PIO/DMA modes enabled. | |
46 | * | |
47 | * Testing has been done with a rather extensive number of drives, | |
48 | * with Quantum & Western Digital models generally outperforming the pack, | |
49 | * and Fujitsu & Conner (and some Seagate which are really Conner) drives | |
50 | * showing more lackluster throughput. | |
51 | * | |
52 | * Keep an eye on /var/adm/messages for "DMA disabled" messages. | |
53 | * | |
54 | * Some people have reported trouble with Intel Zappa motherboards. | |
55 | * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0, | |
56 | * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe | |
57 | * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this). | |
58 | * | |
59 | * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for | |
60 | * fixing the problem with the BIOS on some Acer motherboards. | |
61 | * | |
62 | * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing | |
63 | * "TX" chipset compatibility and for providing patches for the "TX" chipset. | |
64 | * | |
65 | * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack | |
66 | * at generic DMA -- his patches were referred to when preparing this code. | |
67 | * | |
68 | * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> | |
69 | * for supplying a Promise UDMA board & WD UDMA drive for this work! | |
70 | * | |
71 | * And, yes, Intel Zappa boards really *do* use both PIIX IDE ports. | |
72 | * | |
73 | * ATA-66/100 and recovery functions, I forgot the rest...... | |
74 | * | |
75 | */ | |
76 | ||
77 | #include <linux/config.h> | |
78 | #include <linux/module.h> | |
79 | #include <linux/types.h> | |
80 | #include <linux/kernel.h> | |
81 | #include <linux/timer.h> | |
82 | #include <linux/mm.h> | |
83 | #include <linux/interrupt.h> | |
84 | #include <linux/pci.h> | |
85 | #include <linux/init.h> | |
86 | #include <linux/ide.h> | |
87 | #include <linux/delay.h> | |
88 | #include <linux/scatterlist.h> | |
89 | ||
90 | #include <asm/io.h> | |
91 | #include <asm/irq.h> | |
92 | ||
1da177e4 LT |
93 | static const struct drive_list_entry drive_whitelist [] = { |
94 | ||
95 | { "Micropolis 2112A" , "ALL" }, | |
96 | { "CONNER CTMA 4000" , "ALL" }, | |
97 | { "CONNER CTT8000-A" , "ALL" }, | |
98 | { "ST34342A" , "ALL" }, | |
99 | { NULL , NULL } | |
100 | }; | |
101 | ||
102 | static const struct drive_list_entry drive_blacklist [] = { | |
103 | ||
104 | { "WDC AC11000H" , "ALL" }, | |
105 | { "WDC AC22100H" , "ALL" }, | |
106 | { "WDC AC32500H" , "ALL" }, | |
107 | { "WDC AC33100H" , "ALL" }, | |
108 | { "WDC AC31600H" , "ALL" }, | |
109 | { "WDC AC32100H" , "24.09P07" }, | |
110 | { "WDC AC23200L" , "21.10N21" }, | |
111 | { "Compaq CRD-8241B" , "ALL" }, | |
112 | { "CRD-8400B" , "ALL" }, | |
113 | { "CRD-8480B", "ALL" }, | |
114 | { "CRD-8482B", "ALL" }, | |
115 | { "CRD-84" , "ALL" }, | |
116 | { "SanDisk SDP3B" , "ALL" }, | |
117 | { "SanDisk SDP3B-64" , "ALL" }, | |
118 | { "SANYO CD-ROM CRD" , "ALL" }, | |
119 | { "HITACHI CDR-8" , "ALL" }, | |
120 | { "HITACHI CDR-8335" , "ALL" }, | |
121 | { "HITACHI CDR-8435" , "ALL" }, | |
122 | { "Toshiba CD-ROM XM-6202B" , "ALL" }, | |
123 | { "CD-532E-A" , "ALL" }, | |
124 | { "E-IDE CD-ROM CR-840", "ALL" }, | |
125 | { "CD-ROM Drive/F5A", "ALL" }, | |
126 | { "WPI CDD-820", "ALL" }, | |
127 | { "SAMSUNG CD-ROM SC-148C", "ALL" }, | |
128 | { "SAMSUNG CD-ROM SC", "ALL" }, | |
129 | { "SanDisk SDP3B-64" , "ALL" }, | |
1da177e4 LT |
130 | { "ATAPI CD-ROM DRIVE 40X MAXIMUM", "ALL" }, |
131 | { "_NEC DV5800A", "ALL" }, | |
132 | { NULL , NULL } | |
133 | ||
134 | }; | |
135 | ||
136 | /** | |
65e5f2e3 | 137 | * ide_in_drive_list - look for drive in black/white list |
1da177e4 LT |
138 | * @id: drive identifier |
139 | * @drive_table: list to inspect | |
140 | * | |
141 | * Look for a drive in the blacklist and the whitelist tables | |
142 | * Returns 1 if the drive is found in the table. | |
143 | */ | |
144 | ||
65e5f2e3 | 145 | int ide_in_drive_list(struct hd_driveid *id, const struct drive_list_entry *drive_table) |
1da177e4 LT |
146 | { |
147 | for ( ; drive_table->id_model ; drive_table++) | |
148 | if ((!strcmp(drive_table->id_model, id->model)) && | |
149 | ((strstr(drive_table->id_firmware, id->fw_rev)) || | |
150 | (!strcmp(drive_table->id_firmware, "ALL")))) | |
151 | return 1; | |
152 | return 0; | |
153 | } | |
154 | ||
65e5f2e3 JC |
155 | EXPORT_SYMBOL_GPL(ide_in_drive_list); |
156 | ||
1da177e4 LT |
157 | /** |
158 | * ide_dma_intr - IDE DMA interrupt handler | |
159 | * @drive: the drive the interrupt is for | |
160 | * | |
161 | * Handle an interrupt completing a read/write DMA transfer on an | |
162 | * IDE device | |
163 | */ | |
164 | ||
165 | ide_startstop_t ide_dma_intr (ide_drive_t *drive) | |
166 | { | |
167 | u8 stat = 0, dma_stat = 0; | |
168 | ||
169 | dma_stat = HWIF(drive)->ide_dma_end(drive); | |
170 | stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */ | |
171 | if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { | |
172 | if (!dma_stat) { | |
173 | struct request *rq = HWGROUP(drive)->rq; | |
174 | ||
175 | if (rq->rq_disk) { | |
176 | ide_driver_t *drv; | |
177 | ||
178 | drv = *(ide_driver_t **)rq->rq_disk->private_data;; | |
179 | drv->end_request(drive, 1, rq->nr_sectors); | |
180 | } else | |
181 | ide_end_request(drive, 1, rq->nr_sectors); | |
182 | return ide_stopped; | |
183 | } | |
184 | printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n", | |
185 | drive->name, dma_stat); | |
186 | } | |
187 | return ide_error(drive, "dma_intr", stat); | |
188 | } | |
189 | ||
190 | EXPORT_SYMBOL_GPL(ide_dma_intr); | |
191 | ||
192 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
193 | /** | |
194 | * ide_build_sglist - map IDE scatter gather for DMA I/O | |
195 | * @drive: the drive to build the DMA table for | |
196 | * @rq: the request holding the sg list | |
197 | * | |
198 | * Perform the PCI mapping magic necessary to access the source or | |
199 | * target buffers of a request via PCI DMA. The lower layers of the | |
200 | * kernel provide the necessary cache management so that we can | |
201 | * operate in a portable fashion | |
202 | */ | |
203 | ||
204 | int ide_build_sglist(ide_drive_t *drive, struct request *rq) | |
205 | { | |
206 | ide_hwif_t *hwif = HWIF(drive); | |
207 | struct scatterlist *sg = hwif->sg_table; | |
208 | ||
209 | if ((rq->flags & REQ_DRIVE_TASKFILE) && rq->nr_sectors > 256) | |
210 | BUG(); | |
211 | ||
212 | ide_map_sg(drive, rq); | |
213 | ||
214 | if (rq_data_dir(rq) == READ) | |
215 | hwif->sg_dma_direction = PCI_DMA_FROMDEVICE; | |
216 | else | |
217 | hwif->sg_dma_direction = PCI_DMA_TODEVICE; | |
218 | ||
219 | return pci_map_sg(hwif->pci_dev, sg, hwif->sg_nents, hwif->sg_dma_direction); | |
220 | } | |
221 | ||
222 | EXPORT_SYMBOL_GPL(ide_build_sglist); | |
223 | ||
224 | /** | |
225 | * ide_build_dmatable - build IDE DMA table | |
226 | * | |
227 | * ide_build_dmatable() prepares a dma request. We map the command | |
228 | * to get the pci bus addresses of the buffers and then build up | |
229 | * the PRD table that the IDE layer wants to be fed. The code | |
230 | * knows about the 64K wrap bug in the CS5530. | |
231 | * | |
232 | * Returns the number of built PRD entries if all went okay, | |
233 | * returns 0 otherwise. | |
234 | * | |
235 | * May also be invoked from trm290.c | |
236 | */ | |
237 | ||
238 | int ide_build_dmatable (ide_drive_t *drive, struct request *rq) | |
239 | { | |
240 | ide_hwif_t *hwif = HWIF(drive); | |
241 | unsigned int *table = hwif->dmatable_cpu; | |
242 | unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0; | |
243 | unsigned int count = 0; | |
244 | int i; | |
245 | struct scatterlist *sg; | |
246 | ||
247 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
248 | ||
249 | if (!i) | |
250 | return 0; | |
251 | ||
252 | sg = hwif->sg_table; | |
253 | while (i) { | |
254 | u32 cur_addr; | |
255 | u32 cur_len; | |
256 | ||
257 | cur_addr = sg_dma_address(sg); | |
258 | cur_len = sg_dma_len(sg); | |
259 | ||
260 | /* | |
261 | * Fill in the dma table, without crossing any 64kB boundaries. | |
262 | * Most hardware requires 16-bit alignment of all blocks, | |
263 | * but the trm290 requires 32-bit alignment. | |
264 | */ | |
265 | ||
266 | while (cur_len) { | |
267 | if (count++ >= PRD_ENTRIES) { | |
268 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
269 | goto use_pio_instead; | |
270 | } else { | |
271 | u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff); | |
272 | ||
273 | if (bcount > cur_len) | |
274 | bcount = cur_len; | |
275 | *table++ = cpu_to_le32(cur_addr); | |
276 | xcount = bcount & 0xffff; | |
277 | if (is_trm290) | |
278 | xcount = ((xcount >> 2) - 1) << 16; | |
279 | if (xcount == 0x0000) { | |
280 | /* | |
281 | * Most chipsets correctly interpret a length of 0x0000 as 64KB, | |
282 | * but at least one (e.g. CS5530) misinterprets it as zero (!). | |
283 | * So here we break the 64KB entry into two 32KB entries instead. | |
284 | */ | |
285 | if (count++ >= PRD_ENTRIES) { | |
286 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
287 | goto use_pio_instead; | |
288 | } | |
289 | *table++ = cpu_to_le32(0x8000); | |
290 | *table++ = cpu_to_le32(cur_addr + 0x8000); | |
291 | xcount = 0x8000; | |
292 | } | |
293 | *table++ = cpu_to_le32(xcount); | |
294 | cur_addr += bcount; | |
295 | cur_len -= bcount; | |
296 | } | |
297 | } | |
298 | ||
299 | sg++; | |
300 | i--; | |
301 | } | |
302 | ||
303 | if (count) { | |
304 | if (!is_trm290) | |
305 | *--table |= cpu_to_le32(0x80000000); | |
306 | return count; | |
307 | } | |
308 | printk(KERN_ERR "%s: empty DMA table?\n", drive->name); | |
309 | use_pio_instead: | |
310 | pci_unmap_sg(hwif->pci_dev, | |
311 | hwif->sg_table, | |
312 | hwif->sg_nents, | |
313 | hwif->sg_dma_direction); | |
314 | return 0; /* revert to PIO for this request */ | |
315 | } | |
316 | ||
317 | EXPORT_SYMBOL_GPL(ide_build_dmatable); | |
318 | ||
319 | /** | |
320 | * ide_destroy_dmatable - clean up DMA mapping | |
321 | * @drive: The drive to unmap | |
322 | * | |
323 | * Teardown mappings after DMA has completed. This must be called | |
324 | * after the completion of each use of ide_build_dmatable and before | |
325 | * the next use of ide_build_dmatable. Failure to do so will cause | |
326 | * an oops as only one mapping can be live for each target at a given | |
327 | * time. | |
328 | */ | |
329 | ||
330 | void ide_destroy_dmatable (ide_drive_t *drive) | |
331 | { | |
332 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
333 | struct scatterlist *sg = HWIF(drive)->sg_table; | |
334 | int nents = HWIF(drive)->sg_nents; | |
335 | ||
336 | pci_unmap_sg(dev, sg, nents, HWIF(drive)->sg_dma_direction); | |
337 | } | |
338 | ||
339 | EXPORT_SYMBOL_GPL(ide_destroy_dmatable); | |
340 | ||
341 | /** | |
342 | * config_drive_for_dma - attempt to activate IDE DMA | |
343 | * @drive: the drive to place in DMA mode | |
344 | * | |
345 | * If the drive supports at least mode 2 DMA or UDMA of any kind | |
346 | * then attempt to place it into DMA mode. Drives that are known to | |
347 | * support DMA but predate the DMA properties or that are known | |
348 | * to have DMA handling bugs are also set up appropriately based | |
349 | * on the good/bad drive lists. | |
350 | */ | |
351 | ||
352 | static int config_drive_for_dma (ide_drive_t *drive) | |
353 | { | |
354 | struct hd_driveid *id = drive->id; | |
355 | ide_hwif_t *hwif = HWIF(drive); | |
356 | ||
357 | if ((id->capability & 1) && hwif->autodma) { | |
358 | /* | |
359 | * Enable DMA on any drive that has | |
360 | * UltraDMA (mode 0/1/2/3/4/5/6) enabled | |
361 | */ | |
362 | if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f)) | |
363 | return hwif->ide_dma_on(drive); | |
364 | /* | |
365 | * Enable DMA on any drive that has mode2 DMA | |
366 | * (multi or single) enabled | |
367 | */ | |
368 | if (id->field_valid & 2) /* regular DMA */ | |
369 | if ((id->dma_mword & 0x404) == 0x404 || | |
370 | (id->dma_1word & 0x404) == 0x404) | |
371 | return hwif->ide_dma_on(drive); | |
372 | ||
373 | /* Consult the list of known "good" drives */ | |
374 | if (__ide_dma_good_drive(drive)) | |
375 | return hwif->ide_dma_on(drive); | |
376 | } | |
377 | // if (hwif->tuneproc != NULL) hwif->tuneproc(drive, 255); | |
378 | return hwif->ide_dma_off_quietly(drive); | |
379 | } | |
380 | ||
381 | /** | |
382 | * dma_timer_expiry - handle a DMA timeout | |
383 | * @drive: Drive that timed out | |
384 | * | |
385 | * An IDE DMA transfer timed out. In the event of an error we ask | |
386 | * the driver to resolve the problem, if a DMA transfer is still | |
387 | * in progress we continue to wait (arguably we need to add a | |
388 | * secondary 'I don't care what the drive thinks' timeout here) | |
389 | * Finally if we have an interrupt we let it complete the I/O. | |
390 | * But only one time - we clear expiry and if it's still not | |
391 | * completed after WAIT_CMD, we error and retry in PIO. | |
392 | * This can occur if an interrupt is lost or due to hang or bugs. | |
393 | */ | |
394 | ||
395 | static int dma_timer_expiry (ide_drive_t *drive) | |
396 | { | |
397 | ide_hwif_t *hwif = HWIF(drive); | |
398 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
399 | ||
400 | printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n", | |
401 | drive->name, dma_stat); | |
402 | ||
403 | if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ | |
404 | return WAIT_CMD; | |
405 | ||
406 | HWGROUP(drive)->expiry = NULL; /* one free ride for now */ | |
407 | ||
408 | /* 1 dmaing, 2 error, 4 intr */ | |
409 | if (dma_stat & 2) /* ERROR */ | |
410 | return -1; | |
411 | ||
412 | if (dma_stat & 1) /* DMAing */ | |
413 | return WAIT_CMD; | |
414 | ||
415 | if (dma_stat & 4) /* Got an Interrupt */ | |
416 | return WAIT_CMD; | |
417 | ||
418 | return 0; /* Status is unknown -- reset the bus */ | |
419 | } | |
420 | ||
421 | /** | |
422 | * __ide_dma_host_off - Generic DMA kill | |
423 | * @drive: drive to control | |
424 | * | |
425 | * Perform the generic IDE controller DMA off operation. This | |
426 | * works for most IDE bus mastering controllers | |
427 | */ | |
428 | ||
429 | int __ide_dma_host_off (ide_drive_t *drive) | |
430 | { | |
431 | ide_hwif_t *hwif = HWIF(drive); | |
432 | u8 unit = (drive->select.b.unit & 0x01); | |
433 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
434 | ||
435 | hwif->OUTB((dma_stat & ~(1<<(5+unit))), hwif->dma_status); | |
436 | return 0; | |
437 | } | |
438 | ||
439 | EXPORT_SYMBOL(__ide_dma_host_off); | |
440 | ||
441 | /** | |
442 | * __ide_dma_host_off_quietly - Generic DMA kill | |
443 | * @drive: drive to control | |
444 | * | |
445 | * Turn off the current DMA on this IDE controller. | |
446 | */ | |
447 | ||
448 | int __ide_dma_off_quietly (ide_drive_t *drive) | |
449 | { | |
450 | drive->using_dma = 0; | |
451 | ide_toggle_bounce(drive, 0); | |
452 | ||
453 | if (HWIF(drive)->ide_dma_host_off(drive)) | |
454 | return 1; | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
459 | EXPORT_SYMBOL(__ide_dma_off_quietly); | |
460 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ | |
461 | ||
462 | /** | |
463 | * __ide_dma_off - disable DMA on a device | |
464 | * @drive: drive to disable DMA on | |
465 | * | |
466 | * Disable IDE DMA for a device on this IDE controller. | |
467 | * Inform the user that DMA has been disabled. | |
468 | */ | |
469 | ||
470 | int __ide_dma_off (ide_drive_t *drive) | |
471 | { | |
472 | printk(KERN_INFO "%s: DMA disabled\n", drive->name); | |
473 | return HWIF(drive)->ide_dma_off_quietly(drive); | |
474 | } | |
475 | ||
476 | EXPORT_SYMBOL(__ide_dma_off); | |
477 | ||
478 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
479 | /** | |
480 | * __ide_dma_host_on - Enable DMA on a host | |
481 | * @drive: drive to enable for DMA | |
482 | * | |
483 | * Enable DMA on an IDE controller following generic bus mastering | |
484 | * IDE controller behaviour | |
485 | */ | |
486 | ||
487 | int __ide_dma_host_on (ide_drive_t *drive) | |
488 | { | |
489 | if (drive->using_dma) { | |
490 | ide_hwif_t *hwif = HWIF(drive); | |
491 | u8 unit = (drive->select.b.unit & 0x01); | |
492 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
493 | ||
494 | hwif->OUTB((dma_stat|(1<<(5+unit))), hwif->dma_status); | |
495 | return 0; | |
496 | } | |
497 | return 1; | |
498 | } | |
499 | ||
500 | EXPORT_SYMBOL(__ide_dma_host_on); | |
501 | ||
502 | /** | |
503 | * __ide_dma_on - Enable DMA on a device | |
504 | * @drive: drive to enable DMA on | |
505 | * | |
506 | * Enable IDE DMA for a device on this IDE controller. | |
507 | */ | |
508 | ||
509 | int __ide_dma_on (ide_drive_t *drive) | |
510 | { | |
511 | /* consult the list of known "bad" drives */ | |
512 | if (__ide_dma_bad_drive(drive)) | |
513 | return 1; | |
514 | ||
515 | drive->using_dma = 1; | |
516 | ide_toggle_bounce(drive, 1); | |
517 | ||
518 | if (HWIF(drive)->ide_dma_host_on(drive)) | |
519 | return 1; | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
524 | EXPORT_SYMBOL(__ide_dma_on); | |
525 | ||
526 | /** | |
527 | * __ide_dma_check - check DMA setup | |
528 | * @drive: drive to check | |
529 | * | |
530 | * Don't use - due for extermination | |
531 | */ | |
532 | ||
533 | int __ide_dma_check (ide_drive_t *drive) | |
534 | { | |
535 | return config_drive_for_dma(drive); | |
536 | } | |
537 | ||
538 | EXPORT_SYMBOL(__ide_dma_check); | |
539 | ||
540 | /** | |
541 | * ide_dma_setup - begin a DMA phase | |
542 | * @drive: target device | |
543 | * | |
544 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
545 | * and then set up the DMA transfer registers for a device | |
546 | * that follows generic IDE PCI DMA behaviour. Controllers can | |
547 | * override this function if they need to | |
548 | * | |
549 | * Returns 0 on success. If a PIO fallback is required then 1 | |
550 | * is returned. | |
551 | */ | |
552 | ||
553 | int ide_dma_setup(ide_drive_t *drive) | |
554 | { | |
555 | ide_hwif_t *hwif = drive->hwif; | |
556 | struct request *rq = HWGROUP(drive)->rq; | |
557 | unsigned int reading; | |
558 | u8 dma_stat; | |
559 | ||
560 | if (rq_data_dir(rq)) | |
561 | reading = 0; | |
562 | else | |
563 | reading = 1 << 3; | |
564 | ||
565 | /* fall back to pio! */ | |
566 | if (!ide_build_dmatable(drive, rq)) { | |
567 | ide_map_sg(drive, rq); | |
568 | return 1; | |
569 | } | |
570 | ||
571 | /* PRD table */ | |
572 | hwif->OUTL(hwif->dmatable_dma, hwif->dma_prdtable); | |
573 | ||
574 | /* specify r/w */ | |
575 | hwif->OUTB(reading, hwif->dma_command); | |
576 | ||
577 | /* read dma_status for INTR & ERROR flags */ | |
578 | dma_stat = hwif->INB(hwif->dma_status); | |
579 | ||
580 | /* clear INTR & ERROR flags */ | |
581 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
582 | drive->waiting_for_dma = 1; | |
583 | return 0; | |
584 | } | |
585 | ||
586 | EXPORT_SYMBOL_GPL(ide_dma_setup); | |
587 | ||
588 | static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) | |
589 | { | |
590 | /* issue cmd to drive */ | |
591 | ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry); | |
592 | } | |
593 | ||
594 | void ide_dma_start(ide_drive_t *drive) | |
595 | { | |
596 | ide_hwif_t *hwif = HWIF(drive); | |
597 | u8 dma_cmd = hwif->INB(hwif->dma_command); | |
598 | ||
599 | /* Note that this is done *after* the cmd has | |
600 | * been issued to the drive, as per the BM-IDE spec. | |
601 | * The Promise Ultra33 doesn't work correctly when | |
602 | * we do this part before issuing the drive cmd. | |
603 | */ | |
604 | /* start DMA */ | |
605 | hwif->OUTB(dma_cmd|1, hwif->dma_command); | |
606 | hwif->dma = 1; | |
607 | wmb(); | |
608 | } | |
609 | ||
610 | EXPORT_SYMBOL_GPL(ide_dma_start); | |
611 | ||
612 | /* returns 1 on error, 0 otherwise */ | |
613 | int __ide_dma_end (ide_drive_t *drive) | |
614 | { | |
615 | ide_hwif_t *hwif = HWIF(drive); | |
616 | u8 dma_stat = 0, dma_cmd = 0; | |
617 | ||
618 | drive->waiting_for_dma = 0; | |
619 | /* get dma_command mode */ | |
620 | dma_cmd = hwif->INB(hwif->dma_command); | |
621 | /* stop DMA */ | |
622 | hwif->OUTB(dma_cmd&~1, hwif->dma_command); | |
623 | /* get DMA status */ | |
624 | dma_stat = hwif->INB(hwif->dma_status); | |
625 | /* clear the INTR & ERROR bits */ | |
626 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
627 | /* purge DMA mappings */ | |
628 | ide_destroy_dmatable(drive); | |
629 | /* verify good DMA status */ | |
630 | hwif->dma = 0; | |
631 | wmb(); | |
632 | return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; | |
633 | } | |
634 | ||
635 | EXPORT_SYMBOL(__ide_dma_end); | |
636 | ||
637 | /* returns 1 if dma irq issued, 0 otherwise */ | |
638 | static int __ide_dma_test_irq(ide_drive_t *drive) | |
639 | { | |
640 | ide_hwif_t *hwif = HWIF(drive); | |
641 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
642 | ||
643 | #if 0 /* do not set unless you know what you are doing */ | |
644 | if (dma_stat & 4) { | |
645 | u8 stat = hwif->INB(IDE_STATUS_REG); | |
646 | hwif->OUTB(hwif->dma_status, dma_stat & 0xE4); | |
647 | } | |
648 | #endif | |
649 | /* return 1 if INTR asserted */ | |
650 | if ((dma_stat & 4) == 4) | |
651 | return 1; | |
652 | if (!drive->waiting_for_dma) | |
653 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
654 | drive->name, __FUNCTION__); | |
655 | return 0; | |
656 | } | |
657 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ | |
658 | ||
659 | int __ide_dma_bad_drive (ide_drive_t *drive) | |
660 | { | |
661 | struct hd_driveid *id = drive->id; | |
662 | ||
65e5f2e3 | 663 | int blacklist = ide_in_drive_list(id, drive_blacklist); |
1da177e4 LT |
664 | if (blacklist) { |
665 | printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", | |
666 | drive->name, id->model); | |
667 | return blacklist; | |
668 | } | |
669 | return 0; | |
670 | } | |
671 | ||
672 | EXPORT_SYMBOL(__ide_dma_bad_drive); | |
673 | ||
674 | int __ide_dma_good_drive (ide_drive_t *drive) | |
675 | { | |
676 | struct hd_driveid *id = drive->id; | |
65e5f2e3 | 677 | return ide_in_drive_list(id, drive_whitelist); |
1da177e4 LT |
678 | } |
679 | ||
680 | EXPORT_SYMBOL(__ide_dma_good_drive); | |
681 | ||
682 | int ide_use_dma(ide_drive_t *drive) | |
683 | { | |
684 | struct hd_driveid *id = drive->id; | |
685 | ide_hwif_t *hwif = drive->hwif; | |
686 | ||
687 | /* consult the list of known "bad" drives */ | |
688 | if (__ide_dma_bad_drive(drive)) | |
689 | return 0; | |
690 | ||
691 | /* capable of UltraDMA modes */ | |
692 | if (id->field_valid & 4) { | |
693 | if (hwif->ultra_mask & id->dma_ultra) | |
694 | return 1; | |
695 | } | |
696 | ||
697 | /* capable of regular DMA modes */ | |
698 | if (id->field_valid & 2) { | |
699 | if (hwif->mwdma_mask & id->dma_mword) | |
700 | return 1; | |
701 | if (hwif->swdma_mask & id->dma_1word) | |
702 | return 1; | |
703 | } | |
704 | ||
705 | /* consult the list of known "good" drives */ | |
706 | if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150) | |
707 | return 1; | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
712 | EXPORT_SYMBOL_GPL(ide_use_dma); | |
713 | ||
714 | void ide_dma_verbose(ide_drive_t *drive) | |
715 | { | |
716 | struct hd_driveid *id = drive->id; | |
717 | ide_hwif_t *hwif = HWIF(drive); | |
718 | ||
719 | if (id->field_valid & 4) { | |
720 | if ((id->dma_ultra >> 8) && (id->dma_mword >> 8)) | |
721 | goto bug_dma_off; | |
722 | if (id->dma_ultra & ((id->dma_ultra >> 8) & hwif->ultra_mask)) { | |
723 | if (((id->dma_ultra >> 11) & 0x1F) && | |
724 | eighty_ninty_three(drive)) { | |
725 | if ((id->dma_ultra >> 15) & 1) { | |
726 | printk(", UDMA(mode 7)"); | |
727 | } else if ((id->dma_ultra >> 14) & 1) { | |
728 | printk(", UDMA(133)"); | |
729 | } else if ((id->dma_ultra >> 13) & 1) { | |
730 | printk(", UDMA(100)"); | |
731 | } else if ((id->dma_ultra >> 12) & 1) { | |
732 | printk(", UDMA(66)"); | |
733 | } else if ((id->dma_ultra >> 11) & 1) { | |
734 | printk(", UDMA(44)"); | |
735 | } else | |
736 | goto mode_two; | |
737 | } else { | |
738 | mode_two: | |
739 | if ((id->dma_ultra >> 10) & 1) { | |
740 | printk(", UDMA(33)"); | |
741 | } else if ((id->dma_ultra >> 9) & 1) { | |
742 | printk(", UDMA(25)"); | |
743 | } else if ((id->dma_ultra >> 8) & 1) { | |
744 | printk(", UDMA(16)"); | |
745 | } | |
746 | } | |
747 | } else { | |
748 | printk(", (U)DMA"); /* Can be BIOS-enabled! */ | |
749 | } | |
750 | } else if (id->field_valid & 2) { | |
751 | if ((id->dma_mword >> 8) && (id->dma_1word >> 8)) | |
752 | goto bug_dma_off; | |
753 | printk(", DMA"); | |
754 | } else if (id->field_valid & 1) { | |
755 | printk(", BUG"); | |
756 | } | |
757 | return; | |
758 | bug_dma_off: | |
759 | printk(", BUG DMA OFF"); | |
760 | hwif->ide_dma_off_quietly(drive); | |
761 | return; | |
762 | } | |
763 | ||
764 | EXPORT_SYMBOL(ide_dma_verbose); | |
765 | ||
766 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
767 | int __ide_dma_lostirq (ide_drive_t *drive) | |
768 | { | |
769 | printk("%s: DMA interrupt recovery\n", drive->name); | |
770 | return 1; | |
771 | } | |
772 | ||
773 | EXPORT_SYMBOL(__ide_dma_lostirq); | |
774 | ||
775 | int __ide_dma_timeout (ide_drive_t *drive) | |
776 | { | |
777 | printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); | |
778 | if (HWIF(drive)->ide_dma_test_irq(drive)) | |
779 | return 0; | |
780 | ||
781 | return HWIF(drive)->ide_dma_end(drive); | |
782 | } | |
783 | ||
784 | EXPORT_SYMBOL(__ide_dma_timeout); | |
785 | ||
786 | /* | |
787 | * Needed for allowing full modular support of ide-driver | |
788 | */ | |
789 | static int ide_release_dma_engine(ide_hwif_t *hwif) | |
790 | { | |
791 | if (hwif->dmatable_cpu) { | |
792 | pci_free_consistent(hwif->pci_dev, | |
793 | PRD_ENTRIES * PRD_BYTES, | |
794 | hwif->dmatable_cpu, | |
795 | hwif->dmatable_dma); | |
796 | hwif->dmatable_cpu = NULL; | |
797 | } | |
798 | return 1; | |
799 | } | |
800 | ||
801 | static int ide_release_iomio_dma(ide_hwif_t *hwif) | |
802 | { | |
803 | if ((hwif->dma_extra) && (hwif->channel == 0)) | |
804 | release_region((hwif->dma_base + 16), hwif->dma_extra); | |
805 | release_region(hwif->dma_base, 8); | |
806 | if (hwif->dma_base2) | |
807 | release_region(hwif->dma_base, 8); | |
808 | return 1; | |
809 | } | |
810 | ||
811 | /* | |
812 | * Needed for allowing full modular support of ide-driver | |
813 | */ | |
814 | int ide_release_dma (ide_hwif_t *hwif) | |
815 | { | |
816 | if (hwif->mmio == 2) | |
817 | return 1; | |
818 | if (hwif->chipset == ide_etrax100) | |
819 | return 1; | |
820 | ||
821 | ide_release_dma_engine(hwif); | |
822 | return ide_release_iomio_dma(hwif); | |
823 | } | |
824 | ||
825 | static int ide_allocate_dma_engine(ide_hwif_t *hwif) | |
826 | { | |
827 | hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev, | |
828 | PRD_ENTRIES * PRD_BYTES, | |
829 | &hwif->dmatable_dma); | |
830 | ||
831 | if (hwif->dmatable_cpu) | |
832 | return 0; | |
833 | ||
834 | printk(KERN_ERR "%s: -- Error, unable to allocate%s DMA table(s).\n", | |
835 | hwif->cds->name, !hwif->dmatable_cpu ? " CPU" : ""); | |
836 | ||
837 | ide_release_dma_engine(hwif); | |
838 | return 1; | |
839 | } | |
840 | ||
841 | static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
842 | { | |
843 | printk(KERN_INFO " %s: MMIO-DMA ", hwif->name); | |
844 | ||
845 | hwif->dma_base = base; | |
846 | if (hwif->cds->extra && hwif->channel == 0) | |
847 | hwif->dma_extra = hwif->cds->extra; | |
848 | ||
849 | if(hwif->mate) | |
850 | hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base; | |
851 | else | |
852 | hwif->dma_master = base; | |
853 | return 0; | |
854 | } | |
855 | ||
856 | static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
857 | { | |
858 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx", | |
859 | hwif->name, base, base + ports - 1); | |
860 | if (!request_region(base, ports, hwif->name)) { | |
861 | printk(" -- Error, ports in use.\n"); | |
862 | return 1; | |
863 | } | |
864 | hwif->dma_base = base; | |
865 | if ((hwif->cds->extra) && (hwif->channel == 0)) { | |
866 | request_region(base+16, hwif->cds->extra, hwif->cds->name); | |
867 | hwif->dma_extra = hwif->cds->extra; | |
868 | } | |
869 | ||
870 | if(hwif->mate) | |
871 | hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base; | |
872 | else | |
873 | hwif->dma_master = base; | |
874 | if (hwif->dma_base2) { | |
875 | if (!request_region(hwif->dma_base2, ports, hwif->name)) | |
876 | { | |
877 | printk(" -- Error, secondary ports in use.\n"); | |
878 | release_region(base, ports); | |
879 | return 1; | |
880 | } | |
881 | } | |
882 | return 0; | |
883 | } | |
884 | ||
885 | static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
886 | { | |
887 | if (hwif->mmio == 2) | |
888 | return ide_mapped_mmio_dma(hwif, base,ports); | |
889 | BUG_ON(hwif->mmio == 1); | |
890 | return ide_iomio_dma(hwif, base, ports); | |
891 | } | |
892 | ||
893 | /* | |
894 | * This can be called for a dynamically installed interface. Don't __init it | |
895 | */ | |
896 | void ide_setup_dma (ide_hwif_t *hwif, unsigned long dma_base, unsigned int num_ports) | |
897 | { | |
898 | if (ide_dma_iobase(hwif, dma_base, num_ports)) | |
899 | return; | |
900 | ||
901 | if (ide_allocate_dma_engine(hwif)) { | |
902 | ide_release_dma(hwif); | |
903 | return; | |
904 | } | |
905 | ||
906 | if (!(hwif->dma_command)) | |
907 | hwif->dma_command = hwif->dma_base; | |
908 | if (!(hwif->dma_vendor1)) | |
909 | hwif->dma_vendor1 = (hwif->dma_base + 1); | |
910 | if (!(hwif->dma_status)) | |
911 | hwif->dma_status = (hwif->dma_base + 2); | |
912 | if (!(hwif->dma_vendor3)) | |
913 | hwif->dma_vendor3 = (hwif->dma_base + 3); | |
914 | if (!(hwif->dma_prdtable)) | |
915 | hwif->dma_prdtable = (hwif->dma_base + 4); | |
916 | ||
917 | if (!hwif->ide_dma_off_quietly) | |
918 | hwif->ide_dma_off_quietly = &__ide_dma_off_quietly; | |
919 | if (!hwif->ide_dma_host_off) | |
920 | hwif->ide_dma_host_off = &__ide_dma_host_off; | |
921 | if (!hwif->ide_dma_on) | |
922 | hwif->ide_dma_on = &__ide_dma_on; | |
923 | if (!hwif->ide_dma_host_on) | |
924 | hwif->ide_dma_host_on = &__ide_dma_host_on; | |
925 | if (!hwif->ide_dma_check) | |
926 | hwif->ide_dma_check = &__ide_dma_check; | |
927 | if (!hwif->dma_setup) | |
928 | hwif->dma_setup = &ide_dma_setup; | |
929 | if (!hwif->dma_exec_cmd) | |
930 | hwif->dma_exec_cmd = &ide_dma_exec_cmd; | |
931 | if (!hwif->dma_start) | |
932 | hwif->dma_start = &ide_dma_start; | |
933 | if (!hwif->ide_dma_end) | |
934 | hwif->ide_dma_end = &__ide_dma_end; | |
935 | if (!hwif->ide_dma_test_irq) | |
936 | hwif->ide_dma_test_irq = &__ide_dma_test_irq; | |
937 | if (!hwif->ide_dma_timeout) | |
938 | hwif->ide_dma_timeout = &__ide_dma_timeout; | |
939 | if (!hwif->ide_dma_lostirq) | |
940 | hwif->ide_dma_lostirq = &__ide_dma_lostirq; | |
941 | ||
942 | if (hwif->chipset != ide_trm290) { | |
943 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
944 | printk(", BIOS settings: %s:%s, %s:%s", | |
945 | hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "pio", | |
946 | hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "pio"); | |
947 | } | |
948 | printk("\n"); | |
949 | ||
950 | if (!(hwif->dma_master)) | |
951 | BUG(); | |
952 | } | |
953 | ||
954 | EXPORT_SYMBOL_GPL(ide_setup_dma); | |
955 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |