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1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/ide-dma.c Version 4.10 June 9, 2000 | |
3 | * | |
4 | * Copyright (c) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * May be copied or modified under the terms of the GNU General Public License | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Special Thanks to Mark for his Six years of work. | |
10 | * | |
11 | * Copyright (c) 1995-1998 Mark Lord | |
12 | * May be copied or modified under the terms of the GNU General Public License | |
13 | */ | |
14 | ||
15 | /* | |
16 | * This module provides support for the bus-master IDE DMA functions | |
17 | * of various PCI chipsets, including the Intel PIIX (i82371FB for | |
18 | * the 430 FX chipset), the PIIX3 (i82371SB for the 430 HX/VX and | |
19 | * 440 chipsets), and the PIIX4 (i82371AB for the 430 TX chipset) | |
20 | * ("PIIX" stands for "PCI ISA IDE Xcellerator"). | |
21 | * | |
22 | * Pretty much the same code works for other IDE PCI bus-mastering chipsets. | |
23 | * | |
24 | * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). | |
25 | * | |
26 | * By default, DMA support is prepared for use, but is currently enabled only | |
27 | * for drives which already have DMA enabled (UltraDMA or mode 2 multi/single), | |
28 | * or which are recognized as "good" (see table below). Drives with only mode0 | |
29 | * or mode1 (multi/single) DMA should also work with this chipset/driver | |
30 | * (eg. MC2112A) but are not enabled by default. | |
31 | * | |
32 | * Use "hdparm -i" to view modes supported by a given drive. | |
33 | * | |
34 | * The hdparm-3.5 (or later) utility can be used for manually enabling/disabling | |
35 | * DMA support, but must be (re-)compiled against this kernel version or later. | |
36 | * | |
37 | * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting. | |
38 | * If problems arise, ide.c will disable DMA operation after a few retries. | |
39 | * This error recovery mechanism works and has been extremely well exercised. | |
40 | * | |
41 | * IDE drives, depending on their vintage, may support several different modes | |
42 | * of DMA operation. The boot-time modes are indicated with a "*" in | |
43 | * the "hdparm -i" listing, and can be changed with *knowledgeable* use of | |
44 | * the "hdparm -X" feature. There is seldom a need to do this, as drives | |
45 | * normally power-up with their "best" PIO/DMA modes enabled. | |
46 | * | |
47 | * Testing has been done with a rather extensive number of drives, | |
48 | * with Quantum & Western Digital models generally outperforming the pack, | |
49 | * and Fujitsu & Conner (and some Seagate which are really Conner) drives | |
50 | * showing more lackluster throughput. | |
51 | * | |
52 | * Keep an eye on /var/adm/messages for "DMA disabled" messages. | |
53 | * | |
54 | * Some people have reported trouble with Intel Zappa motherboards. | |
55 | * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0, | |
56 | * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe | |
57 | * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this). | |
58 | * | |
59 | * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for | |
60 | * fixing the problem with the BIOS on some Acer motherboards. | |
61 | * | |
62 | * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing | |
63 | * "TX" chipset compatibility and for providing patches for the "TX" chipset. | |
64 | * | |
65 | * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack | |
66 | * at generic DMA -- his patches were referred to when preparing this code. | |
67 | * | |
68 | * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> | |
69 | * for supplying a Promise UDMA board & WD UDMA drive for this work! | |
70 | * | |
71 | * And, yes, Intel Zappa boards really *do* use both PIIX IDE ports. | |
72 | * | |
73 | * ATA-66/100 and recovery functions, I forgot the rest...... | |
74 | * | |
75 | */ | |
76 | ||
1da177e4 LT |
77 | #include <linux/module.h> |
78 | #include <linux/types.h> | |
79 | #include <linux/kernel.h> | |
80 | #include <linux/timer.h> | |
81 | #include <linux/mm.h> | |
82 | #include <linux/interrupt.h> | |
83 | #include <linux/pci.h> | |
84 | #include <linux/init.h> | |
85 | #include <linux/ide.h> | |
86 | #include <linux/delay.h> | |
87 | #include <linux/scatterlist.h> | |
88 | ||
89 | #include <asm/io.h> | |
90 | #include <asm/irq.h> | |
91 | ||
1da177e4 LT |
92 | static const struct drive_list_entry drive_whitelist [] = { |
93 | ||
94 | { "Micropolis 2112A" , "ALL" }, | |
95 | { "CONNER CTMA 4000" , "ALL" }, | |
96 | { "CONNER CTT8000-A" , "ALL" }, | |
97 | { "ST34342A" , "ALL" }, | |
98 | { NULL , NULL } | |
99 | }; | |
100 | ||
101 | static const struct drive_list_entry drive_blacklist [] = { | |
102 | ||
103 | { "WDC AC11000H" , "ALL" }, | |
104 | { "WDC AC22100H" , "ALL" }, | |
105 | { "WDC AC32500H" , "ALL" }, | |
106 | { "WDC AC33100H" , "ALL" }, | |
107 | { "WDC AC31600H" , "ALL" }, | |
108 | { "WDC AC32100H" , "24.09P07" }, | |
109 | { "WDC AC23200L" , "21.10N21" }, | |
110 | { "Compaq CRD-8241B" , "ALL" }, | |
111 | { "CRD-8400B" , "ALL" }, | |
112 | { "CRD-8480B", "ALL" }, | |
113 | { "CRD-8482B", "ALL" }, | |
114 | { "CRD-84" , "ALL" }, | |
115 | { "SanDisk SDP3B" , "ALL" }, | |
116 | { "SanDisk SDP3B-64" , "ALL" }, | |
117 | { "SANYO CD-ROM CRD" , "ALL" }, | |
118 | { "HITACHI CDR-8" , "ALL" }, | |
119 | { "HITACHI CDR-8335" , "ALL" }, | |
120 | { "HITACHI CDR-8435" , "ALL" }, | |
121 | { "Toshiba CD-ROM XM-6202B" , "ALL" }, | |
122 | { "CD-532E-A" , "ALL" }, | |
123 | { "E-IDE CD-ROM CR-840", "ALL" }, | |
124 | { "CD-ROM Drive/F5A", "ALL" }, | |
125 | { "WPI CDD-820", "ALL" }, | |
126 | { "SAMSUNG CD-ROM SC-148C", "ALL" }, | |
127 | { "SAMSUNG CD-ROM SC", "ALL" }, | |
128 | { "SanDisk SDP3B-64" , "ALL" }, | |
1da177e4 LT |
129 | { "ATAPI CD-ROM DRIVE 40X MAXIMUM", "ALL" }, |
130 | { "_NEC DV5800A", "ALL" }, | |
131 | { NULL , NULL } | |
132 | ||
133 | }; | |
134 | ||
135 | /** | |
65e5f2e3 | 136 | * ide_in_drive_list - look for drive in black/white list |
1da177e4 LT |
137 | * @id: drive identifier |
138 | * @drive_table: list to inspect | |
139 | * | |
140 | * Look for a drive in the blacklist and the whitelist tables | |
141 | * Returns 1 if the drive is found in the table. | |
142 | */ | |
143 | ||
65e5f2e3 | 144 | int ide_in_drive_list(struct hd_driveid *id, const struct drive_list_entry *drive_table) |
1da177e4 LT |
145 | { |
146 | for ( ; drive_table->id_model ; drive_table++) | |
147 | if ((!strcmp(drive_table->id_model, id->model)) && | |
14e0a193 | 148 | ((strstr(id->fw_rev, drive_table->id_firmware)) || |
1da177e4 LT |
149 | (!strcmp(drive_table->id_firmware, "ALL")))) |
150 | return 1; | |
151 | return 0; | |
152 | } | |
153 | ||
154 | /** | |
155 | * ide_dma_intr - IDE DMA interrupt handler | |
156 | * @drive: the drive the interrupt is for | |
157 | * | |
158 | * Handle an interrupt completing a read/write DMA transfer on an | |
159 | * IDE device | |
160 | */ | |
161 | ||
162 | ide_startstop_t ide_dma_intr (ide_drive_t *drive) | |
163 | { | |
164 | u8 stat = 0, dma_stat = 0; | |
165 | ||
166 | dma_stat = HWIF(drive)->ide_dma_end(drive); | |
167 | stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */ | |
168 | if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { | |
169 | if (!dma_stat) { | |
170 | struct request *rq = HWGROUP(drive)->rq; | |
171 | ||
172 | if (rq->rq_disk) { | |
173 | ide_driver_t *drv; | |
174 | ||
53b3531b | 175 | drv = *(ide_driver_t **)rq->rq_disk->private_data; |
1da177e4 LT |
176 | drv->end_request(drive, 1, rq->nr_sectors); |
177 | } else | |
178 | ide_end_request(drive, 1, rq->nr_sectors); | |
179 | return ide_stopped; | |
180 | } | |
181 | printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n", | |
182 | drive->name, dma_stat); | |
183 | } | |
184 | return ide_error(drive, "dma_intr", stat); | |
185 | } | |
186 | ||
187 | EXPORT_SYMBOL_GPL(ide_dma_intr); | |
188 | ||
189 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
190 | /** | |
191 | * ide_build_sglist - map IDE scatter gather for DMA I/O | |
192 | * @drive: the drive to build the DMA table for | |
193 | * @rq: the request holding the sg list | |
194 | * | |
195 | * Perform the PCI mapping magic necessary to access the source or | |
196 | * target buffers of a request via PCI DMA. The lower layers of the | |
197 | * kernel provide the necessary cache management so that we can | |
198 | * operate in a portable fashion | |
199 | */ | |
200 | ||
201 | int ide_build_sglist(ide_drive_t *drive, struct request *rq) | |
202 | { | |
203 | ide_hwif_t *hwif = HWIF(drive); | |
204 | struct scatterlist *sg = hwif->sg_table; | |
205 | ||
4aff5e23 | 206 | BUG_ON((rq->cmd_type == REQ_TYPE_ATA_TASKFILE) && rq->nr_sectors > 256); |
1da177e4 LT |
207 | |
208 | ide_map_sg(drive, rq); | |
209 | ||
210 | if (rq_data_dir(rq) == READ) | |
211 | hwif->sg_dma_direction = PCI_DMA_FROMDEVICE; | |
212 | else | |
213 | hwif->sg_dma_direction = PCI_DMA_TODEVICE; | |
214 | ||
215 | return pci_map_sg(hwif->pci_dev, sg, hwif->sg_nents, hwif->sg_dma_direction); | |
216 | } | |
217 | ||
218 | EXPORT_SYMBOL_GPL(ide_build_sglist); | |
219 | ||
220 | /** | |
221 | * ide_build_dmatable - build IDE DMA table | |
222 | * | |
223 | * ide_build_dmatable() prepares a dma request. We map the command | |
224 | * to get the pci bus addresses of the buffers and then build up | |
225 | * the PRD table that the IDE layer wants to be fed. The code | |
226 | * knows about the 64K wrap bug in the CS5530. | |
227 | * | |
228 | * Returns the number of built PRD entries if all went okay, | |
229 | * returns 0 otherwise. | |
230 | * | |
231 | * May also be invoked from trm290.c | |
232 | */ | |
233 | ||
234 | int ide_build_dmatable (ide_drive_t *drive, struct request *rq) | |
235 | { | |
236 | ide_hwif_t *hwif = HWIF(drive); | |
237 | unsigned int *table = hwif->dmatable_cpu; | |
238 | unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0; | |
239 | unsigned int count = 0; | |
240 | int i; | |
241 | struct scatterlist *sg; | |
242 | ||
243 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
244 | ||
245 | if (!i) | |
246 | return 0; | |
247 | ||
248 | sg = hwif->sg_table; | |
249 | while (i) { | |
250 | u32 cur_addr; | |
251 | u32 cur_len; | |
252 | ||
253 | cur_addr = sg_dma_address(sg); | |
254 | cur_len = sg_dma_len(sg); | |
255 | ||
256 | /* | |
257 | * Fill in the dma table, without crossing any 64kB boundaries. | |
258 | * Most hardware requires 16-bit alignment of all blocks, | |
259 | * but the trm290 requires 32-bit alignment. | |
260 | */ | |
261 | ||
262 | while (cur_len) { | |
263 | if (count++ >= PRD_ENTRIES) { | |
264 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
265 | goto use_pio_instead; | |
266 | } else { | |
267 | u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff); | |
268 | ||
269 | if (bcount > cur_len) | |
270 | bcount = cur_len; | |
271 | *table++ = cpu_to_le32(cur_addr); | |
272 | xcount = bcount & 0xffff; | |
273 | if (is_trm290) | |
274 | xcount = ((xcount >> 2) - 1) << 16; | |
275 | if (xcount == 0x0000) { | |
276 | /* | |
277 | * Most chipsets correctly interpret a length of 0x0000 as 64KB, | |
278 | * but at least one (e.g. CS5530) misinterprets it as zero (!). | |
279 | * So here we break the 64KB entry into two 32KB entries instead. | |
280 | */ | |
281 | if (count++ >= PRD_ENTRIES) { | |
282 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
283 | goto use_pio_instead; | |
284 | } | |
285 | *table++ = cpu_to_le32(0x8000); | |
286 | *table++ = cpu_to_le32(cur_addr + 0x8000); | |
287 | xcount = 0x8000; | |
288 | } | |
289 | *table++ = cpu_to_le32(xcount); | |
290 | cur_addr += bcount; | |
291 | cur_len -= bcount; | |
292 | } | |
293 | } | |
294 | ||
295 | sg++; | |
296 | i--; | |
297 | } | |
298 | ||
299 | if (count) { | |
300 | if (!is_trm290) | |
301 | *--table |= cpu_to_le32(0x80000000); | |
302 | return count; | |
303 | } | |
304 | printk(KERN_ERR "%s: empty DMA table?\n", drive->name); | |
305 | use_pio_instead: | |
306 | pci_unmap_sg(hwif->pci_dev, | |
307 | hwif->sg_table, | |
308 | hwif->sg_nents, | |
309 | hwif->sg_dma_direction); | |
310 | return 0; /* revert to PIO for this request */ | |
311 | } | |
312 | ||
313 | EXPORT_SYMBOL_GPL(ide_build_dmatable); | |
314 | ||
315 | /** | |
316 | * ide_destroy_dmatable - clean up DMA mapping | |
317 | * @drive: The drive to unmap | |
318 | * | |
319 | * Teardown mappings after DMA has completed. This must be called | |
320 | * after the completion of each use of ide_build_dmatable and before | |
321 | * the next use of ide_build_dmatable. Failure to do so will cause | |
322 | * an oops as only one mapping can be live for each target at a given | |
323 | * time. | |
324 | */ | |
325 | ||
326 | void ide_destroy_dmatable (ide_drive_t *drive) | |
327 | { | |
328 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
329 | struct scatterlist *sg = HWIF(drive)->sg_table; | |
330 | int nents = HWIF(drive)->sg_nents; | |
331 | ||
332 | pci_unmap_sg(dev, sg, nents, HWIF(drive)->sg_dma_direction); | |
333 | } | |
334 | ||
335 | EXPORT_SYMBOL_GPL(ide_destroy_dmatable); | |
336 | ||
337 | /** | |
338 | * config_drive_for_dma - attempt to activate IDE DMA | |
339 | * @drive: the drive to place in DMA mode | |
340 | * | |
341 | * If the drive supports at least mode 2 DMA or UDMA of any kind | |
342 | * then attempt to place it into DMA mode. Drives that are known to | |
343 | * support DMA but predate the DMA properties or that are known | |
344 | * to have DMA handling bugs are also set up appropriately based | |
345 | * on the good/bad drive lists. | |
346 | */ | |
347 | ||
348 | static int config_drive_for_dma (ide_drive_t *drive) | |
349 | { | |
350 | struct hd_driveid *id = drive->id; | |
1da177e4 | 351 | |
3608b5d7 | 352 | if ((id->capability & 1) && drive->hwif->autodma) { |
1da177e4 LT |
353 | /* |
354 | * Enable DMA on any drive that has | |
355 | * UltraDMA (mode 0/1/2/3/4/5/6) enabled | |
356 | */ | |
357 | if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f)) | |
3608b5d7 | 358 | return 0; |
1da177e4 LT |
359 | /* |
360 | * Enable DMA on any drive that has mode2 DMA | |
361 | * (multi or single) enabled | |
362 | */ | |
363 | if (id->field_valid & 2) /* regular DMA */ | |
364 | if ((id->dma_mword & 0x404) == 0x404 || | |
365 | (id->dma_1word & 0x404) == 0x404) | |
3608b5d7 | 366 | return 0; |
1da177e4 LT |
367 | |
368 | /* Consult the list of known "good" drives */ | |
369 | if (__ide_dma_good_drive(drive)) | |
3608b5d7 | 370 | return 0; |
1da177e4 | 371 | } |
3608b5d7 BZ |
372 | |
373 | return -1; | |
1da177e4 LT |
374 | } |
375 | ||
376 | /** | |
377 | * dma_timer_expiry - handle a DMA timeout | |
378 | * @drive: Drive that timed out | |
379 | * | |
380 | * An IDE DMA transfer timed out. In the event of an error we ask | |
381 | * the driver to resolve the problem, if a DMA transfer is still | |
382 | * in progress we continue to wait (arguably we need to add a | |
383 | * secondary 'I don't care what the drive thinks' timeout here) | |
384 | * Finally if we have an interrupt we let it complete the I/O. | |
385 | * But only one time - we clear expiry and if it's still not | |
386 | * completed after WAIT_CMD, we error and retry in PIO. | |
387 | * This can occur if an interrupt is lost or due to hang or bugs. | |
388 | */ | |
389 | ||
390 | static int dma_timer_expiry (ide_drive_t *drive) | |
391 | { | |
392 | ide_hwif_t *hwif = HWIF(drive); | |
393 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
394 | ||
395 | printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n", | |
396 | drive->name, dma_stat); | |
397 | ||
398 | if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ | |
399 | return WAIT_CMD; | |
400 | ||
401 | HWGROUP(drive)->expiry = NULL; /* one free ride for now */ | |
402 | ||
403 | /* 1 dmaing, 2 error, 4 intr */ | |
404 | if (dma_stat & 2) /* ERROR */ | |
405 | return -1; | |
406 | ||
407 | if (dma_stat & 1) /* DMAing */ | |
408 | return WAIT_CMD; | |
409 | ||
410 | if (dma_stat & 4) /* Got an Interrupt */ | |
411 | return WAIT_CMD; | |
412 | ||
413 | return 0; /* Status is unknown -- reset the bus */ | |
414 | } | |
415 | ||
416 | /** | |
7469aaf6 | 417 | * ide_dma_host_off - Generic DMA kill |
1da177e4 LT |
418 | * @drive: drive to control |
419 | * | |
420 | * Perform the generic IDE controller DMA off operation. This | |
421 | * works for most IDE bus mastering controllers | |
422 | */ | |
423 | ||
7469aaf6 | 424 | void ide_dma_host_off(ide_drive_t *drive) |
1da177e4 LT |
425 | { |
426 | ide_hwif_t *hwif = HWIF(drive); | |
427 | u8 unit = (drive->select.b.unit & 0x01); | |
428 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
429 | ||
430 | hwif->OUTB((dma_stat & ~(1<<(5+unit))), hwif->dma_status); | |
1da177e4 LT |
431 | } |
432 | ||
7469aaf6 | 433 | EXPORT_SYMBOL(ide_dma_host_off); |
1da177e4 LT |
434 | |
435 | /** | |
7469aaf6 | 436 | * ide_dma_off_quietly - Generic DMA kill |
1da177e4 LT |
437 | * @drive: drive to control |
438 | * | |
439 | * Turn off the current DMA on this IDE controller. | |
440 | */ | |
441 | ||
7469aaf6 | 442 | void ide_dma_off_quietly(ide_drive_t *drive) |
1da177e4 LT |
443 | { |
444 | drive->using_dma = 0; | |
445 | ide_toggle_bounce(drive, 0); | |
446 | ||
7469aaf6 | 447 | drive->hwif->dma_host_off(drive); |
1da177e4 LT |
448 | } |
449 | ||
7469aaf6 | 450 | EXPORT_SYMBOL(ide_dma_off_quietly); |
1da177e4 LT |
451 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
452 | ||
453 | /** | |
7469aaf6 | 454 | * ide_dma_off - disable DMA on a device |
1da177e4 LT |
455 | * @drive: drive to disable DMA on |
456 | * | |
457 | * Disable IDE DMA for a device on this IDE controller. | |
458 | * Inform the user that DMA has been disabled. | |
459 | */ | |
460 | ||
7469aaf6 | 461 | void ide_dma_off(ide_drive_t *drive) |
1da177e4 LT |
462 | { |
463 | printk(KERN_INFO "%s: DMA disabled\n", drive->name); | |
7469aaf6 | 464 | drive->hwif->dma_off_quietly(drive); |
1da177e4 LT |
465 | } |
466 | ||
7469aaf6 | 467 | EXPORT_SYMBOL(ide_dma_off); |
1da177e4 LT |
468 | |
469 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
470 | /** | |
ccf35289 | 471 | * ide_dma_host_on - Enable DMA on a host |
1da177e4 LT |
472 | * @drive: drive to enable for DMA |
473 | * | |
474 | * Enable DMA on an IDE controller following generic bus mastering | |
475 | * IDE controller behaviour | |
476 | */ | |
ccf35289 BZ |
477 | |
478 | void ide_dma_host_on(ide_drive_t *drive) | |
1da177e4 LT |
479 | { |
480 | if (drive->using_dma) { | |
481 | ide_hwif_t *hwif = HWIF(drive); | |
482 | u8 unit = (drive->select.b.unit & 0x01); | |
483 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
484 | ||
485 | hwif->OUTB((dma_stat|(1<<(5+unit))), hwif->dma_status); | |
1da177e4 | 486 | } |
1da177e4 LT |
487 | } |
488 | ||
ccf35289 | 489 | EXPORT_SYMBOL(ide_dma_host_on); |
1da177e4 LT |
490 | |
491 | /** | |
492 | * __ide_dma_on - Enable DMA on a device | |
493 | * @drive: drive to enable DMA on | |
494 | * | |
495 | * Enable IDE DMA for a device on this IDE controller. | |
496 | */ | |
497 | ||
498 | int __ide_dma_on (ide_drive_t *drive) | |
499 | { | |
500 | /* consult the list of known "bad" drives */ | |
501 | if (__ide_dma_bad_drive(drive)) | |
502 | return 1; | |
503 | ||
504 | drive->using_dma = 1; | |
505 | ide_toggle_bounce(drive, 1); | |
506 | ||
ccf35289 | 507 | drive->hwif->dma_host_on(drive); |
1da177e4 LT |
508 | |
509 | return 0; | |
510 | } | |
511 | ||
512 | EXPORT_SYMBOL(__ide_dma_on); | |
513 | ||
514 | /** | |
515 | * __ide_dma_check - check DMA setup | |
516 | * @drive: drive to check | |
517 | * | |
518 | * Don't use - due for extermination | |
519 | */ | |
520 | ||
521 | int __ide_dma_check (ide_drive_t *drive) | |
522 | { | |
523 | return config_drive_for_dma(drive); | |
524 | } | |
525 | ||
526 | EXPORT_SYMBOL(__ide_dma_check); | |
527 | ||
528 | /** | |
529 | * ide_dma_setup - begin a DMA phase | |
530 | * @drive: target device | |
531 | * | |
532 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
533 | * and then set up the DMA transfer registers for a device | |
534 | * that follows generic IDE PCI DMA behaviour. Controllers can | |
535 | * override this function if they need to | |
536 | * | |
537 | * Returns 0 on success. If a PIO fallback is required then 1 | |
538 | * is returned. | |
539 | */ | |
540 | ||
541 | int ide_dma_setup(ide_drive_t *drive) | |
542 | { | |
543 | ide_hwif_t *hwif = drive->hwif; | |
544 | struct request *rq = HWGROUP(drive)->rq; | |
545 | unsigned int reading; | |
546 | u8 dma_stat; | |
547 | ||
548 | if (rq_data_dir(rq)) | |
549 | reading = 0; | |
550 | else | |
551 | reading = 1 << 3; | |
552 | ||
553 | /* fall back to pio! */ | |
554 | if (!ide_build_dmatable(drive, rq)) { | |
555 | ide_map_sg(drive, rq); | |
556 | return 1; | |
557 | } | |
558 | ||
559 | /* PRD table */ | |
2ad1e558 | 560 | if (hwif->mmio) |
0ecdca26 BZ |
561 | writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable); |
562 | else | |
563 | outl(hwif->dmatable_dma, hwif->dma_prdtable); | |
1da177e4 LT |
564 | |
565 | /* specify r/w */ | |
566 | hwif->OUTB(reading, hwif->dma_command); | |
567 | ||
568 | /* read dma_status for INTR & ERROR flags */ | |
569 | dma_stat = hwif->INB(hwif->dma_status); | |
570 | ||
571 | /* clear INTR & ERROR flags */ | |
572 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
573 | drive->waiting_for_dma = 1; | |
574 | return 0; | |
575 | } | |
576 | ||
577 | EXPORT_SYMBOL_GPL(ide_dma_setup); | |
578 | ||
579 | static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) | |
580 | { | |
581 | /* issue cmd to drive */ | |
582 | ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry); | |
583 | } | |
584 | ||
585 | void ide_dma_start(ide_drive_t *drive) | |
586 | { | |
587 | ide_hwif_t *hwif = HWIF(drive); | |
588 | u8 dma_cmd = hwif->INB(hwif->dma_command); | |
589 | ||
590 | /* Note that this is done *after* the cmd has | |
591 | * been issued to the drive, as per the BM-IDE spec. | |
592 | * The Promise Ultra33 doesn't work correctly when | |
593 | * we do this part before issuing the drive cmd. | |
594 | */ | |
595 | /* start DMA */ | |
596 | hwif->OUTB(dma_cmd|1, hwif->dma_command); | |
597 | hwif->dma = 1; | |
598 | wmb(); | |
599 | } | |
600 | ||
601 | EXPORT_SYMBOL_GPL(ide_dma_start); | |
602 | ||
603 | /* returns 1 on error, 0 otherwise */ | |
604 | int __ide_dma_end (ide_drive_t *drive) | |
605 | { | |
606 | ide_hwif_t *hwif = HWIF(drive); | |
607 | u8 dma_stat = 0, dma_cmd = 0; | |
608 | ||
609 | drive->waiting_for_dma = 0; | |
610 | /* get dma_command mode */ | |
611 | dma_cmd = hwif->INB(hwif->dma_command); | |
612 | /* stop DMA */ | |
613 | hwif->OUTB(dma_cmd&~1, hwif->dma_command); | |
614 | /* get DMA status */ | |
615 | dma_stat = hwif->INB(hwif->dma_status); | |
616 | /* clear the INTR & ERROR bits */ | |
617 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
618 | /* purge DMA mappings */ | |
619 | ide_destroy_dmatable(drive); | |
620 | /* verify good DMA status */ | |
621 | hwif->dma = 0; | |
622 | wmb(); | |
623 | return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; | |
624 | } | |
625 | ||
626 | EXPORT_SYMBOL(__ide_dma_end); | |
627 | ||
628 | /* returns 1 if dma irq issued, 0 otherwise */ | |
629 | static int __ide_dma_test_irq(ide_drive_t *drive) | |
630 | { | |
631 | ide_hwif_t *hwif = HWIF(drive); | |
632 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
633 | ||
634 | #if 0 /* do not set unless you know what you are doing */ | |
635 | if (dma_stat & 4) { | |
636 | u8 stat = hwif->INB(IDE_STATUS_REG); | |
637 | hwif->OUTB(hwif->dma_status, dma_stat & 0xE4); | |
638 | } | |
639 | #endif | |
640 | /* return 1 if INTR asserted */ | |
641 | if ((dma_stat & 4) == 4) | |
642 | return 1; | |
643 | if (!drive->waiting_for_dma) | |
644 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
645 | drive->name, __FUNCTION__); | |
646 | return 0; | |
647 | } | |
648 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ | |
649 | ||
650 | int __ide_dma_bad_drive (ide_drive_t *drive) | |
651 | { | |
652 | struct hd_driveid *id = drive->id; | |
653 | ||
65e5f2e3 | 654 | int blacklist = ide_in_drive_list(id, drive_blacklist); |
1da177e4 LT |
655 | if (blacklist) { |
656 | printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", | |
657 | drive->name, id->model); | |
658 | return blacklist; | |
659 | } | |
660 | return 0; | |
661 | } | |
662 | ||
663 | EXPORT_SYMBOL(__ide_dma_bad_drive); | |
664 | ||
665 | int __ide_dma_good_drive (ide_drive_t *drive) | |
666 | { | |
667 | struct hd_driveid *id = drive->id; | |
65e5f2e3 | 668 | return ide_in_drive_list(id, drive_whitelist); |
1da177e4 LT |
669 | } |
670 | ||
671 | EXPORT_SYMBOL(__ide_dma_good_drive); | |
672 | ||
673 | int ide_use_dma(ide_drive_t *drive) | |
674 | { | |
675 | struct hd_driveid *id = drive->id; | |
676 | ide_hwif_t *hwif = drive->hwif; | |
677 | ||
7569e8dc BZ |
678 | if ((id->capability & 1) == 0 || drive->autodma == 0) |
679 | return 0; | |
680 | ||
1da177e4 LT |
681 | /* consult the list of known "bad" drives */ |
682 | if (__ide_dma_bad_drive(drive)) | |
683 | return 0; | |
684 | ||
685 | /* capable of UltraDMA modes */ | |
686 | if (id->field_valid & 4) { | |
687 | if (hwif->ultra_mask & id->dma_ultra) | |
688 | return 1; | |
689 | } | |
690 | ||
691 | /* capable of regular DMA modes */ | |
692 | if (id->field_valid & 2) { | |
693 | if (hwif->mwdma_mask & id->dma_mword) | |
694 | return 1; | |
695 | if (hwif->swdma_mask & id->dma_1word) | |
696 | return 1; | |
697 | } | |
698 | ||
699 | /* consult the list of known "good" drives */ | |
700 | if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150) | |
701 | return 1; | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
706 | EXPORT_SYMBOL_GPL(ide_use_dma); | |
707 | ||
2d5eaa6d BZ |
708 | static const u8 xfer_mode_bases[] = { |
709 | XFER_UDMA_0, | |
710 | XFER_MW_DMA_0, | |
711 | XFER_SW_DMA_0, | |
712 | }; | |
713 | ||
714 | static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base) | |
715 | { | |
716 | struct hd_driveid *id = drive->id; | |
717 | ide_hwif_t *hwif = drive->hwif; | |
718 | unsigned int mask = 0; | |
719 | ||
720 | switch(base) { | |
721 | case XFER_UDMA_0: | |
722 | if ((id->field_valid & 4) == 0) | |
723 | break; | |
724 | ||
725 | mask = id->dma_ultra & hwif->ultra_mask; | |
726 | ||
727 | if (hwif->udma_filter) | |
728 | mask &= hwif->udma_filter(drive); | |
729 | ||
730 | if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) | |
731 | mask &= 0x07; | |
732 | break; | |
733 | case XFER_MW_DMA_0: | |
734 | mask = id->dma_mword & hwif->mwdma_mask; | |
735 | break; | |
736 | case XFER_SW_DMA_0: | |
737 | mask = id->dma_1word & hwif->swdma_mask; | |
738 | break; | |
739 | default: | |
740 | BUG(); | |
741 | break; | |
742 | } | |
743 | ||
744 | return mask; | |
745 | } | |
746 | ||
747 | /** | |
748 | * ide_max_dma_mode - compute DMA speed | |
749 | * @drive: IDE device | |
750 | * | |
751 | * Checks the drive capabilities and returns the speed to use | |
752 | * for the DMA transfer. Returns 0 if the drive is incapable | |
753 | * of DMA transfers. | |
754 | */ | |
755 | ||
756 | u8 ide_max_dma_mode(ide_drive_t *drive) | |
757 | { | |
758 | ide_hwif_t *hwif = drive->hwif; | |
759 | unsigned int mask; | |
760 | int x, i; | |
761 | u8 mode = 0; | |
762 | ||
763 | if (drive->media != ide_disk && hwif->atapi_dma == 0) | |
764 | return 0; | |
765 | ||
766 | for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) { | |
767 | mask = ide_get_mode_mask(drive, xfer_mode_bases[i]); | |
768 | x = fls(mask) - 1; | |
769 | if (x >= 0) { | |
770 | mode = xfer_mode_bases[i] + x; | |
771 | break; | |
772 | } | |
773 | } | |
774 | ||
775 | printk(KERN_DEBUG "%s: selected mode 0x%x\n", drive->name, mode); | |
776 | ||
777 | return mode; | |
778 | } | |
779 | ||
780 | EXPORT_SYMBOL_GPL(ide_max_dma_mode); | |
781 | ||
1da177e4 LT |
782 | void ide_dma_verbose(ide_drive_t *drive) |
783 | { | |
784 | struct hd_driveid *id = drive->id; | |
785 | ide_hwif_t *hwif = HWIF(drive); | |
786 | ||
787 | if (id->field_valid & 4) { | |
788 | if ((id->dma_ultra >> 8) && (id->dma_mword >> 8)) | |
789 | goto bug_dma_off; | |
790 | if (id->dma_ultra & ((id->dma_ultra >> 8) & hwif->ultra_mask)) { | |
791 | if (((id->dma_ultra >> 11) & 0x1F) && | |
792 | eighty_ninty_three(drive)) { | |
793 | if ((id->dma_ultra >> 15) & 1) { | |
794 | printk(", UDMA(mode 7)"); | |
795 | } else if ((id->dma_ultra >> 14) & 1) { | |
796 | printk(", UDMA(133)"); | |
797 | } else if ((id->dma_ultra >> 13) & 1) { | |
798 | printk(", UDMA(100)"); | |
799 | } else if ((id->dma_ultra >> 12) & 1) { | |
800 | printk(", UDMA(66)"); | |
801 | } else if ((id->dma_ultra >> 11) & 1) { | |
802 | printk(", UDMA(44)"); | |
803 | } else | |
804 | goto mode_two; | |
805 | } else { | |
806 | mode_two: | |
807 | if ((id->dma_ultra >> 10) & 1) { | |
808 | printk(", UDMA(33)"); | |
809 | } else if ((id->dma_ultra >> 9) & 1) { | |
810 | printk(", UDMA(25)"); | |
811 | } else if ((id->dma_ultra >> 8) & 1) { | |
812 | printk(", UDMA(16)"); | |
813 | } | |
814 | } | |
815 | } else { | |
816 | printk(", (U)DMA"); /* Can be BIOS-enabled! */ | |
817 | } | |
818 | } else if (id->field_valid & 2) { | |
819 | if ((id->dma_mword >> 8) && (id->dma_1word >> 8)) | |
820 | goto bug_dma_off; | |
821 | printk(", DMA"); | |
822 | } else if (id->field_valid & 1) { | |
0a8348d0 | 823 | goto bug_dma_off; |
1da177e4 LT |
824 | } |
825 | return; | |
826 | bug_dma_off: | |
827 | printk(", BUG DMA OFF"); | |
7469aaf6 | 828 | hwif->dma_off_quietly(drive); |
1da177e4 LT |
829 | return; |
830 | } | |
831 | ||
832 | EXPORT_SYMBOL(ide_dma_verbose); | |
833 | ||
3608b5d7 BZ |
834 | int ide_set_dma(ide_drive_t *drive) |
835 | { | |
836 | ide_hwif_t *hwif = drive->hwif; | |
837 | int rc; | |
838 | ||
839 | rc = hwif->ide_dma_check(drive); | |
840 | ||
841 | switch(rc) { | |
842 | case -1: /* DMA needs to be disabled */ | |
7469aaf6 | 843 | hwif->dma_off_quietly(drive); |
6f5050a9 | 844 | return -1; |
3608b5d7 BZ |
845 | case 0: /* DMA needs to be enabled */ |
846 | return hwif->ide_dma_on(drive); | |
847 | case 1: /* DMA setting cannot be changed */ | |
848 | break; | |
849 | default: | |
850 | BUG(); | |
851 | break; | |
852 | } | |
853 | ||
854 | return rc; | |
855 | } | |
856 | ||
857 | EXPORT_SYMBOL_GPL(ide_set_dma); | |
858 | ||
1da177e4 LT |
859 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
860 | int __ide_dma_lostirq (ide_drive_t *drive) | |
861 | { | |
862 | printk("%s: DMA interrupt recovery\n", drive->name); | |
863 | return 1; | |
864 | } | |
865 | ||
866 | EXPORT_SYMBOL(__ide_dma_lostirq); | |
867 | ||
868 | int __ide_dma_timeout (ide_drive_t *drive) | |
869 | { | |
870 | printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); | |
871 | if (HWIF(drive)->ide_dma_test_irq(drive)) | |
872 | return 0; | |
873 | ||
874 | return HWIF(drive)->ide_dma_end(drive); | |
875 | } | |
876 | ||
877 | EXPORT_SYMBOL(__ide_dma_timeout); | |
878 | ||
879 | /* | |
880 | * Needed for allowing full modular support of ide-driver | |
881 | */ | |
882 | static int ide_release_dma_engine(ide_hwif_t *hwif) | |
883 | { | |
884 | if (hwif->dmatable_cpu) { | |
885 | pci_free_consistent(hwif->pci_dev, | |
886 | PRD_ENTRIES * PRD_BYTES, | |
887 | hwif->dmatable_cpu, | |
888 | hwif->dmatable_dma); | |
889 | hwif->dmatable_cpu = NULL; | |
890 | } | |
891 | return 1; | |
892 | } | |
893 | ||
894 | static int ide_release_iomio_dma(ide_hwif_t *hwif) | |
895 | { | |
1da177e4 | 896 | release_region(hwif->dma_base, 8); |
020e322d SS |
897 | if (hwif->extra_ports) |
898 | release_region(hwif->extra_base, hwif->extra_ports); | |
1da177e4 LT |
899 | return 1; |
900 | } | |
901 | ||
902 | /* | |
903 | * Needed for allowing full modular support of ide-driver | |
904 | */ | |
dc844e05 | 905 | int ide_release_dma(ide_hwif_t *hwif) |
1da177e4 | 906 | { |
dc844e05 SS |
907 | ide_release_dma_engine(hwif); |
908 | ||
2ad1e558 | 909 | if (hwif->mmio) |
1da177e4 | 910 | return 1; |
dc844e05 SS |
911 | else |
912 | return ide_release_iomio_dma(hwif); | |
1da177e4 LT |
913 | } |
914 | ||
915 | static int ide_allocate_dma_engine(ide_hwif_t *hwif) | |
916 | { | |
917 | hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev, | |
918 | PRD_ENTRIES * PRD_BYTES, | |
919 | &hwif->dmatable_dma); | |
920 | ||
921 | if (hwif->dmatable_cpu) | |
922 | return 0; | |
923 | ||
dc844e05 SS |
924 | printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n", |
925 | hwif->cds->name); | |
1da177e4 | 926 | |
1da177e4 LT |
927 | return 1; |
928 | } | |
929 | ||
930 | static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
931 | { | |
932 | printk(KERN_INFO " %s: MMIO-DMA ", hwif->name); | |
933 | ||
020e322d | 934 | hwif->dma_base = base; |
1da177e4 LT |
935 | |
936 | if(hwif->mate) | |
937 | hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base; | |
938 | else | |
939 | hwif->dma_master = base; | |
940 | return 0; | |
941 | } | |
942 | ||
943 | static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
944 | { | |
945 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx", | |
020e322d SS |
946 | hwif->name, base, base + ports - 1); |
947 | ||
1da177e4 LT |
948 | if (!request_region(base, ports, hwif->name)) { |
949 | printk(" -- Error, ports in use.\n"); | |
950 | return 1; | |
951 | } | |
020e322d | 952 | |
1da177e4 | 953 | hwif->dma_base = base; |
020e322d SS |
954 | |
955 | if (hwif->cds->extra) { | |
956 | hwif->extra_base = base + (hwif->channel ? 8 : 16); | |
957 | ||
958 | if (!hwif->mate || !hwif->mate->extra_ports) { | |
959 | if (!request_region(hwif->extra_base, | |
960 | hwif->cds->extra, hwif->cds->name)) { | |
961 | printk(" -- Error, extra ports in use.\n"); | |
962 | release_region(base, ports); | |
963 | return 1; | |
964 | } | |
965 | hwif->extra_ports = hwif->cds->extra; | |
966 | } | |
1da177e4 | 967 | } |
020e322d | 968 | |
1da177e4 | 969 | if(hwif->mate) |
3f63c5e8 | 970 | hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base:base; |
1da177e4 LT |
971 | else |
972 | hwif->dma_master = base; | |
1da177e4 LT |
973 | return 0; |
974 | } | |
975 | ||
976 | static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
977 | { | |
2ad1e558 | 978 | if (hwif->mmio) |
1da177e4 | 979 | return ide_mapped_mmio_dma(hwif, base,ports); |
2ad1e558 | 980 | |
1da177e4 LT |
981 | return ide_iomio_dma(hwif, base, ports); |
982 | } | |
983 | ||
984 | /* | |
985 | * This can be called for a dynamically installed interface. Don't __init it | |
986 | */ | |
987 | void ide_setup_dma (ide_hwif_t *hwif, unsigned long dma_base, unsigned int num_ports) | |
988 | { | |
989 | if (ide_dma_iobase(hwif, dma_base, num_ports)) | |
990 | return; | |
991 | ||
992 | if (ide_allocate_dma_engine(hwif)) { | |
993 | ide_release_dma(hwif); | |
994 | return; | |
995 | } | |
996 | ||
997 | if (!(hwif->dma_command)) | |
998 | hwif->dma_command = hwif->dma_base; | |
999 | if (!(hwif->dma_vendor1)) | |
1000 | hwif->dma_vendor1 = (hwif->dma_base + 1); | |
1001 | if (!(hwif->dma_status)) | |
1002 | hwif->dma_status = (hwif->dma_base + 2); | |
1003 | if (!(hwif->dma_vendor3)) | |
1004 | hwif->dma_vendor3 = (hwif->dma_base + 3); | |
1005 | if (!(hwif->dma_prdtable)) | |
1006 | hwif->dma_prdtable = (hwif->dma_base + 4); | |
1007 | ||
7469aaf6 BZ |
1008 | if (!hwif->dma_off_quietly) |
1009 | hwif->dma_off_quietly = &ide_dma_off_quietly; | |
1010 | if (!hwif->dma_host_off) | |
1011 | hwif->dma_host_off = &ide_dma_host_off; | |
1da177e4 LT |
1012 | if (!hwif->ide_dma_on) |
1013 | hwif->ide_dma_on = &__ide_dma_on; | |
ccf35289 BZ |
1014 | if (!hwif->dma_host_on) |
1015 | hwif->dma_host_on = &ide_dma_host_on; | |
1da177e4 LT |
1016 | if (!hwif->ide_dma_check) |
1017 | hwif->ide_dma_check = &__ide_dma_check; | |
1018 | if (!hwif->dma_setup) | |
1019 | hwif->dma_setup = &ide_dma_setup; | |
1020 | if (!hwif->dma_exec_cmd) | |
1021 | hwif->dma_exec_cmd = &ide_dma_exec_cmd; | |
1022 | if (!hwif->dma_start) | |
1023 | hwif->dma_start = &ide_dma_start; | |
1024 | if (!hwif->ide_dma_end) | |
1025 | hwif->ide_dma_end = &__ide_dma_end; | |
1026 | if (!hwif->ide_dma_test_irq) | |
1027 | hwif->ide_dma_test_irq = &__ide_dma_test_irq; | |
1028 | if (!hwif->ide_dma_timeout) | |
1029 | hwif->ide_dma_timeout = &__ide_dma_timeout; | |
1030 | if (!hwif->ide_dma_lostirq) | |
1031 | hwif->ide_dma_lostirq = &__ide_dma_lostirq; | |
1032 | ||
1033 | if (hwif->chipset != ide_trm290) { | |
1034 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
1035 | printk(", BIOS settings: %s:%s, %s:%s", | |
1036 | hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "pio", | |
1037 | hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "pio"); | |
1038 | } | |
1039 | printk("\n"); | |
1040 | ||
125e1874 | 1041 | BUG_ON(!hwif->dma_master); |
1da177e4 LT |
1042 | } |
1043 | ||
1044 | EXPORT_SYMBOL_GPL(ide_setup_dma); | |
1045 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |