]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/ide-dma.c Version 4.10 June 9, 2000 | |
3 | * | |
4 | * Copyright (c) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * May be copied or modified under the terms of the GNU General Public License | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Special Thanks to Mark for his Six years of work. | |
10 | * | |
11 | * Copyright (c) 1995-1998 Mark Lord | |
12 | * May be copied or modified under the terms of the GNU General Public License | |
13 | */ | |
14 | ||
15 | /* | |
16 | * This module provides support for the bus-master IDE DMA functions | |
17 | * of various PCI chipsets, including the Intel PIIX (i82371FB for | |
18 | * the 430 FX chipset), the PIIX3 (i82371SB for the 430 HX/VX and | |
19 | * 440 chipsets), and the PIIX4 (i82371AB for the 430 TX chipset) | |
20 | * ("PIIX" stands for "PCI ISA IDE Xcellerator"). | |
21 | * | |
22 | * Pretty much the same code works for other IDE PCI bus-mastering chipsets. | |
23 | * | |
24 | * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). | |
25 | * | |
26 | * By default, DMA support is prepared for use, but is currently enabled only | |
27 | * for drives which already have DMA enabled (UltraDMA or mode 2 multi/single), | |
28 | * or which are recognized as "good" (see table below). Drives with only mode0 | |
29 | * or mode1 (multi/single) DMA should also work with this chipset/driver | |
30 | * (eg. MC2112A) but are not enabled by default. | |
31 | * | |
32 | * Use "hdparm -i" to view modes supported by a given drive. | |
33 | * | |
34 | * The hdparm-3.5 (or later) utility can be used for manually enabling/disabling | |
35 | * DMA support, but must be (re-)compiled against this kernel version or later. | |
36 | * | |
37 | * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting. | |
38 | * If problems arise, ide.c will disable DMA operation after a few retries. | |
39 | * This error recovery mechanism works and has been extremely well exercised. | |
40 | * | |
41 | * IDE drives, depending on their vintage, may support several different modes | |
42 | * of DMA operation. The boot-time modes are indicated with a "*" in | |
43 | * the "hdparm -i" listing, and can be changed with *knowledgeable* use of | |
44 | * the "hdparm -X" feature. There is seldom a need to do this, as drives | |
45 | * normally power-up with their "best" PIO/DMA modes enabled. | |
46 | * | |
47 | * Testing has been done with a rather extensive number of drives, | |
48 | * with Quantum & Western Digital models generally outperforming the pack, | |
49 | * and Fujitsu & Conner (and some Seagate which are really Conner) drives | |
50 | * showing more lackluster throughput. | |
51 | * | |
52 | * Keep an eye on /var/adm/messages for "DMA disabled" messages. | |
53 | * | |
54 | * Some people have reported trouble with Intel Zappa motherboards. | |
55 | * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0, | |
56 | * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe | |
57 | * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this). | |
58 | * | |
59 | * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for | |
60 | * fixing the problem with the BIOS on some Acer motherboards. | |
61 | * | |
62 | * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing | |
63 | * "TX" chipset compatibility and for providing patches for the "TX" chipset. | |
64 | * | |
65 | * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack | |
66 | * at generic DMA -- his patches were referred to when preparing this code. | |
67 | * | |
68 | * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> | |
69 | * for supplying a Promise UDMA board & WD UDMA drive for this work! | |
70 | * | |
71 | * And, yes, Intel Zappa boards really *do* use both PIIX IDE ports. | |
72 | * | |
73 | * ATA-66/100 and recovery functions, I forgot the rest...... | |
74 | * | |
75 | */ | |
76 | ||
1da177e4 LT |
77 | #include <linux/module.h> |
78 | #include <linux/types.h> | |
79 | #include <linux/kernel.h> | |
80 | #include <linux/timer.h> | |
81 | #include <linux/mm.h> | |
82 | #include <linux/interrupt.h> | |
83 | #include <linux/pci.h> | |
84 | #include <linux/init.h> | |
85 | #include <linux/ide.h> | |
86 | #include <linux/delay.h> | |
87 | #include <linux/scatterlist.h> | |
88 | ||
89 | #include <asm/io.h> | |
90 | #include <asm/irq.h> | |
91 | ||
1da177e4 LT |
92 | static const struct drive_list_entry drive_whitelist [] = { |
93 | ||
c2d3ce8c JH |
94 | { "Micropolis 2112A" , NULL }, |
95 | { "CONNER CTMA 4000" , NULL }, | |
96 | { "CONNER CTT8000-A" , NULL }, | |
97 | { "ST34342A" , NULL }, | |
1da177e4 LT |
98 | { NULL , NULL } |
99 | }; | |
100 | ||
101 | static const struct drive_list_entry drive_blacklist [] = { | |
102 | ||
c2d3ce8c JH |
103 | { "WDC AC11000H" , NULL }, |
104 | { "WDC AC22100H" , NULL }, | |
105 | { "WDC AC32500H" , NULL }, | |
106 | { "WDC AC33100H" , NULL }, | |
107 | { "WDC AC31600H" , NULL }, | |
1da177e4 LT |
108 | { "WDC AC32100H" , "24.09P07" }, |
109 | { "WDC AC23200L" , "21.10N21" }, | |
c2d3ce8c JH |
110 | { "Compaq CRD-8241B" , NULL }, |
111 | { "CRD-8400B" , NULL }, | |
112 | { "CRD-8480B", NULL }, | |
113 | { "CRD-8482B", NULL }, | |
114 | { "CRD-84" , NULL }, | |
115 | { "SanDisk SDP3B" , NULL }, | |
116 | { "SanDisk SDP3B-64" , NULL }, | |
117 | { "SANYO CD-ROM CRD" , NULL }, | |
118 | { "HITACHI CDR-8" , NULL }, | |
119 | { "HITACHI CDR-8335" , NULL }, | |
120 | { "HITACHI CDR-8435" , NULL }, | |
121 | { "Toshiba CD-ROM XM-6202B" , NULL }, | |
122 | { "TOSHIBA CD-ROM XM-1702BC", NULL }, | |
123 | { "CD-532E-A" , NULL }, | |
124 | { "E-IDE CD-ROM CR-840", NULL }, | |
125 | { "CD-ROM Drive/F5A", NULL }, | |
126 | { "WPI CDD-820", NULL }, | |
127 | { "SAMSUNG CD-ROM SC-148C", NULL }, | |
128 | { "SAMSUNG CD-ROM SC", NULL }, | |
129 | { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL }, | |
130 | { "_NEC DV5800A", NULL }, | |
5a6248ca | 131 | { "SAMSUNG CD-ROM SN-124", "N001" }, |
c2d3ce8c | 132 | { "Seagate STT20000A", NULL }, |
1da177e4 LT |
133 | { NULL , NULL } |
134 | ||
135 | }; | |
136 | ||
137 | /** | |
65e5f2e3 | 138 | * ide_in_drive_list - look for drive in black/white list |
1da177e4 LT |
139 | * @id: drive identifier |
140 | * @drive_table: list to inspect | |
141 | * | |
142 | * Look for a drive in the blacklist and the whitelist tables | |
143 | * Returns 1 if the drive is found in the table. | |
144 | */ | |
145 | ||
65e5f2e3 | 146 | int ide_in_drive_list(struct hd_driveid *id, const struct drive_list_entry *drive_table) |
1da177e4 LT |
147 | { |
148 | for ( ; drive_table->id_model ; drive_table++) | |
149 | if ((!strcmp(drive_table->id_model, id->model)) && | |
c2d3ce8c JH |
150 | (!drive_table->id_firmware || |
151 | !strcmp(drive_table->id_firmware, "ALL") || /* to be removed later */ | |
152 | strstr(id->fw_rev, drive_table->id_firmware))) | |
1da177e4 LT |
153 | return 1; |
154 | return 0; | |
155 | } | |
156 | ||
157 | /** | |
158 | * ide_dma_intr - IDE DMA interrupt handler | |
159 | * @drive: the drive the interrupt is for | |
160 | * | |
161 | * Handle an interrupt completing a read/write DMA transfer on an | |
162 | * IDE device | |
163 | */ | |
164 | ||
165 | ide_startstop_t ide_dma_intr (ide_drive_t *drive) | |
166 | { | |
167 | u8 stat = 0, dma_stat = 0; | |
168 | ||
169 | dma_stat = HWIF(drive)->ide_dma_end(drive); | |
170 | stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */ | |
171 | if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { | |
172 | if (!dma_stat) { | |
173 | struct request *rq = HWGROUP(drive)->rq; | |
174 | ||
175 | if (rq->rq_disk) { | |
176 | ide_driver_t *drv; | |
177 | ||
53b3531b | 178 | drv = *(ide_driver_t **)rq->rq_disk->private_data; |
1da177e4 LT |
179 | drv->end_request(drive, 1, rq->nr_sectors); |
180 | } else | |
181 | ide_end_request(drive, 1, rq->nr_sectors); | |
182 | return ide_stopped; | |
183 | } | |
184 | printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n", | |
185 | drive->name, dma_stat); | |
186 | } | |
187 | return ide_error(drive, "dma_intr", stat); | |
188 | } | |
189 | ||
190 | EXPORT_SYMBOL_GPL(ide_dma_intr); | |
191 | ||
192 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
193 | /** | |
194 | * ide_build_sglist - map IDE scatter gather for DMA I/O | |
195 | * @drive: the drive to build the DMA table for | |
196 | * @rq: the request holding the sg list | |
197 | * | |
198 | * Perform the PCI mapping magic necessary to access the source or | |
199 | * target buffers of a request via PCI DMA. The lower layers of the | |
200 | * kernel provide the necessary cache management so that we can | |
201 | * operate in a portable fashion | |
202 | */ | |
203 | ||
204 | int ide_build_sglist(ide_drive_t *drive, struct request *rq) | |
205 | { | |
206 | ide_hwif_t *hwif = HWIF(drive); | |
207 | struct scatterlist *sg = hwif->sg_table; | |
208 | ||
4aff5e23 | 209 | BUG_ON((rq->cmd_type == REQ_TYPE_ATA_TASKFILE) && rq->nr_sectors > 256); |
1da177e4 LT |
210 | |
211 | ide_map_sg(drive, rq); | |
212 | ||
213 | if (rq_data_dir(rq) == READ) | |
214 | hwif->sg_dma_direction = PCI_DMA_FROMDEVICE; | |
215 | else | |
216 | hwif->sg_dma_direction = PCI_DMA_TODEVICE; | |
217 | ||
218 | return pci_map_sg(hwif->pci_dev, sg, hwif->sg_nents, hwif->sg_dma_direction); | |
219 | } | |
220 | ||
221 | EXPORT_SYMBOL_GPL(ide_build_sglist); | |
222 | ||
223 | /** | |
224 | * ide_build_dmatable - build IDE DMA table | |
225 | * | |
226 | * ide_build_dmatable() prepares a dma request. We map the command | |
227 | * to get the pci bus addresses of the buffers and then build up | |
228 | * the PRD table that the IDE layer wants to be fed. The code | |
229 | * knows about the 64K wrap bug in the CS5530. | |
230 | * | |
231 | * Returns the number of built PRD entries if all went okay, | |
232 | * returns 0 otherwise. | |
233 | * | |
234 | * May also be invoked from trm290.c | |
235 | */ | |
236 | ||
237 | int ide_build_dmatable (ide_drive_t *drive, struct request *rq) | |
238 | { | |
239 | ide_hwif_t *hwif = HWIF(drive); | |
240 | unsigned int *table = hwif->dmatable_cpu; | |
241 | unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0; | |
242 | unsigned int count = 0; | |
243 | int i; | |
244 | struct scatterlist *sg; | |
245 | ||
246 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
247 | ||
248 | if (!i) | |
249 | return 0; | |
250 | ||
251 | sg = hwif->sg_table; | |
252 | while (i) { | |
253 | u32 cur_addr; | |
254 | u32 cur_len; | |
255 | ||
256 | cur_addr = sg_dma_address(sg); | |
257 | cur_len = sg_dma_len(sg); | |
258 | ||
259 | /* | |
260 | * Fill in the dma table, without crossing any 64kB boundaries. | |
261 | * Most hardware requires 16-bit alignment of all blocks, | |
262 | * but the trm290 requires 32-bit alignment. | |
263 | */ | |
264 | ||
265 | while (cur_len) { | |
266 | if (count++ >= PRD_ENTRIES) { | |
267 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
268 | goto use_pio_instead; | |
269 | } else { | |
270 | u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff); | |
271 | ||
272 | if (bcount > cur_len) | |
273 | bcount = cur_len; | |
274 | *table++ = cpu_to_le32(cur_addr); | |
275 | xcount = bcount & 0xffff; | |
276 | if (is_trm290) | |
277 | xcount = ((xcount >> 2) - 1) << 16; | |
278 | if (xcount == 0x0000) { | |
279 | /* | |
280 | * Most chipsets correctly interpret a length of 0x0000 as 64KB, | |
281 | * but at least one (e.g. CS5530) misinterprets it as zero (!). | |
282 | * So here we break the 64KB entry into two 32KB entries instead. | |
283 | */ | |
284 | if (count++ >= PRD_ENTRIES) { | |
285 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
286 | goto use_pio_instead; | |
287 | } | |
288 | *table++ = cpu_to_le32(0x8000); | |
289 | *table++ = cpu_to_le32(cur_addr + 0x8000); | |
290 | xcount = 0x8000; | |
291 | } | |
292 | *table++ = cpu_to_le32(xcount); | |
293 | cur_addr += bcount; | |
294 | cur_len -= bcount; | |
295 | } | |
296 | } | |
297 | ||
298 | sg++; | |
299 | i--; | |
300 | } | |
301 | ||
302 | if (count) { | |
303 | if (!is_trm290) | |
304 | *--table |= cpu_to_le32(0x80000000); | |
305 | return count; | |
306 | } | |
307 | printk(KERN_ERR "%s: empty DMA table?\n", drive->name); | |
308 | use_pio_instead: | |
309 | pci_unmap_sg(hwif->pci_dev, | |
310 | hwif->sg_table, | |
311 | hwif->sg_nents, | |
312 | hwif->sg_dma_direction); | |
313 | return 0; /* revert to PIO for this request */ | |
314 | } | |
315 | ||
316 | EXPORT_SYMBOL_GPL(ide_build_dmatable); | |
317 | ||
318 | /** | |
319 | * ide_destroy_dmatable - clean up DMA mapping | |
320 | * @drive: The drive to unmap | |
321 | * | |
322 | * Teardown mappings after DMA has completed. This must be called | |
323 | * after the completion of each use of ide_build_dmatable and before | |
324 | * the next use of ide_build_dmatable. Failure to do so will cause | |
325 | * an oops as only one mapping can be live for each target at a given | |
326 | * time. | |
327 | */ | |
328 | ||
329 | void ide_destroy_dmatable (ide_drive_t *drive) | |
330 | { | |
331 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
332 | struct scatterlist *sg = HWIF(drive)->sg_table; | |
333 | int nents = HWIF(drive)->sg_nents; | |
334 | ||
335 | pci_unmap_sg(dev, sg, nents, HWIF(drive)->sg_dma_direction); | |
336 | } | |
337 | ||
338 | EXPORT_SYMBOL_GPL(ide_destroy_dmatable); | |
339 | ||
340 | /** | |
341 | * config_drive_for_dma - attempt to activate IDE DMA | |
342 | * @drive: the drive to place in DMA mode | |
343 | * | |
344 | * If the drive supports at least mode 2 DMA or UDMA of any kind | |
345 | * then attempt to place it into DMA mode. Drives that are known to | |
346 | * support DMA but predate the DMA properties or that are known | |
347 | * to have DMA handling bugs are also set up appropriately based | |
348 | * on the good/bad drive lists. | |
349 | */ | |
350 | ||
351 | static int config_drive_for_dma (ide_drive_t *drive) | |
352 | { | |
353 | struct hd_driveid *id = drive->id; | |
1da177e4 | 354 | |
3608b5d7 | 355 | if ((id->capability & 1) && drive->hwif->autodma) { |
1da177e4 LT |
356 | /* |
357 | * Enable DMA on any drive that has | |
358 | * UltraDMA (mode 0/1/2/3/4/5/6) enabled | |
359 | */ | |
360 | if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f)) | |
3608b5d7 | 361 | return 0; |
1da177e4 LT |
362 | /* |
363 | * Enable DMA on any drive that has mode2 DMA | |
364 | * (multi or single) enabled | |
365 | */ | |
366 | if (id->field_valid & 2) /* regular DMA */ | |
367 | if ((id->dma_mword & 0x404) == 0x404 || | |
368 | (id->dma_1word & 0x404) == 0x404) | |
3608b5d7 | 369 | return 0; |
1da177e4 LT |
370 | |
371 | /* Consult the list of known "good" drives */ | |
372 | if (__ide_dma_good_drive(drive)) | |
3608b5d7 | 373 | return 0; |
1da177e4 | 374 | } |
3608b5d7 BZ |
375 | |
376 | return -1; | |
1da177e4 LT |
377 | } |
378 | ||
379 | /** | |
380 | * dma_timer_expiry - handle a DMA timeout | |
381 | * @drive: Drive that timed out | |
382 | * | |
383 | * An IDE DMA transfer timed out. In the event of an error we ask | |
384 | * the driver to resolve the problem, if a DMA transfer is still | |
385 | * in progress we continue to wait (arguably we need to add a | |
386 | * secondary 'I don't care what the drive thinks' timeout here) | |
387 | * Finally if we have an interrupt we let it complete the I/O. | |
388 | * But only one time - we clear expiry and if it's still not | |
389 | * completed after WAIT_CMD, we error and retry in PIO. | |
390 | * This can occur if an interrupt is lost or due to hang or bugs. | |
391 | */ | |
392 | ||
393 | static int dma_timer_expiry (ide_drive_t *drive) | |
394 | { | |
395 | ide_hwif_t *hwif = HWIF(drive); | |
396 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
397 | ||
398 | printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n", | |
399 | drive->name, dma_stat); | |
400 | ||
401 | if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ | |
402 | return WAIT_CMD; | |
403 | ||
404 | HWGROUP(drive)->expiry = NULL; /* one free ride for now */ | |
405 | ||
406 | /* 1 dmaing, 2 error, 4 intr */ | |
407 | if (dma_stat & 2) /* ERROR */ | |
408 | return -1; | |
409 | ||
410 | if (dma_stat & 1) /* DMAing */ | |
411 | return WAIT_CMD; | |
412 | ||
413 | if (dma_stat & 4) /* Got an Interrupt */ | |
414 | return WAIT_CMD; | |
415 | ||
416 | return 0; /* Status is unknown -- reset the bus */ | |
417 | } | |
418 | ||
419 | /** | |
7469aaf6 | 420 | * ide_dma_host_off - Generic DMA kill |
1da177e4 LT |
421 | * @drive: drive to control |
422 | * | |
423 | * Perform the generic IDE controller DMA off operation. This | |
424 | * works for most IDE bus mastering controllers | |
425 | */ | |
426 | ||
7469aaf6 | 427 | void ide_dma_host_off(ide_drive_t *drive) |
1da177e4 LT |
428 | { |
429 | ide_hwif_t *hwif = HWIF(drive); | |
430 | u8 unit = (drive->select.b.unit & 0x01); | |
431 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
432 | ||
433 | hwif->OUTB((dma_stat & ~(1<<(5+unit))), hwif->dma_status); | |
1da177e4 LT |
434 | } |
435 | ||
7469aaf6 | 436 | EXPORT_SYMBOL(ide_dma_host_off); |
1da177e4 LT |
437 | |
438 | /** | |
7469aaf6 | 439 | * ide_dma_off_quietly - Generic DMA kill |
1da177e4 LT |
440 | * @drive: drive to control |
441 | * | |
442 | * Turn off the current DMA on this IDE controller. | |
443 | */ | |
444 | ||
7469aaf6 | 445 | void ide_dma_off_quietly(ide_drive_t *drive) |
1da177e4 LT |
446 | { |
447 | drive->using_dma = 0; | |
448 | ide_toggle_bounce(drive, 0); | |
449 | ||
7469aaf6 | 450 | drive->hwif->dma_host_off(drive); |
1da177e4 LT |
451 | } |
452 | ||
7469aaf6 | 453 | EXPORT_SYMBOL(ide_dma_off_quietly); |
1da177e4 LT |
454 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
455 | ||
456 | /** | |
7469aaf6 | 457 | * ide_dma_off - disable DMA on a device |
1da177e4 LT |
458 | * @drive: drive to disable DMA on |
459 | * | |
460 | * Disable IDE DMA for a device on this IDE controller. | |
461 | * Inform the user that DMA has been disabled. | |
462 | */ | |
463 | ||
7469aaf6 | 464 | void ide_dma_off(ide_drive_t *drive) |
1da177e4 LT |
465 | { |
466 | printk(KERN_INFO "%s: DMA disabled\n", drive->name); | |
7469aaf6 | 467 | drive->hwif->dma_off_quietly(drive); |
1da177e4 LT |
468 | } |
469 | ||
7469aaf6 | 470 | EXPORT_SYMBOL(ide_dma_off); |
1da177e4 LT |
471 | |
472 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
473 | /** | |
ccf35289 | 474 | * ide_dma_host_on - Enable DMA on a host |
1da177e4 LT |
475 | * @drive: drive to enable for DMA |
476 | * | |
477 | * Enable DMA on an IDE controller following generic bus mastering | |
478 | * IDE controller behaviour | |
479 | */ | |
ccf35289 BZ |
480 | |
481 | void ide_dma_host_on(ide_drive_t *drive) | |
1da177e4 LT |
482 | { |
483 | if (drive->using_dma) { | |
484 | ide_hwif_t *hwif = HWIF(drive); | |
485 | u8 unit = (drive->select.b.unit & 0x01); | |
486 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
487 | ||
488 | hwif->OUTB((dma_stat|(1<<(5+unit))), hwif->dma_status); | |
1da177e4 | 489 | } |
1da177e4 LT |
490 | } |
491 | ||
ccf35289 | 492 | EXPORT_SYMBOL(ide_dma_host_on); |
1da177e4 LT |
493 | |
494 | /** | |
495 | * __ide_dma_on - Enable DMA on a device | |
496 | * @drive: drive to enable DMA on | |
497 | * | |
498 | * Enable IDE DMA for a device on this IDE controller. | |
499 | */ | |
500 | ||
501 | int __ide_dma_on (ide_drive_t *drive) | |
502 | { | |
503 | /* consult the list of known "bad" drives */ | |
504 | if (__ide_dma_bad_drive(drive)) | |
505 | return 1; | |
506 | ||
507 | drive->using_dma = 1; | |
508 | ide_toggle_bounce(drive, 1); | |
509 | ||
ccf35289 | 510 | drive->hwif->dma_host_on(drive); |
1da177e4 LT |
511 | |
512 | return 0; | |
513 | } | |
514 | ||
515 | EXPORT_SYMBOL(__ide_dma_on); | |
516 | ||
517 | /** | |
518 | * __ide_dma_check - check DMA setup | |
519 | * @drive: drive to check | |
520 | * | |
521 | * Don't use - due for extermination | |
522 | */ | |
523 | ||
524 | int __ide_dma_check (ide_drive_t *drive) | |
525 | { | |
526 | return config_drive_for_dma(drive); | |
527 | } | |
528 | ||
529 | EXPORT_SYMBOL(__ide_dma_check); | |
530 | ||
531 | /** | |
532 | * ide_dma_setup - begin a DMA phase | |
533 | * @drive: target device | |
534 | * | |
535 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
536 | * and then set up the DMA transfer registers for a device | |
537 | * that follows generic IDE PCI DMA behaviour. Controllers can | |
538 | * override this function if they need to | |
539 | * | |
540 | * Returns 0 on success. If a PIO fallback is required then 1 | |
541 | * is returned. | |
542 | */ | |
543 | ||
544 | int ide_dma_setup(ide_drive_t *drive) | |
545 | { | |
546 | ide_hwif_t *hwif = drive->hwif; | |
547 | struct request *rq = HWGROUP(drive)->rq; | |
548 | unsigned int reading; | |
549 | u8 dma_stat; | |
550 | ||
551 | if (rq_data_dir(rq)) | |
552 | reading = 0; | |
553 | else | |
554 | reading = 1 << 3; | |
555 | ||
556 | /* fall back to pio! */ | |
557 | if (!ide_build_dmatable(drive, rq)) { | |
558 | ide_map_sg(drive, rq); | |
559 | return 1; | |
560 | } | |
561 | ||
562 | /* PRD table */ | |
2ad1e558 | 563 | if (hwif->mmio) |
0ecdca26 BZ |
564 | writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable); |
565 | else | |
566 | outl(hwif->dmatable_dma, hwif->dma_prdtable); | |
1da177e4 LT |
567 | |
568 | /* specify r/w */ | |
569 | hwif->OUTB(reading, hwif->dma_command); | |
570 | ||
571 | /* read dma_status for INTR & ERROR flags */ | |
572 | dma_stat = hwif->INB(hwif->dma_status); | |
573 | ||
574 | /* clear INTR & ERROR flags */ | |
575 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
576 | drive->waiting_for_dma = 1; | |
577 | return 0; | |
578 | } | |
579 | ||
580 | EXPORT_SYMBOL_GPL(ide_dma_setup); | |
581 | ||
582 | static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) | |
583 | { | |
584 | /* issue cmd to drive */ | |
585 | ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry); | |
586 | } | |
587 | ||
588 | void ide_dma_start(ide_drive_t *drive) | |
589 | { | |
590 | ide_hwif_t *hwif = HWIF(drive); | |
591 | u8 dma_cmd = hwif->INB(hwif->dma_command); | |
592 | ||
593 | /* Note that this is done *after* the cmd has | |
594 | * been issued to the drive, as per the BM-IDE spec. | |
595 | * The Promise Ultra33 doesn't work correctly when | |
596 | * we do this part before issuing the drive cmd. | |
597 | */ | |
598 | /* start DMA */ | |
599 | hwif->OUTB(dma_cmd|1, hwif->dma_command); | |
600 | hwif->dma = 1; | |
601 | wmb(); | |
602 | } | |
603 | ||
604 | EXPORT_SYMBOL_GPL(ide_dma_start); | |
605 | ||
606 | /* returns 1 on error, 0 otherwise */ | |
607 | int __ide_dma_end (ide_drive_t *drive) | |
608 | { | |
609 | ide_hwif_t *hwif = HWIF(drive); | |
610 | u8 dma_stat = 0, dma_cmd = 0; | |
611 | ||
612 | drive->waiting_for_dma = 0; | |
613 | /* get dma_command mode */ | |
614 | dma_cmd = hwif->INB(hwif->dma_command); | |
615 | /* stop DMA */ | |
616 | hwif->OUTB(dma_cmd&~1, hwif->dma_command); | |
617 | /* get DMA status */ | |
618 | dma_stat = hwif->INB(hwif->dma_status); | |
619 | /* clear the INTR & ERROR bits */ | |
620 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
621 | /* purge DMA mappings */ | |
622 | ide_destroy_dmatable(drive); | |
623 | /* verify good DMA status */ | |
624 | hwif->dma = 0; | |
625 | wmb(); | |
626 | return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; | |
627 | } | |
628 | ||
629 | EXPORT_SYMBOL(__ide_dma_end); | |
630 | ||
631 | /* returns 1 if dma irq issued, 0 otherwise */ | |
632 | static int __ide_dma_test_irq(ide_drive_t *drive) | |
633 | { | |
634 | ide_hwif_t *hwif = HWIF(drive); | |
635 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
636 | ||
637 | #if 0 /* do not set unless you know what you are doing */ | |
638 | if (dma_stat & 4) { | |
639 | u8 stat = hwif->INB(IDE_STATUS_REG); | |
640 | hwif->OUTB(hwif->dma_status, dma_stat & 0xE4); | |
641 | } | |
642 | #endif | |
643 | /* return 1 if INTR asserted */ | |
644 | if ((dma_stat & 4) == 4) | |
645 | return 1; | |
646 | if (!drive->waiting_for_dma) | |
647 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
648 | drive->name, __FUNCTION__); | |
649 | return 0; | |
650 | } | |
651 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ | |
652 | ||
653 | int __ide_dma_bad_drive (ide_drive_t *drive) | |
654 | { | |
655 | struct hd_driveid *id = drive->id; | |
656 | ||
65e5f2e3 | 657 | int blacklist = ide_in_drive_list(id, drive_blacklist); |
1da177e4 LT |
658 | if (blacklist) { |
659 | printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", | |
660 | drive->name, id->model); | |
661 | return blacklist; | |
662 | } | |
663 | return 0; | |
664 | } | |
665 | ||
666 | EXPORT_SYMBOL(__ide_dma_bad_drive); | |
667 | ||
668 | int __ide_dma_good_drive (ide_drive_t *drive) | |
669 | { | |
670 | struct hd_driveid *id = drive->id; | |
65e5f2e3 | 671 | return ide_in_drive_list(id, drive_whitelist); |
1da177e4 LT |
672 | } |
673 | ||
674 | EXPORT_SYMBOL(__ide_dma_good_drive); | |
675 | ||
2d5eaa6d BZ |
676 | static const u8 xfer_mode_bases[] = { |
677 | XFER_UDMA_0, | |
678 | XFER_MW_DMA_0, | |
679 | XFER_SW_DMA_0, | |
680 | }; | |
681 | ||
682 | static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base) | |
683 | { | |
684 | struct hd_driveid *id = drive->id; | |
685 | ide_hwif_t *hwif = drive->hwif; | |
686 | unsigned int mask = 0; | |
687 | ||
688 | switch(base) { | |
689 | case XFER_UDMA_0: | |
690 | if ((id->field_valid & 4) == 0) | |
691 | break; | |
692 | ||
693 | mask = id->dma_ultra & hwif->ultra_mask; | |
694 | ||
695 | if (hwif->udma_filter) | |
696 | mask &= hwif->udma_filter(drive); | |
697 | ||
698 | if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) | |
699 | mask &= 0x07; | |
700 | break; | |
701 | case XFER_MW_DMA_0: | |
3649c06e BZ |
702 | if (id->field_valid & 2) |
703 | mask = id->dma_mword & hwif->mwdma_mask; | |
2d5eaa6d BZ |
704 | break; |
705 | case XFER_SW_DMA_0: | |
3649c06e BZ |
706 | if (id->field_valid & 2) |
707 | mask = id->dma_1word & hwif->swdma_mask; | |
2d5eaa6d BZ |
708 | break; |
709 | default: | |
710 | BUG(); | |
711 | break; | |
712 | } | |
713 | ||
714 | return mask; | |
715 | } | |
716 | ||
717 | /** | |
718 | * ide_max_dma_mode - compute DMA speed | |
719 | * @drive: IDE device | |
720 | * | |
721 | * Checks the drive capabilities and returns the speed to use | |
722 | * for the DMA transfer. Returns 0 if the drive is incapable | |
723 | * of DMA transfers. | |
724 | */ | |
725 | ||
726 | u8 ide_max_dma_mode(ide_drive_t *drive) | |
727 | { | |
728 | ide_hwif_t *hwif = drive->hwif; | |
729 | unsigned int mask; | |
730 | int x, i; | |
731 | u8 mode = 0; | |
732 | ||
733 | if (drive->media != ide_disk && hwif->atapi_dma == 0) | |
734 | return 0; | |
735 | ||
736 | for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) { | |
737 | mask = ide_get_mode_mask(drive, xfer_mode_bases[i]); | |
738 | x = fls(mask) - 1; | |
739 | if (x >= 0) { | |
740 | mode = xfer_mode_bases[i] + x; | |
741 | break; | |
742 | } | |
743 | } | |
744 | ||
745 | printk(KERN_DEBUG "%s: selected mode 0x%x\n", drive->name, mode); | |
746 | ||
747 | return mode; | |
748 | } | |
749 | ||
750 | EXPORT_SYMBOL_GPL(ide_max_dma_mode); | |
751 | ||
29e744d0 BZ |
752 | int ide_tune_dma(ide_drive_t *drive) |
753 | { | |
754 | u8 speed; | |
755 | ||
122ab088 BZ |
756 | if ((drive->id->capability & 1) == 0 || drive->autodma == 0) |
757 | return 0; | |
758 | ||
759 | /* consult the list of known "bad" drives */ | |
760 | if (__ide_dma_bad_drive(drive)) | |
29e744d0 BZ |
761 | return 0; |
762 | ||
763 | speed = ide_max_dma_mode(drive); | |
764 | ||
765 | if (!speed) | |
766 | return 0; | |
767 | ||
4728d546 BZ |
768 | if (drive->hwif->speedproc(drive, speed)) |
769 | return 0; | |
29e744d0 | 770 | |
4728d546 | 771 | return 1; |
29e744d0 BZ |
772 | } |
773 | ||
774 | EXPORT_SYMBOL_GPL(ide_tune_dma); | |
775 | ||
1da177e4 LT |
776 | void ide_dma_verbose(ide_drive_t *drive) |
777 | { | |
778 | struct hd_driveid *id = drive->id; | |
779 | ide_hwif_t *hwif = HWIF(drive); | |
780 | ||
781 | if (id->field_valid & 4) { | |
782 | if ((id->dma_ultra >> 8) && (id->dma_mword >> 8)) | |
783 | goto bug_dma_off; | |
784 | if (id->dma_ultra & ((id->dma_ultra >> 8) & hwif->ultra_mask)) { | |
785 | if (((id->dma_ultra >> 11) & 0x1F) && | |
786 | eighty_ninty_three(drive)) { | |
787 | if ((id->dma_ultra >> 15) & 1) { | |
788 | printk(", UDMA(mode 7)"); | |
789 | } else if ((id->dma_ultra >> 14) & 1) { | |
790 | printk(", UDMA(133)"); | |
791 | } else if ((id->dma_ultra >> 13) & 1) { | |
792 | printk(", UDMA(100)"); | |
793 | } else if ((id->dma_ultra >> 12) & 1) { | |
794 | printk(", UDMA(66)"); | |
795 | } else if ((id->dma_ultra >> 11) & 1) { | |
796 | printk(", UDMA(44)"); | |
797 | } else | |
798 | goto mode_two; | |
799 | } else { | |
800 | mode_two: | |
801 | if ((id->dma_ultra >> 10) & 1) { | |
802 | printk(", UDMA(33)"); | |
803 | } else if ((id->dma_ultra >> 9) & 1) { | |
804 | printk(", UDMA(25)"); | |
805 | } else if ((id->dma_ultra >> 8) & 1) { | |
806 | printk(", UDMA(16)"); | |
807 | } | |
808 | } | |
809 | } else { | |
810 | printk(", (U)DMA"); /* Can be BIOS-enabled! */ | |
811 | } | |
812 | } else if (id->field_valid & 2) { | |
813 | if ((id->dma_mword >> 8) && (id->dma_1word >> 8)) | |
814 | goto bug_dma_off; | |
815 | printk(", DMA"); | |
816 | } else if (id->field_valid & 1) { | |
0a8348d0 | 817 | goto bug_dma_off; |
1da177e4 LT |
818 | } |
819 | return; | |
820 | bug_dma_off: | |
821 | printk(", BUG DMA OFF"); | |
7469aaf6 | 822 | hwif->dma_off_quietly(drive); |
1da177e4 LT |
823 | return; |
824 | } | |
825 | ||
826 | EXPORT_SYMBOL(ide_dma_verbose); | |
827 | ||
3608b5d7 BZ |
828 | int ide_set_dma(ide_drive_t *drive) |
829 | { | |
830 | ide_hwif_t *hwif = drive->hwif; | |
831 | int rc; | |
832 | ||
833 | rc = hwif->ide_dma_check(drive); | |
834 | ||
835 | switch(rc) { | |
836 | case -1: /* DMA needs to be disabled */ | |
7469aaf6 | 837 | hwif->dma_off_quietly(drive); |
6f5050a9 | 838 | return -1; |
3608b5d7 BZ |
839 | case 0: /* DMA needs to be enabled */ |
840 | return hwif->ide_dma_on(drive); | |
841 | case 1: /* DMA setting cannot be changed */ | |
842 | break; | |
843 | default: | |
844 | BUG(); | |
845 | break; | |
846 | } | |
847 | ||
848 | return rc; | |
849 | } | |
850 | ||
851 | EXPORT_SYMBOL_GPL(ide_set_dma); | |
852 | ||
1da177e4 | 853 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
841d2a9b | 854 | void ide_dma_lost_irq (ide_drive_t *drive) |
1da177e4 LT |
855 | { |
856 | printk("%s: DMA interrupt recovery\n", drive->name); | |
1da177e4 LT |
857 | } |
858 | ||
841d2a9b | 859 | EXPORT_SYMBOL(ide_dma_lost_irq); |
1da177e4 | 860 | |
c283f5db | 861 | void ide_dma_timeout (ide_drive_t *drive) |
1da177e4 | 862 | { |
c283f5db SS |
863 | ide_hwif_t *hwif = HWIF(drive); |
864 | ||
1da177e4 | 865 | printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); |
1da177e4 | 866 | |
c283f5db SS |
867 | if (hwif->ide_dma_test_irq(drive)) |
868 | return; | |
869 | ||
870 | hwif->ide_dma_end(drive); | |
1da177e4 LT |
871 | } |
872 | ||
c283f5db | 873 | EXPORT_SYMBOL(ide_dma_timeout); |
1da177e4 LT |
874 | |
875 | /* | |
876 | * Needed for allowing full modular support of ide-driver | |
877 | */ | |
878 | static int ide_release_dma_engine(ide_hwif_t *hwif) | |
879 | { | |
880 | if (hwif->dmatable_cpu) { | |
881 | pci_free_consistent(hwif->pci_dev, | |
882 | PRD_ENTRIES * PRD_BYTES, | |
883 | hwif->dmatable_cpu, | |
884 | hwif->dmatable_dma); | |
885 | hwif->dmatable_cpu = NULL; | |
886 | } | |
887 | return 1; | |
888 | } | |
889 | ||
890 | static int ide_release_iomio_dma(ide_hwif_t *hwif) | |
891 | { | |
1da177e4 | 892 | release_region(hwif->dma_base, 8); |
020e322d SS |
893 | if (hwif->extra_ports) |
894 | release_region(hwif->extra_base, hwif->extra_ports); | |
1da177e4 LT |
895 | return 1; |
896 | } | |
897 | ||
898 | /* | |
899 | * Needed for allowing full modular support of ide-driver | |
900 | */ | |
dc844e05 | 901 | int ide_release_dma(ide_hwif_t *hwif) |
1da177e4 | 902 | { |
dc844e05 SS |
903 | ide_release_dma_engine(hwif); |
904 | ||
2ad1e558 | 905 | if (hwif->mmio) |
1da177e4 | 906 | return 1; |
dc844e05 SS |
907 | else |
908 | return ide_release_iomio_dma(hwif); | |
1da177e4 LT |
909 | } |
910 | ||
911 | static int ide_allocate_dma_engine(ide_hwif_t *hwif) | |
912 | { | |
913 | hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev, | |
914 | PRD_ENTRIES * PRD_BYTES, | |
915 | &hwif->dmatable_dma); | |
916 | ||
917 | if (hwif->dmatable_cpu) | |
918 | return 0; | |
919 | ||
dc844e05 SS |
920 | printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n", |
921 | hwif->cds->name); | |
1da177e4 | 922 | |
1da177e4 LT |
923 | return 1; |
924 | } | |
925 | ||
926 | static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
927 | { | |
928 | printk(KERN_INFO " %s: MMIO-DMA ", hwif->name); | |
929 | ||
020e322d | 930 | hwif->dma_base = base; |
1da177e4 LT |
931 | |
932 | if(hwif->mate) | |
933 | hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base; | |
934 | else | |
935 | hwif->dma_master = base; | |
936 | return 0; | |
937 | } | |
938 | ||
939 | static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
940 | { | |
941 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx", | |
020e322d SS |
942 | hwif->name, base, base + ports - 1); |
943 | ||
1da177e4 LT |
944 | if (!request_region(base, ports, hwif->name)) { |
945 | printk(" -- Error, ports in use.\n"); | |
946 | return 1; | |
947 | } | |
020e322d | 948 | |
1da177e4 | 949 | hwif->dma_base = base; |
020e322d SS |
950 | |
951 | if (hwif->cds->extra) { | |
952 | hwif->extra_base = base + (hwif->channel ? 8 : 16); | |
953 | ||
954 | if (!hwif->mate || !hwif->mate->extra_ports) { | |
955 | if (!request_region(hwif->extra_base, | |
956 | hwif->cds->extra, hwif->cds->name)) { | |
957 | printk(" -- Error, extra ports in use.\n"); | |
958 | release_region(base, ports); | |
959 | return 1; | |
960 | } | |
961 | hwif->extra_ports = hwif->cds->extra; | |
962 | } | |
1da177e4 | 963 | } |
020e322d | 964 | |
1da177e4 | 965 | if(hwif->mate) |
3f63c5e8 | 966 | hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base:base; |
1da177e4 LT |
967 | else |
968 | hwif->dma_master = base; | |
1da177e4 LT |
969 | return 0; |
970 | } | |
971 | ||
972 | static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
973 | { | |
2ad1e558 | 974 | if (hwif->mmio) |
1da177e4 | 975 | return ide_mapped_mmio_dma(hwif, base,ports); |
2ad1e558 | 976 | |
1da177e4 LT |
977 | return ide_iomio_dma(hwif, base, ports); |
978 | } | |
979 | ||
980 | /* | |
981 | * This can be called for a dynamically installed interface. Don't __init it | |
982 | */ | |
983 | void ide_setup_dma (ide_hwif_t *hwif, unsigned long dma_base, unsigned int num_ports) | |
984 | { | |
985 | if (ide_dma_iobase(hwif, dma_base, num_ports)) | |
986 | return; | |
987 | ||
988 | if (ide_allocate_dma_engine(hwif)) { | |
989 | ide_release_dma(hwif); | |
990 | return; | |
991 | } | |
992 | ||
993 | if (!(hwif->dma_command)) | |
994 | hwif->dma_command = hwif->dma_base; | |
995 | if (!(hwif->dma_vendor1)) | |
996 | hwif->dma_vendor1 = (hwif->dma_base + 1); | |
997 | if (!(hwif->dma_status)) | |
998 | hwif->dma_status = (hwif->dma_base + 2); | |
999 | if (!(hwif->dma_vendor3)) | |
1000 | hwif->dma_vendor3 = (hwif->dma_base + 3); | |
1001 | if (!(hwif->dma_prdtable)) | |
1002 | hwif->dma_prdtable = (hwif->dma_base + 4); | |
1003 | ||
7469aaf6 BZ |
1004 | if (!hwif->dma_off_quietly) |
1005 | hwif->dma_off_quietly = &ide_dma_off_quietly; | |
1006 | if (!hwif->dma_host_off) | |
1007 | hwif->dma_host_off = &ide_dma_host_off; | |
1da177e4 LT |
1008 | if (!hwif->ide_dma_on) |
1009 | hwif->ide_dma_on = &__ide_dma_on; | |
ccf35289 BZ |
1010 | if (!hwif->dma_host_on) |
1011 | hwif->dma_host_on = &ide_dma_host_on; | |
1da177e4 LT |
1012 | if (!hwif->ide_dma_check) |
1013 | hwif->ide_dma_check = &__ide_dma_check; | |
1014 | if (!hwif->dma_setup) | |
1015 | hwif->dma_setup = &ide_dma_setup; | |
1016 | if (!hwif->dma_exec_cmd) | |
1017 | hwif->dma_exec_cmd = &ide_dma_exec_cmd; | |
1018 | if (!hwif->dma_start) | |
1019 | hwif->dma_start = &ide_dma_start; | |
1020 | if (!hwif->ide_dma_end) | |
1021 | hwif->ide_dma_end = &__ide_dma_end; | |
1022 | if (!hwif->ide_dma_test_irq) | |
1023 | hwif->ide_dma_test_irq = &__ide_dma_test_irq; | |
c283f5db SS |
1024 | if (!hwif->dma_timeout) |
1025 | hwif->dma_timeout = &ide_dma_timeout; | |
841d2a9b SS |
1026 | if (!hwif->dma_lost_irq) |
1027 | hwif->dma_lost_irq = &ide_dma_lost_irq; | |
1da177e4 LT |
1028 | |
1029 | if (hwif->chipset != ide_trm290) { | |
1030 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
1031 | printk(", BIOS settings: %s:%s, %s:%s", | |
1032 | hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "pio", | |
1033 | hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "pio"); | |
1034 | } | |
1035 | printk("\n"); | |
1036 | ||
125e1874 | 1037 | BUG_ON(!hwif->dma_master); |
1da177e4 LT |
1038 | } |
1039 | ||
1040 | EXPORT_SYMBOL_GPL(ide_setup_dma); | |
1041 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |