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1da177e4 | 1 | /* |
204f47c5 BZ |
2 | * IDE DMA support (including IDE PCI BM-DMA). |
3 | * | |
59bca8cc BZ |
4 | * Copyright (C) 1995-1998 Mark Lord |
5 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
6 | * Copyright (C) 2004, 2007 Bartlomiej Zolnierkiewicz | |
58f189fc | 7 | * |
1da177e4 | 8 | * May be copied or modified under the terms of the GNU General Public License |
204f47c5 BZ |
9 | * |
10 | * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). | |
1da177e4 LT |
11 | */ |
12 | ||
13 | /* | |
14 | * Special Thanks to Mark for his Six years of work. | |
1da177e4 LT |
15 | */ |
16 | ||
17 | /* | |
1da177e4 LT |
18 | * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for |
19 | * fixing the problem with the BIOS on some Acer motherboards. | |
20 | * | |
21 | * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing | |
22 | * "TX" chipset compatibility and for providing patches for the "TX" chipset. | |
23 | * | |
24 | * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack | |
25 | * at generic DMA -- his patches were referred to when preparing this code. | |
26 | * | |
27 | * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> | |
28 | * for supplying a Promise UDMA board & WD UDMA drive for this work! | |
1da177e4 LT |
29 | */ |
30 | ||
1da177e4 LT |
31 | #include <linux/module.h> |
32 | #include <linux/types.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/timer.h> | |
35 | #include <linux/mm.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/ide.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/scatterlist.h> | |
5c05ff68 | 42 | #include <linux/dma-mapping.h> |
1da177e4 LT |
43 | |
44 | #include <asm/io.h> | |
45 | #include <asm/irq.h> | |
46 | ||
1da177e4 LT |
47 | static const struct drive_list_entry drive_whitelist [] = { |
48 | ||
c2d3ce8c JH |
49 | { "Micropolis 2112A" , NULL }, |
50 | { "CONNER CTMA 4000" , NULL }, | |
51 | { "CONNER CTT8000-A" , NULL }, | |
52 | { "ST34342A" , NULL }, | |
1da177e4 LT |
53 | { NULL , NULL } |
54 | }; | |
55 | ||
56 | static const struct drive_list_entry drive_blacklist [] = { | |
57 | ||
c2d3ce8c JH |
58 | { "WDC AC11000H" , NULL }, |
59 | { "WDC AC22100H" , NULL }, | |
60 | { "WDC AC32500H" , NULL }, | |
61 | { "WDC AC33100H" , NULL }, | |
62 | { "WDC AC31600H" , NULL }, | |
1da177e4 LT |
63 | { "WDC AC32100H" , "24.09P07" }, |
64 | { "WDC AC23200L" , "21.10N21" }, | |
c2d3ce8c JH |
65 | { "Compaq CRD-8241B" , NULL }, |
66 | { "CRD-8400B" , NULL }, | |
67 | { "CRD-8480B", NULL }, | |
68 | { "CRD-8482B", NULL }, | |
69 | { "CRD-84" , NULL }, | |
70 | { "SanDisk SDP3B" , NULL }, | |
71 | { "SanDisk SDP3B-64" , NULL }, | |
72 | { "SANYO CD-ROM CRD" , NULL }, | |
73 | { "HITACHI CDR-8" , NULL }, | |
74 | { "HITACHI CDR-8335" , NULL }, | |
75 | { "HITACHI CDR-8435" , NULL }, | |
76 | { "Toshiba CD-ROM XM-6202B" , NULL }, | |
77 | { "TOSHIBA CD-ROM XM-1702BC", NULL }, | |
78 | { "CD-532E-A" , NULL }, | |
79 | { "E-IDE CD-ROM CR-840", NULL }, | |
80 | { "CD-ROM Drive/F5A", NULL }, | |
81 | { "WPI CDD-820", NULL }, | |
82 | { "SAMSUNG CD-ROM SC-148C", NULL }, | |
83 | { "SAMSUNG CD-ROM SC", NULL }, | |
84 | { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL }, | |
85 | { "_NEC DV5800A", NULL }, | |
5a6248ca | 86 | { "SAMSUNG CD-ROM SN-124", "N001" }, |
c2d3ce8c | 87 | { "Seagate STT20000A", NULL }, |
b0bc65b9 | 88 | { "CD-ROM CDR_U200", "1.09" }, |
1da177e4 LT |
89 | { NULL , NULL } |
90 | ||
91 | }; | |
92 | ||
1da177e4 LT |
93 | /** |
94 | * ide_dma_intr - IDE DMA interrupt handler | |
95 | * @drive: the drive the interrupt is for | |
96 | * | |
97 | * Handle an interrupt completing a read/write DMA transfer on an | |
98 | * IDE device | |
99 | */ | |
100 | ||
101 | ide_startstop_t ide_dma_intr (ide_drive_t *drive) | |
102 | { | |
b73c7ee2 | 103 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 LT |
104 | u8 stat = 0, dma_stat = 0; |
105 | ||
b73c7ee2 | 106 | dma_stat = hwif->dma_ops->dma_end(drive); |
374e042c | 107 | stat = hwif->tp_ops->read_status(hwif); |
c47137a9 | 108 | |
3a7d2484 | 109 | if (OK_STAT(stat, DRIVE_READY, drive->bad_wstat | ATA_DRQ)) { |
1da177e4 LT |
110 | if (!dma_stat) { |
111 | struct request *rq = HWGROUP(drive)->rq; | |
112 | ||
4d7a984b | 113 | task_end_request(drive, rq, stat); |
1da177e4 LT |
114 | return ide_stopped; |
115 | } | |
116 | printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n", | |
117 | drive->name, dma_stat); | |
118 | } | |
119 | return ide_error(drive, "dma_intr", stat); | |
120 | } | |
121 | ||
122 | EXPORT_SYMBOL_GPL(ide_dma_intr); | |
123 | ||
75d7d963 BZ |
124 | static int ide_dma_good_drive(ide_drive_t *drive) |
125 | { | |
126 | return ide_in_drive_list(drive->id, drive_whitelist); | |
127 | } | |
128 | ||
1da177e4 LT |
129 | /** |
130 | * ide_build_sglist - map IDE scatter gather for DMA I/O | |
131 | * @drive: the drive to build the DMA table for | |
132 | * @rq: the request holding the sg list | |
133 | * | |
5c05ff68 BZ |
134 | * Perform the DMA mapping magic necessary to access the source or |
135 | * target buffers of a request via DMA. The lower layers of the | |
1da177e4 | 136 | * kernel provide the necessary cache management so that we can |
5c05ff68 | 137 | * operate in a portable fashion. |
1da177e4 LT |
138 | */ |
139 | ||
140 | int ide_build_sglist(ide_drive_t *drive, struct request *rq) | |
141 | { | |
142 | ide_hwif_t *hwif = HWIF(drive); | |
143 | struct scatterlist *sg = hwif->sg_table; | |
144 | ||
1da177e4 LT |
145 | ide_map_sg(drive, rq); |
146 | ||
147 | if (rq_data_dir(rq) == READ) | |
5c05ff68 | 148 | hwif->sg_dma_direction = DMA_FROM_DEVICE; |
1da177e4 | 149 | else |
5c05ff68 | 150 | hwif->sg_dma_direction = DMA_TO_DEVICE; |
1da177e4 | 151 | |
5c05ff68 BZ |
152 | return dma_map_sg(hwif->dev, sg, hwif->sg_nents, |
153 | hwif->sg_dma_direction); | |
1da177e4 LT |
154 | } |
155 | ||
156 | EXPORT_SYMBOL_GPL(ide_build_sglist); | |
157 | ||
8e882ba1 | 158 | #ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
1da177e4 LT |
159 | /** |
160 | * ide_build_dmatable - build IDE DMA table | |
161 | * | |
162 | * ide_build_dmatable() prepares a dma request. We map the command | |
163 | * to get the pci bus addresses of the buffers and then build up | |
164 | * the PRD table that the IDE layer wants to be fed. The code | |
165 | * knows about the 64K wrap bug in the CS5530. | |
166 | * | |
167 | * Returns the number of built PRD entries if all went okay, | |
168 | * returns 0 otherwise. | |
169 | * | |
170 | * May also be invoked from trm290.c | |
171 | */ | |
172 | ||
173 | int ide_build_dmatable (ide_drive_t *drive, struct request *rq) | |
174 | { | |
175 | ide_hwif_t *hwif = HWIF(drive); | |
7fa897b9 | 176 | __le32 *table = (__le32 *)hwif->dmatable_cpu; |
1da177e4 LT |
177 | unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0; |
178 | unsigned int count = 0; | |
179 | int i; | |
180 | struct scatterlist *sg; | |
181 | ||
182 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
183 | ||
184 | if (!i) | |
185 | return 0; | |
186 | ||
187 | sg = hwif->sg_table; | |
188 | while (i) { | |
189 | u32 cur_addr; | |
190 | u32 cur_len; | |
191 | ||
192 | cur_addr = sg_dma_address(sg); | |
193 | cur_len = sg_dma_len(sg); | |
194 | ||
195 | /* | |
196 | * Fill in the dma table, without crossing any 64kB boundaries. | |
197 | * Most hardware requires 16-bit alignment of all blocks, | |
198 | * but the trm290 requires 32-bit alignment. | |
199 | */ | |
200 | ||
201 | while (cur_len) { | |
202 | if (count++ >= PRD_ENTRIES) { | |
203 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
204 | goto use_pio_instead; | |
205 | } else { | |
206 | u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff); | |
207 | ||
208 | if (bcount > cur_len) | |
209 | bcount = cur_len; | |
210 | *table++ = cpu_to_le32(cur_addr); | |
211 | xcount = bcount & 0xffff; | |
212 | if (is_trm290) | |
213 | xcount = ((xcount >> 2) - 1) << 16; | |
22e05b45 | 214 | else if (xcount == 0x0000) { |
1da177e4 LT |
215 | /* |
216 | * Most chipsets correctly interpret a length of 0x0000 as 64KB, | |
217 | * but at least one (e.g. CS5530) misinterprets it as zero (!). | |
218 | * So here we break the 64KB entry into two 32KB entries instead. | |
219 | */ | |
220 | if (count++ >= PRD_ENTRIES) { | |
221 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
222 | goto use_pio_instead; | |
223 | } | |
224 | *table++ = cpu_to_le32(0x8000); | |
225 | *table++ = cpu_to_le32(cur_addr + 0x8000); | |
226 | xcount = 0x8000; | |
227 | } | |
228 | *table++ = cpu_to_le32(xcount); | |
229 | cur_addr += bcount; | |
230 | cur_len -= bcount; | |
231 | } | |
232 | } | |
233 | ||
55c16a70 | 234 | sg = sg_next(sg); |
1da177e4 LT |
235 | i--; |
236 | } | |
237 | ||
238 | if (count) { | |
239 | if (!is_trm290) | |
240 | *--table |= cpu_to_le32(0x80000000); | |
241 | return count; | |
242 | } | |
f6fb786d | 243 | |
1da177e4 | 244 | printk(KERN_ERR "%s: empty DMA table?\n", drive->name); |
f6fb786d | 245 | |
1da177e4 | 246 | use_pio_instead: |
f6fb786d BZ |
247 | ide_destroy_dmatable(drive); |
248 | ||
1da177e4 LT |
249 | return 0; /* revert to PIO for this request */ |
250 | } | |
251 | ||
252 | EXPORT_SYMBOL_GPL(ide_build_dmatable); | |
062f9f02 | 253 | #endif |
1da177e4 LT |
254 | |
255 | /** | |
256 | * ide_destroy_dmatable - clean up DMA mapping | |
257 | * @drive: The drive to unmap | |
258 | * | |
259 | * Teardown mappings after DMA has completed. This must be called | |
260 | * after the completion of each use of ide_build_dmatable and before | |
261 | * the next use of ide_build_dmatable. Failure to do so will cause | |
262 | * an oops as only one mapping can be live for each target at a given | |
263 | * time. | |
264 | */ | |
265 | ||
266 | void ide_destroy_dmatable (ide_drive_t *drive) | |
267 | { | |
36501650 | 268 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 | 269 | |
5c05ff68 | 270 | dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->sg_nents, |
36501650 | 271 | hwif->sg_dma_direction); |
1da177e4 LT |
272 | } |
273 | ||
274 | EXPORT_SYMBOL_GPL(ide_destroy_dmatable); | |
275 | ||
8e882ba1 | 276 | #ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
1da177e4 LT |
277 | /** |
278 | * config_drive_for_dma - attempt to activate IDE DMA | |
279 | * @drive: the drive to place in DMA mode | |
280 | * | |
281 | * If the drive supports at least mode 2 DMA or UDMA of any kind | |
282 | * then attempt to place it into DMA mode. Drives that are known to | |
283 | * support DMA but predate the DMA properties or that are known | |
284 | * to have DMA handling bugs are also set up appropriately based | |
285 | * on the good/bad drive lists. | |
286 | */ | |
287 | ||
288 | static int config_drive_for_dma (ide_drive_t *drive) | |
289 | { | |
1116fae5 | 290 | ide_hwif_t *hwif = drive->hwif; |
4dde4492 | 291 | u16 *id = drive->id; |
1da177e4 | 292 | |
33c1002e BZ |
293 | if (drive->media != ide_disk) { |
294 | if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) | |
bcbf6ee3 | 295 | return 0; |
33c1002e | 296 | } |
1116fae5 | 297 | |
0ae2e178 BZ |
298 | /* |
299 | * Enable DMA on any drive that has | |
300 | * UltraDMA (mode 0/1/2/3/4/5/6) enabled | |
301 | */ | |
4dde4492 BZ |
302 | if ((id[ATA_ID_FIELD_VALID] & 4) && |
303 | ((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f)) | |
0ae2e178 BZ |
304 | return 1; |
305 | ||
306 | /* | |
307 | * Enable DMA on any drive that has mode2 DMA | |
308 | * (multi or single) enabled | |
309 | */ | |
4dde4492 BZ |
310 | if (id[ATA_ID_FIELD_VALID] & 2) /* regular DMA */ |
311 | if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 || | |
312 | (id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404) | |
0ae2e178 | 313 | return 1; |
3608b5d7 | 314 | |
0ae2e178 BZ |
315 | /* Consult the list of known "good" drives */ |
316 | if (ide_dma_good_drive(drive)) | |
317 | return 1; | |
318 | ||
319 | return 0; | |
1da177e4 LT |
320 | } |
321 | ||
322 | /** | |
323 | * dma_timer_expiry - handle a DMA timeout | |
324 | * @drive: Drive that timed out | |
325 | * | |
326 | * An IDE DMA transfer timed out. In the event of an error we ask | |
327 | * the driver to resolve the problem, if a DMA transfer is still | |
328 | * in progress we continue to wait (arguably we need to add a | |
329 | * secondary 'I don't care what the drive thinks' timeout here) | |
330 | * Finally if we have an interrupt we let it complete the I/O. | |
331 | * But only one time - we clear expiry and if it's still not | |
332 | * completed after WAIT_CMD, we error and retry in PIO. | |
333 | * This can occur if an interrupt is lost or due to hang or bugs. | |
334 | */ | |
335 | ||
336 | static int dma_timer_expiry (ide_drive_t *drive) | |
337 | { | |
338 | ide_hwif_t *hwif = HWIF(drive); | |
374e042c | 339 | u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); |
1da177e4 LT |
340 | |
341 | printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n", | |
342 | drive->name, dma_stat); | |
343 | ||
344 | if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ | |
345 | return WAIT_CMD; | |
346 | ||
347 | HWGROUP(drive)->expiry = NULL; /* one free ride for now */ | |
348 | ||
349 | /* 1 dmaing, 2 error, 4 intr */ | |
350 | if (dma_stat & 2) /* ERROR */ | |
351 | return -1; | |
352 | ||
353 | if (dma_stat & 1) /* DMAing */ | |
354 | return WAIT_CMD; | |
355 | ||
356 | if (dma_stat & 4) /* Got an Interrupt */ | |
357 | return WAIT_CMD; | |
358 | ||
359 | return 0; /* Status is unknown -- reset the bus */ | |
360 | } | |
361 | ||
362 | /** | |
15ce926a | 363 | * ide_dma_host_set - Enable/disable DMA on a host |
1da177e4 LT |
364 | * @drive: drive to control |
365 | * | |
15ce926a BZ |
366 | * Enable/disable DMA on an IDE controller following generic |
367 | * bus-mastering IDE controller behaviour. | |
1da177e4 LT |
368 | */ |
369 | ||
15ce926a | 370 | void ide_dma_host_set(ide_drive_t *drive, int on) |
1da177e4 LT |
371 | { |
372 | ide_hwif_t *hwif = HWIF(drive); | |
123995b9 | 373 | u8 unit = drive->dn & 1; |
374e042c | 374 | u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); |
1da177e4 | 375 | |
15ce926a BZ |
376 | if (on) |
377 | dma_stat |= (1 << (5 + unit)); | |
378 | else | |
379 | dma_stat &= ~(1 << (5 + unit)); | |
380 | ||
ab86f91e | 381 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
cab7f8ed BZ |
382 | writeb(dma_stat, |
383 | (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); | |
ab86f91e | 384 | else |
cab7f8ed | 385 | outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS); |
1da177e4 LT |
386 | } |
387 | ||
15ce926a | 388 | EXPORT_SYMBOL_GPL(ide_dma_host_set); |
8e882ba1 | 389 | #endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ |
1da177e4 LT |
390 | |
391 | /** | |
7469aaf6 | 392 | * ide_dma_off_quietly - Generic DMA kill |
1da177e4 LT |
393 | * @drive: drive to control |
394 | * | |
395 | * Turn off the current DMA on this IDE controller. | |
396 | */ | |
397 | ||
7469aaf6 | 398 | void ide_dma_off_quietly(ide_drive_t *drive) |
1da177e4 | 399 | { |
97100fc8 | 400 | drive->dev_flags &= ~IDE_DFLAG_USING_DMA; |
1da177e4 LT |
401 | ide_toggle_bounce(drive, 0); |
402 | ||
5e37bdc0 | 403 | drive->hwif->dma_ops->dma_host_set(drive, 0); |
1da177e4 LT |
404 | } |
405 | ||
7469aaf6 | 406 | EXPORT_SYMBOL(ide_dma_off_quietly); |
1da177e4 LT |
407 | |
408 | /** | |
7469aaf6 | 409 | * ide_dma_off - disable DMA on a device |
1da177e4 LT |
410 | * @drive: drive to disable DMA on |
411 | * | |
412 | * Disable IDE DMA for a device on this IDE controller. | |
413 | * Inform the user that DMA has been disabled. | |
414 | */ | |
415 | ||
7469aaf6 | 416 | void ide_dma_off(ide_drive_t *drive) |
1da177e4 LT |
417 | { |
418 | printk(KERN_INFO "%s: DMA disabled\n", drive->name); | |
4a546e04 | 419 | ide_dma_off_quietly(drive); |
1da177e4 LT |
420 | } |
421 | ||
7469aaf6 | 422 | EXPORT_SYMBOL(ide_dma_off); |
1da177e4 | 423 | |
1da177e4 | 424 | /** |
4a546e04 | 425 | * ide_dma_on - Enable DMA on a device |
1da177e4 LT |
426 | * @drive: drive to enable DMA on |
427 | * | |
428 | * Enable IDE DMA for a device on this IDE controller. | |
429 | */ | |
4a546e04 BZ |
430 | |
431 | void ide_dma_on(ide_drive_t *drive) | |
1da177e4 | 432 | { |
97100fc8 | 433 | drive->dev_flags |= IDE_DFLAG_USING_DMA; |
1da177e4 LT |
434 | ide_toggle_bounce(drive, 1); |
435 | ||
5e37bdc0 | 436 | drive->hwif->dma_ops->dma_host_set(drive, 1); |
1da177e4 LT |
437 | } |
438 | ||
8e882ba1 | 439 | #ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
1da177e4 LT |
440 | /** |
441 | * ide_dma_setup - begin a DMA phase | |
442 | * @drive: target device | |
443 | * | |
444 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
445 | * and then set up the DMA transfer registers for a device | |
446 | * that follows generic IDE PCI DMA behaviour. Controllers can | |
447 | * override this function if they need to | |
448 | * | |
449 | * Returns 0 on success. If a PIO fallback is required then 1 | |
450 | * is returned. | |
451 | */ | |
452 | ||
453 | int ide_dma_setup(ide_drive_t *drive) | |
454 | { | |
455 | ide_hwif_t *hwif = drive->hwif; | |
456 | struct request *rq = HWGROUP(drive)->rq; | |
457 | unsigned int reading; | |
ab86f91e | 458 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
1da177e4 LT |
459 | u8 dma_stat; |
460 | ||
461 | if (rq_data_dir(rq)) | |
462 | reading = 0; | |
463 | else | |
464 | reading = 1 << 3; | |
465 | ||
466 | /* fall back to pio! */ | |
467 | if (!ide_build_dmatable(drive, rq)) { | |
468 | ide_map_sg(drive, rq); | |
469 | return 1; | |
470 | } | |
471 | ||
472 | /* PRD table */ | |
13572144 | 473 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
55224bc8 BZ |
474 | writel(hwif->dmatable_dma, |
475 | (void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS)); | |
0ecdca26 | 476 | else |
55224bc8 | 477 | outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS); |
1da177e4 LT |
478 | |
479 | /* specify r/w */ | |
ab86f91e | 480 | if (mmio) |
cab7f8ed | 481 | writeb(reading, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); |
ab86f91e | 482 | else |
cab7f8ed | 483 | outb(reading, hwif->dma_base + ATA_DMA_CMD); |
1da177e4 | 484 | |
b2f951aa | 485 | /* read DMA status for INTR & ERROR flags */ |
374e042c | 486 | dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); |
1da177e4 LT |
487 | |
488 | /* clear INTR & ERROR flags */ | |
ab86f91e | 489 | if (mmio) |
cab7f8ed BZ |
490 | writeb(dma_stat | 6, |
491 | (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); | |
ab86f91e | 492 | else |
cab7f8ed | 493 | outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS); |
ab86f91e | 494 | |
1da177e4 LT |
495 | drive->waiting_for_dma = 1; |
496 | return 0; | |
497 | } | |
498 | ||
499 | EXPORT_SYMBOL_GPL(ide_dma_setup); | |
500 | ||
f37afdac | 501 | void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) |
1da177e4 LT |
502 | { |
503 | /* issue cmd to drive */ | |
504 | ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry); | |
505 | } | |
f37afdac | 506 | EXPORT_SYMBOL_GPL(ide_dma_exec_cmd); |
1da177e4 LT |
507 | |
508 | void ide_dma_start(ide_drive_t *drive) | |
509 | { | |
ab86f91e BZ |
510 | ide_hwif_t *hwif = drive->hwif; |
511 | u8 dma_cmd; | |
1da177e4 LT |
512 | |
513 | /* Note that this is done *after* the cmd has | |
514 | * been issued to the drive, as per the BM-IDE spec. | |
515 | * The Promise Ultra33 doesn't work correctly when | |
516 | * we do this part before issuing the drive cmd. | |
517 | */ | |
ab86f91e | 518 | if (hwif->host_flags & IDE_HFLAG_MMIO) { |
cab7f8ed | 519 | dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); |
ab86f91e | 520 | /* start DMA */ |
cab7f8ed BZ |
521 | writeb(dma_cmd | 1, |
522 | (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); | |
ab86f91e | 523 | } else { |
cab7f8ed BZ |
524 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
525 | outb(dma_cmd | 1, hwif->dma_base + ATA_DMA_CMD); | |
ab86f91e BZ |
526 | } |
527 | ||
1da177e4 LT |
528 | wmb(); |
529 | } | |
530 | ||
531 | EXPORT_SYMBOL_GPL(ide_dma_start); | |
532 | ||
533 | /* returns 1 on error, 0 otherwise */ | |
653bcf52 | 534 | int ide_dma_end(ide_drive_t *drive) |
1da177e4 | 535 | { |
ab86f91e BZ |
536 | ide_hwif_t *hwif = drive->hwif; |
537 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; | |
1da177e4 LT |
538 | u8 dma_stat = 0, dma_cmd = 0; |
539 | ||
540 | drive->waiting_for_dma = 0; | |
ab86f91e BZ |
541 | |
542 | if (mmio) { | |
543 | /* get DMA command mode */ | |
cab7f8ed | 544 | dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); |
ab86f91e | 545 | /* stop DMA */ |
cab7f8ed BZ |
546 | writeb(dma_cmd & ~1, |
547 | (void __iomem *)(hwif->dma_base + ATA_DMA_CMD)); | |
ab86f91e | 548 | } else { |
cab7f8ed BZ |
549 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
550 | outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); | |
ab86f91e BZ |
551 | } |
552 | ||
1da177e4 | 553 | /* get DMA status */ |
374e042c | 554 | dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); |
ab86f91e BZ |
555 | |
556 | if (mmio) | |
557 | /* clear the INTR & ERROR bits */ | |
cab7f8ed BZ |
558 | writeb(dma_stat | 6, |
559 | (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)); | |
ab86f91e | 560 | else |
cab7f8ed | 561 | outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS); |
ab86f91e | 562 | |
1da177e4 LT |
563 | /* purge DMA mappings */ |
564 | ide_destroy_dmatable(drive); | |
565 | /* verify good DMA status */ | |
1da177e4 LT |
566 | wmb(); |
567 | return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; | |
568 | } | |
653bcf52 | 569 | EXPORT_SYMBOL_GPL(ide_dma_end); |
1da177e4 LT |
570 | |
571 | /* returns 1 if dma irq issued, 0 otherwise */ | |
f37afdac | 572 | int ide_dma_test_irq(ide_drive_t *drive) |
1da177e4 LT |
573 | { |
574 | ide_hwif_t *hwif = HWIF(drive); | |
374e042c | 575 | u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); |
1da177e4 | 576 | |
1da177e4 LT |
577 | /* return 1 if INTR asserted */ |
578 | if ((dma_stat & 4) == 4) | |
579 | return 1; | |
c67c216d | 580 | |
1da177e4 LT |
581 | return 0; |
582 | } | |
f37afdac | 583 | EXPORT_SYMBOL_GPL(ide_dma_test_irq); |
0ae2e178 BZ |
584 | #else |
585 | static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; } | |
8e882ba1 | 586 | #endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ |
1da177e4 LT |
587 | |
588 | int __ide_dma_bad_drive (ide_drive_t *drive) | |
589 | { | |
4dde4492 | 590 | u16 *id = drive->id; |
1da177e4 | 591 | |
65e5f2e3 | 592 | int blacklist = ide_in_drive_list(id, drive_blacklist); |
1da177e4 LT |
593 | if (blacklist) { |
594 | printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", | |
4dde4492 | 595 | drive->name, (char *)&id[ATA_ID_PROD]); |
1da177e4 LT |
596 | return blacklist; |
597 | } | |
598 | return 0; | |
599 | } | |
600 | ||
601 | EXPORT_SYMBOL(__ide_dma_bad_drive); | |
602 | ||
2d5eaa6d BZ |
603 | static const u8 xfer_mode_bases[] = { |
604 | XFER_UDMA_0, | |
605 | XFER_MW_DMA_0, | |
606 | XFER_SW_DMA_0, | |
607 | }; | |
608 | ||
7670df73 | 609 | static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode) |
2d5eaa6d | 610 | { |
4dde4492 | 611 | u16 *id = drive->id; |
2d5eaa6d | 612 | ide_hwif_t *hwif = drive->hwif; |
ac95beed | 613 | const struct ide_port_ops *port_ops = hwif->port_ops; |
2d5eaa6d BZ |
614 | unsigned int mask = 0; |
615 | ||
616 | switch(base) { | |
617 | case XFER_UDMA_0: | |
4dde4492 | 618 | if ((id[ATA_ID_FIELD_VALID] & 4) == 0) |
2d5eaa6d BZ |
619 | break; |
620 | ||
ac95beed BZ |
621 | if (port_ops && port_ops->udma_filter) |
622 | mask = port_ops->udma_filter(drive); | |
851dd33b SS |
623 | else |
624 | mask = hwif->ultra_mask; | |
4dde4492 | 625 | mask &= id[ATA_ID_UDMA_MODES]; |
2d5eaa6d | 626 | |
7670df73 BZ |
627 | /* |
628 | * avoid false cable warning from eighty_ninty_three() | |
629 | */ | |
630 | if (req_mode > XFER_UDMA_2) { | |
631 | if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) | |
632 | mask &= 0x07; | |
633 | } | |
2d5eaa6d BZ |
634 | break; |
635 | case XFER_MW_DMA_0: | |
4dde4492 | 636 | if ((id[ATA_ID_FIELD_VALID] & 2) == 0) |
b4e44369 | 637 | break; |
ac95beed BZ |
638 | if (port_ops && port_ops->mdma_filter) |
639 | mask = port_ops->mdma_filter(drive); | |
b4e44369 SS |
640 | else |
641 | mask = hwif->mwdma_mask; | |
4dde4492 | 642 | mask &= id[ATA_ID_MWDMA_MODES]; |
2d5eaa6d BZ |
643 | break; |
644 | case XFER_SW_DMA_0: | |
4dde4492 BZ |
645 | if (id[ATA_ID_FIELD_VALID] & 2) { |
646 | mask = id[ATA_ID_SWDMA_MODES] & hwif->swdma_mask; | |
48fb2688 BZ |
647 | } else if (id[ATA_ID_OLD_DMA_MODES] >> 8) { |
648 | u8 mode = id[ATA_ID_OLD_DMA_MODES] >> 8; | |
15a4f943 BZ |
649 | |
650 | /* | |
651 | * if the mode is valid convert it to the mask | |
652 | * (the maximum allowed mode is XFER_SW_DMA_2) | |
653 | */ | |
654 | if (mode <= 2) | |
655 | mask = ((2 << mode) - 1) & hwif->swdma_mask; | |
656 | } | |
2d5eaa6d BZ |
657 | break; |
658 | default: | |
659 | BUG(); | |
660 | break; | |
661 | } | |
662 | ||
663 | return mask; | |
664 | } | |
665 | ||
666 | /** | |
7670df73 | 667 | * ide_find_dma_mode - compute DMA speed |
2d5eaa6d | 668 | * @drive: IDE device |
7670df73 BZ |
669 | * @req_mode: requested mode |
670 | * | |
671 | * Checks the drive/host capabilities and finds the speed to use for | |
672 | * the DMA transfer. The speed is then limited by the requested mode. | |
2d5eaa6d | 673 | * |
7670df73 BZ |
674 | * Returns 0 if the drive/host combination is incapable of DMA transfers |
675 | * or if the requested mode is not a DMA mode. | |
2d5eaa6d BZ |
676 | */ |
677 | ||
7670df73 | 678 | u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode) |
2d5eaa6d BZ |
679 | { |
680 | ide_hwif_t *hwif = drive->hwif; | |
681 | unsigned int mask; | |
682 | int x, i; | |
683 | u8 mode = 0; | |
684 | ||
33c1002e BZ |
685 | if (drive->media != ide_disk) { |
686 | if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) | |
687 | return 0; | |
688 | } | |
2d5eaa6d BZ |
689 | |
690 | for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) { | |
7670df73 BZ |
691 | if (req_mode < xfer_mode_bases[i]) |
692 | continue; | |
693 | mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode); | |
2d5eaa6d BZ |
694 | x = fls(mask) - 1; |
695 | if (x >= 0) { | |
696 | mode = xfer_mode_bases[i] + x; | |
697 | break; | |
698 | } | |
699 | } | |
700 | ||
75d7d963 BZ |
701 | if (hwif->chipset == ide_acorn && mode == 0) { |
702 | /* | |
703 | * is this correct? | |
704 | */ | |
4dde4492 BZ |
705 | if (ide_dma_good_drive(drive) && |
706 | drive->id[ATA_ID_EIDE_DMA_TIME] < 150) | |
75d7d963 BZ |
707 | mode = XFER_MW_DMA_1; |
708 | } | |
709 | ||
3ab7efe8 BZ |
710 | mode = min(mode, req_mode); |
711 | ||
712 | printk(KERN_INFO "%s: %s mode selected\n", drive->name, | |
d34887da | 713 | mode ? ide_xfer_verbose(mode) : "no DMA"); |
2d5eaa6d | 714 | |
3ab7efe8 | 715 | return mode; |
2d5eaa6d BZ |
716 | } |
717 | ||
7670df73 | 718 | EXPORT_SYMBOL_GPL(ide_find_dma_mode); |
2d5eaa6d | 719 | |
0ae2e178 | 720 | static int ide_tune_dma(ide_drive_t *drive) |
29e744d0 | 721 | { |
8704de8f | 722 | ide_hwif_t *hwif = drive->hwif; |
29e744d0 BZ |
723 | u8 speed; |
724 | ||
97100fc8 BZ |
725 | if (ata_id_has_dma(drive->id) == 0 || |
726 | (drive->dev_flags & IDE_DFLAG_NODMA)) | |
122ab088 BZ |
727 | return 0; |
728 | ||
729 | /* consult the list of known "bad" drives */ | |
730 | if (__ide_dma_bad_drive(drive)) | |
29e744d0 BZ |
731 | return 0; |
732 | ||
3ab7efe8 BZ |
733 | if (ide_id_dma_bug(drive)) |
734 | return 0; | |
735 | ||
8704de8f | 736 | if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) |
0ae2e178 BZ |
737 | return config_drive_for_dma(drive); |
738 | ||
29e744d0 BZ |
739 | speed = ide_max_dma_mode(drive); |
740 | ||
951784b6 BZ |
741 | if (!speed) |
742 | return 0; | |
29e744d0 | 743 | |
88b2b32b | 744 | if (ide_set_dma_mode(drive, speed)) |
4728d546 | 745 | return 0; |
29e744d0 | 746 | |
4728d546 | 747 | return 1; |
29e744d0 BZ |
748 | } |
749 | ||
0ae2e178 BZ |
750 | static int ide_dma_check(ide_drive_t *drive) |
751 | { | |
752 | ide_hwif_t *hwif = drive->hwif; | |
0ae2e178 | 753 | |
ba4b2e60 | 754 | if (ide_tune_dma(drive)) |
0ae2e178 BZ |
755 | return 0; |
756 | ||
757 | /* TODO: always do PIO fallback */ | |
758 | if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) | |
759 | return -1; | |
760 | ||
761 | ide_set_max_pio(drive); | |
762 | ||
ba4b2e60 | 763 | return -1; |
0ae2e178 BZ |
764 | } |
765 | ||
3ab7efe8 | 766 | int ide_id_dma_bug(ide_drive_t *drive) |
1da177e4 | 767 | { |
4dde4492 | 768 | u16 *id = drive->id; |
1da177e4 | 769 | |
4dde4492 BZ |
770 | if (id[ATA_ID_FIELD_VALID] & 4) { |
771 | if ((id[ATA_ID_UDMA_MODES] >> 8) && | |
772 | (id[ATA_ID_MWDMA_MODES] >> 8)) | |
3ab7efe8 | 773 | goto err_out; |
4dde4492 BZ |
774 | } else if (id[ATA_ID_FIELD_VALID] & 2) { |
775 | if ((id[ATA_ID_MWDMA_MODES] >> 8) && | |
776 | (id[ATA_ID_SWDMA_MODES] >> 8)) | |
3ab7efe8 | 777 | goto err_out; |
1da177e4 | 778 | } |
3ab7efe8 BZ |
779 | return 0; |
780 | err_out: | |
781 | printk(KERN_ERR "%s: bad DMA info in identify block\n", drive->name); | |
782 | return 1; | |
1da177e4 LT |
783 | } |
784 | ||
3608b5d7 BZ |
785 | int ide_set_dma(ide_drive_t *drive) |
786 | { | |
3608b5d7 BZ |
787 | int rc; |
788 | ||
7b905994 BZ |
789 | /* |
790 | * Force DMAing for the beginning of the check. | |
791 | * Some chipsets appear to do interesting | |
792 | * things, if not checked and cleared. | |
793 | * PARANOIA!!! | |
794 | */ | |
4a546e04 | 795 | ide_dma_off_quietly(drive); |
3608b5d7 | 796 | |
7b905994 BZ |
797 | rc = ide_dma_check(drive); |
798 | if (rc) | |
799 | return rc; | |
3608b5d7 | 800 | |
4a546e04 BZ |
801 | ide_dma_on(drive); |
802 | ||
803 | return 0; | |
3608b5d7 BZ |
804 | } |
805 | ||
578cfa0d BZ |
806 | void ide_check_dma_crc(ide_drive_t *drive) |
807 | { | |
808 | u8 mode; | |
809 | ||
810 | ide_dma_off_quietly(drive); | |
811 | drive->crc_count = 0; | |
812 | mode = drive->current_speed; | |
813 | /* | |
814 | * Don't try non Ultra-DMA modes without iCRC's. Force the | |
815 | * device to PIO and make the user enable SWDMA/MWDMA modes. | |
816 | */ | |
817 | if (mode > XFER_UDMA_0 && mode <= XFER_UDMA_7) | |
818 | mode--; | |
819 | else | |
820 | mode = XFER_PIO_4; | |
821 | ide_set_xfer_rate(drive, mode); | |
822 | if (drive->current_speed >= XFER_SW_DMA_0) | |
823 | ide_dma_on(drive); | |
824 | } | |
825 | ||
de23ec9c | 826 | void ide_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 827 | { |
de23ec9c | 828 | printk(KERN_ERR "%s: DMA interrupt recovery\n", drive->name); |
1da177e4 | 829 | } |
de23ec9c | 830 | EXPORT_SYMBOL_GPL(ide_dma_lost_irq); |
1da177e4 | 831 | |
ffa15a69 | 832 | void ide_dma_timeout(ide_drive_t *drive) |
1da177e4 | 833 | { |
c283f5db SS |
834 | ide_hwif_t *hwif = HWIF(drive); |
835 | ||
1da177e4 | 836 | printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); |
1da177e4 | 837 | |
5e37bdc0 | 838 | if (hwif->dma_ops->dma_test_irq(drive)) |
c283f5db SS |
839 | return; |
840 | ||
ffa15a69 BZ |
841 | ide_dump_status(drive, "DMA timeout", hwif->tp_ops->read_status(hwif)); |
842 | ||
5e37bdc0 | 843 | hwif->dma_ops->dma_end(drive); |
1da177e4 | 844 | } |
ffa15a69 | 845 | EXPORT_SYMBOL_GPL(ide_dma_timeout); |
1da177e4 | 846 | |
ffa15a69 | 847 | #ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
0d1bad21 | 848 | void ide_release_dma_engine(ide_hwif_t *hwif) |
1da177e4 LT |
849 | { |
850 | if (hwif->dmatable_cpu) { | |
36501650 BZ |
851 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
852 | ||
853 | pci_free_consistent(pdev, PRD_ENTRIES * PRD_BYTES, | |
854 | hwif->dmatable_cpu, hwif->dmatable_dma); | |
1da177e4 LT |
855 | hwif->dmatable_cpu = NULL; |
856 | } | |
1da177e4 LT |
857 | } |
858 | ||
b8e73fba | 859 | int ide_allocate_dma_engine(ide_hwif_t *hwif) |
1da177e4 | 860 | { |
36501650 BZ |
861 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
862 | ||
863 | hwif->dmatable_cpu = pci_alloc_consistent(pdev, | |
1da177e4 LT |
864 | PRD_ENTRIES * PRD_BYTES, |
865 | &hwif->dmatable_dma); | |
866 | ||
867 | if (hwif->dmatable_cpu) | |
868 | return 0; | |
869 | ||
dc844e05 | 870 | printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n", |
5e59c236 | 871 | hwif->name); |
1da177e4 | 872 | |
1da177e4 LT |
873 | return 1; |
874 | } | |
b8e73fba | 875 | EXPORT_SYMBOL_GPL(ide_allocate_dma_engine); |
1da177e4 | 876 | |
81e8d5a3 | 877 | const struct ide_dma_ops sff_dma_ops = { |
5e37bdc0 BZ |
878 | .dma_host_set = ide_dma_host_set, |
879 | .dma_setup = ide_dma_setup, | |
880 | .dma_exec_cmd = ide_dma_exec_cmd, | |
881 | .dma_start = ide_dma_start, | |
653bcf52 | 882 | .dma_end = ide_dma_end, |
f37afdac | 883 | .dma_test_irq = ide_dma_test_irq, |
5e37bdc0 BZ |
884 | .dma_timeout = ide_dma_timeout, |
885 | .dma_lost_irq = ide_dma_lost_irq, | |
886 | }; | |
81e8d5a3 | 887 | EXPORT_SYMBOL_GPL(sff_dma_ops); |
8e882ba1 | 888 | #endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ |