[mirror_ubuntu-artful-kernel.git] / drivers / ide / ide-timing.h

#ifndef _IDE_TIMING_H
#define _IDE_TIMING_H

/*
 *  Copyright (c) 1999-2001 Vojtech Pavlik
 */

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 * Should you need to contact me, the author, you can do so either by
 * e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail:
 * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
 */

#include <linux/kernel.h>
#include <linux/hdreg.h>

struct ide_timing {
	short mode;
	short setup;	/* t1 */
	short act8b;	/* t2 for 8-bit io */
	short rec8b;	/* t2i for 8-bit io */
	short cyc8b;	/* t0 for 8-bit io */
	short active;	/* t2 or tD */
	short recover;	/* t2i or tK */
	short cycle;	/* t0 */
	short udma;	/* t2CYCTYP/2 */
};

/*
 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
 * for PIO 5, which is a nonstandard extension and UDMA6, which
 * is currently supported only by Maxtor drives. 
 */

static struct ide_timing ide_timing[] = {

	{ XFER_UDMA_6,     0,   0,   0,   0,   0,   0,   0,  15 },
	{ XFER_UDMA_5,     0,   0,   0,   0,   0,   0,   0,  20 },
	{ XFER_UDMA_4,     0,   0,   0,   0,   0,   0,   0,  30 },
	{ XFER_UDMA_3,     0,   0,   0,   0,   0,   0,   0,  45 },

	{ XFER_UDMA_2,     0,   0,   0,   0,   0,   0,   0,  60 },
	{ XFER_UDMA_1,     0,   0,   0,   0,   0,   0,   0,  80 },
	{ XFER_UDMA_0,     0,   0,   0,   0,   0,   0,   0, 120 },

	{ XFER_MW_DMA_2,  25,   0,   0,   0,  70,  25, 120,   0 },
	{ XFER_MW_DMA_1,  45,   0,   0,   0,  80,  50, 150,   0 },
	{ XFER_MW_DMA_0,  60,   0,   0,   0, 215, 215, 480,   0 },

	{ XFER_SW_DMA_2,  60,   0,   0,   0, 120, 120, 240,   0 },
	{ XFER_SW_DMA_1,  90,   0,   0,   0, 240, 240, 480,   0 },
	{ XFER_SW_DMA_0, 120,   0,   0,   0, 480, 480, 960,   0 },

	{ XFER_PIO_5,     20,  50,  30, 100,  50,  30, 100,   0 },
	{ XFER_PIO_4,     25,  70,  25, 120,  70,  25, 120,   0 },
	{ XFER_PIO_3,     30,  80,  70, 180,  80,  70, 180,   0 },

	{ XFER_PIO_2,     30, 290,  40, 330, 100,  90, 240,   0 },
	{ XFER_PIO_1,     50, 290,  93, 383, 125, 100, 383,   0 },
	{ XFER_PIO_0,     70, 290, 240, 600, 165, 150, 600,   0 },

	{ XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960,   0 },

	{ -1 }
};

#define IDE_TIMING_SETUP	0x01
#define IDE_TIMING_ACT8B	0x02
#define IDE_TIMING_REC8B	0x04
#define IDE_TIMING_CYC8B	0x08
#define IDE_TIMING_8BIT		0x0e
#define IDE_TIMING_ACTIVE	0x10
#define IDE_TIMING_RECOVER	0x20
#define IDE_TIMING_CYCLE	0x40
#define IDE_TIMING_UDMA		0x80
#define IDE_TIMING_ALL		0xff

#define ENOUGH(v,unit)		(((v)-1)/(unit)+1)
#define EZ(v,unit)		((v)?ENOUGH(v,unit):0)

#define XFER_MODE	0xf0
#define XFER_MWDMA	0x20
#define XFER_EPIO	0x01
#define XFER_PIO	0x00

static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q, int T, int UT)
{
	q->setup   = EZ(t->setup   * 1000,  T);
	q->act8b   = EZ(t->act8b   * 1000,  T);
	q->rec8b   = EZ(t->rec8b   * 1000,  T);
	q->cyc8b   = EZ(t->cyc8b   * 1000,  T);
	q->active  = EZ(t->active  * 1000,  T);
	q->recover = EZ(t->recover * 1000,  T);
	q->cycle   = EZ(t->cycle   * 1000,  T);
	q->udma    = EZ(t->udma    * 1000, UT);
}

static void ide_timing_merge(struct ide_timing *a, struct ide_timing *b, struct ide_timing *m, unsigned int what)
{
	if (what & IDE_TIMING_SETUP  ) m->setup   = max(a->setup,   b->setup);
	if (what & IDE_TIMING_ACT8B  ) m->act8b   = max(a->act8b,   b->act8b);
	if (what & IDE_TIMING_REC8B  ) m->rec8b   = max(a->rec8b,   b->rec8b);
	if (what & IDE_TIMING_CYC8B  ) m->cyc8b   = max(a->cyc8b,   b->cyc8b);
	if (what & IDE_TIMING_ACTIVE ) m->active  = max(a->active,  b->active);
	if (what & IDE_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
	if (what & IDE_TIMING_CYCLE  ) m->cycle   = max(a->cycle,   b->cycle);
	if (what & IDE_TIMING_UDMA   ) m->udma    = max(a->udma,    b->udma);
}

static struct ide_timing* ide_timing_find_mode(short speed)
{
	struct ide_timing *t;

	for (t = ide_timing; t->mode != speed; t++)
		if (t->mode < 0)
			return NULL;
	return t; 
}

static int ide_timing_compute(ide_drive_t *drive, short speed, struct ide_timing *t, int T, int UT)
{
	struct hd_driveid *id = drive->id;
	struct ide_timing *s, p;

/*
 * Find the mode.
 */

	if (!(s = ide_timing_find_mode(speed)))
		return -EINVAL;

/*
 * Copy the timing from the table.
 */

	*t = *s;

/*
 * If the drive is an EIDE drive, it can tell us it needs extended
 * PIO/MWDMA cycle timing.
 */

	if (id && id->field_valid & 2) {	/* EIDE drive */

		memset(&p, 0, sizeof(p));

		switch (speed & XFER_MODE) {

			case XFER_PIO:
				if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = id->eide_pio;
						    else p.cycle = p.cyc8b = id->eide_pio_iordy;
				break;

			case XFER_MWDMA:
				p.cycle = id->eide_dma_min;
				break;
		}

		ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
	}

/*
 * Convert the timing to bus clock counts.
 */

	ide_timing_quantize(t, t, T, UT);

/*
 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
 * and some other commands. We have to ensure that the DMA cycle timing is
 * slower/equal than the fastest PIO timing.
 */

	if ((speed & XFER_MODE) != XFER_PIO) {
		u8 pio = ide_get_best_pio_mode(drive, 255, 5);
		ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT);
		ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
	}

/*
 * Lengthen active & recovery time so that cycle time is correct.
 */

	if (t->act8b + t->rec8b < t->cyc8b) {
		t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
		t->rec8b = t->cyc8b - t->act8b;
	}

	if (t->active + t->recover < t->cycle) {
		t->active += (t->cycle - (t->active + t->recover)) / 2;
		t->recover = t->cycle - t->active;
	}

	return 0;
}

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef _IDE_TIMING_H
	2	#define _IDE_TIMING_H
	3
	4	/*
1da177e4 LT	5	* Copyright (c) 1999-2001 Vojtech Pavlik
	6	*/
	7
	8	/*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* Should you need to contact me, the author, you can do so either by
	24	* e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail:
	25	* Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
	26	*/
	27
2665b891	28	#include <linux/kernel.h>
1da177e4 LT	29	#include <linux/hdreg.h>
1da177e4 LT	30
1da177e4 LT	31	struct ide_timing {
	32	short mode;
	33	short setup; /* t1 */
	34	short act8b; /* t2 for 8-bit io */
	35	short rec8b; /* t2i for 8-bit io */
	36	short cyc8b; /* t0 for 8-bit io */
	37	short active; /* t2 or tD */
	38	short recover; /* t2i or tK */
	39	short cycle; /* t0 */
	40	short udma; /* t2CYCTYP/2 */
	41	};
	42
	43	/*
	44	* PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
	45	* These were taken from ATA/ATAPI-6 standard, rev 0a, except
	46	* for PIO 5, which is a nonstandard extension and UDMA6, which
	47	* is currently supported only by Maxtor drives.
	48	*/
	49
	50	static struct ide_timing ide_timing[] = {
	51
	52	{ XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
	53	{ XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
	54	{ XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
	55	{ XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
	56
	57	{ XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
	58	{ XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
	59	{ XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
	60
1da177e4 LT	61	{ XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
	62	{ XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
	63	{ XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
f0ffc987	64
1da177e4 LT	65	{ XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
	66	{ XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
	67	{ XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
	68
	69	{ XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 },
	70	{ XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
	71	{ XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
	72
	73	{ XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
	74	{ XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
	75	{ XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
	76
	77	{ XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 },
	78
	79	{ -1 }
	80	};
	81
	82	#define IDE_TIMING_SETUP 0x01
	83	#define IDE_TIMING_ACT8B 0x02
	84	#define IDE_TIMING_REC8B 0x04
	85	#define IDE_TIMING_CYC8B 0x08
	86	#define IDE_TIMING_8BIT 0x0e
	87	#define IDE_TIMING_ACTIVE 0x10
	88	#define IDE_TIMING_RECOVER 0x20
	89	#define IDE_TIMING_CYCLE 0x40
	90	#define IDE_TIMING_UDMA 0x80
	91	#define IDE_TIMING_ALL 0xff
	92
2665b891 CB	93	#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
2665b891 CB	94	#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1da177e4 LT	95
1da177e4 LT	96	#define XFER_MODE 0xf0
1da177e4	97	#define XFER_MWDMA 0x20
1da177e4 LT	98	#define XFER_EPIO 0x01
	99	#define XFER_PIO 0x00
	100
1da177e4 LT	101	static void ide_timing_quantize(struct ide_timing t, struct ide_timing q, int T, int UT)
	102	{
	103	q->setup = EZ(t->setup * 1000, T);
	104	q->act8b = EZ(t->act8b * 1000, T);
	105	q->rec8b = EZ(t->rec8b * 1000, T);
	106	q->cyc8b = EZ(t->cyc8b * 1000, T);
	107	q->active = EZ(t->active * 1000, T);
	108	q->recover = EZ(t->recover * 1000, T);
	109	q->cycle = EZ(t->cycle * 1000, T);
	110	q->udma = EZ(t->udma * 1000, UT);
	111	}
	112
	113	static void ide_timing_merge(struct ide_timing a, struct ide_timing b, struct ide_timing *m, unsigned int what)
	114	{
2665b891 CB	115	if (what & IDE_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
	116	if (what & IDE_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
	117	if (what & IDE_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
	118	if (what & IDE_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
	119	if (what & IDE_TIMING_ACTIVE ) m->active = max(a->active, b->active);
	120	if (what & IDE_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
	121	if (what & IDE_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
	122	if (what & IDE_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1da177e4 LT	123	}
	124
	125	static struct ide_timing* ide_timing_find_mode(short speed)
	126	{
	127	struct ide_timing *t;
	128
	129	for (t = ide_timing; t->mode != speed; t++)
	130	if (t->mode < 0)
	131	return NULL;
	132	return t;
	133	}
	134
	135	static int ide_timing_compute(ide_drive_t drive, short speed, struct ide_timing t, int T, int UT)
	136	{
	137	struct hd_driveid *id = drive->id;
	138	struct ide_timing *s, p;
	139
	140	/*
	141	* Find the mode.
	142	*/
	143
	144	if (!(s = ide_timing_find_mode(speed)))
	145	return -EINVAL;
	146
17c1033d SS	147	/*
	148	* Copy the timing from the table.
	149	*/
	150
	151	t = s;
	152
1da177e4 LT	153	/*
	154	* If the drive is an EIDE drive, it can tell us it needs extended
	155	* PIO/MWDMA cycle timing.
	156	*/
	157
	158	if (id && id->field_valid & 2) { /* EIDE drive */
	159
	160	memset(&p, 0, sizeof(p));
	161
	162	switch (speed & XFER_MODE) {
	163
	164	case XFER_PIO:
	165	if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = id->eide_pio;
	166	else p.cycle = p.cyc8b = id->eide_pio_iordy;
	167	break;
	168
	169	case XFER_MWDMA:
	170	p.cycle = id->eide_dma_min;
	171	break;
	172	}
	173
	174	ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE \| IDE_TIMING_CYC8B);
	175	}
	176
	177	/*
	178	* Convert the timing to bus clock counts.
	179	*/
	180
17c1033d	181	ide_timing_quantize(t, t, T, UT);
1da177e4 LT	182
	183	/*
	184	* Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
	185	* and some other commands. We have to ensure that the DMA cycle timing is
	186	* slower/equal than the fastest PIO timing.
	187	*/
	188
	189	if ((speed & XFER_MODE) != XFER_PIO) {
6a824c92 BZ	190	u8 pio = ide_get_best_pio_mode(drive, 255, 5);
6a824c92 BZ	191	ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT);
1da177e4 LT	192	ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
	193	}
	194
	195	/*
efad798b	196	* Lengthen active & recovery time so that cycle time is correct.
1da177e4 LT	197	*/
	198
	199	if (t->act8b + t->rec8b < t->cyc8b) {
	200	t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
	201	t->rec8b = t->cyc8b - t->act8b;
	202	}
	203
	204	if (t->active + t->recover < t->cycle) {
	205	t->active += (t->cycle - (t->active + t->recover)) / 2;
	206	t->recover = t->cycle - t->active;
	207	}
	208
	209	return 0;
	210	}
	211
	212	#endif