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26a940e2 PP |
1 | /* |
2 | * linux/drivers/ide/mips/au1xxx-ide.c version 01.30.00 Aug. 02 2005 | |
3 | * | |
4 | * BRIEF MODULE DESCRIPTION | |
5 | * AMD Alchemy Au1xxx IDE interface routines over the Static Bus | |
6 | * | |
7 | * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it under | |
10 | * the terms of the GNU General Public License as published by the Free Software | |
11 | * Foundation; either version 2 of the License, or (at your option) any later | |
12 | * version. | |
13 | * | |
14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, | |
15 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND | |
16 | * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR | |
17 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
18 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
19 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
20 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
21 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
22 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
23 | * POSSIBILITY OF SUCH DAMAGE. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License along with | |
26 | * this program; if not, write to the Free Software Foundation, Inc., | |
27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
28 | * | |
29 | * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE | |
30 | * Interface and Linux Device Driver" Application Note. | |
31 | */ | |
26a940e2 PP |
32 | #include <linux/types.h> |
33 | #include <linux/module.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/delay.h> | |
8f29e650 JC |
36 | #include <linux/platform_device.h> |
37 | ||
26a940e2 PP |
38 | #include <linux/init.h> |
39 | #include <linux/ide.h> | |
40 | #include <linux/sysdev.h> | |
41 | ||
42 | #include <linux/dma-mapping.h> | |
43 | ||
8f29e650 JC |
44 | #include "ide-timing.h" |
45 | ||
26a940e2 PP |
46 | #include <asm/io.h> |
47 | #include <asm/mach-au1x00/au1xxx.h> | |
48 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
49 | ||
26a940e2 PP |
50 | #include <asm/mach-au1x00/au1xxx_ide.h> |
51 | ||
52 | #define DRV_NAME "au1200-ide" | |
53 | #define DRV_VERSION "1.0" | |
8f29e650 | 54 | #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>" |
26a940e2 | 55 | |
8f29e650 JC |
56 | /* enable the burstmode in the dbdma */ |
57 | #define IDE_AU1XXX_BURSTMODE 1 | |
26a940e2 | 58 | |
8f29e650 JC |
59 | static _auide_hwif auide_hwif; |
60 | static int dbdma_init_done; | |
26a940e2 | 61 | |
26a940e2 PP |
62 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) |
63 | ||
8f29e650 | 64 | void auide_insw(unsigned long port, void *addr, u32 count) |
26a940e2 | 65 | { |
8f29e650 JC |
66 | _auide_hwif *ahwif = &auide_hwif; |
67 | chan_tab_t *ctp; | |
68 | au1x_ddma_desc_t *dp; | |
26a940e2 | 69 | |
8f29e650 JC |
70 | if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, |
71 | DDMA_FLAGS_NOIE)) { | |
72 | printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__); | |
73 | return; | |
74 | } | |
75 | ctp = *((chan_tab_t **)ahwif->rx_chan); | |
76 | dp = ctp->cur_ptr; | |
77 | while (dp->dscr_cmd0 & DSCR_CMD0_V) | |
78 | ; | |
79 | ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); | |
26a940e2 PP |
80 | } |
81 | ||
8f29e650 | 82 | void auide_outsw(unsigned long port, void *addr, u32 count) |
26a940e2 | 83 | { |
8f29e650 JC |
84 | _auide_hwif *ahwif = &auide_hwif; |
85 | chan_tab_t *ctp; | |
86 | au1x_ddma_desc_t *dp; | |
26a940e2 | 87 | |
8f29e650 JC |
88 | if(!put_source_flags(ahwif->tx_chan, (void*)addr, |
89 | count << 1, DDMA_FLAGS_NOIE)) { | |
90 | printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__); | |
91 | return; | |
92 | } | |
93 | ctp = *((chan_tab_t **)ahwif->tx_chan); | |
94 | dp = ctp->cur_ptr; | |
95 | while (dp->dscr_cmd0 & DSCR_CMD0_V) | |
96 | ; | |
97 | ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); | |
26a940e2 PP |
98 | } |
99 | ||
26a940e2 | 100 | #endif |
26a940e2 PP |
101 | |
102 | static void auide_tune_drive(ide_drive_t *drive, byte pio) | |
103 | { | |
8f29e650 JC |
104 | int mem_sttime; |
105 | int mem_stcfg; | |
106 | u8 speed; | |
107 | ||
108 | /* get the best pio mode for the drive */ | |
2134758d | 109 | pio = ide_get_best_pio_mode(drive, pio, 4); |
8f29e650 JC |
110 | |
111 | printk(KERN_INFO "%s: setting Au1XXX IDE to PIO mode%d\n", | |
112 | drive->name, pio); | |
113 | ||
114 | mem_sttime = 0; | |
115 | mem_stcfg = au_readl(MEM_STCFG2); | |
116 | ||
117 | /* set pio mode! */ | |
118 | switch(pio) { | |
119 | case 0: | |
120 | mem_sttime = SBC_IDE_TIMING(PIO0); | |
121 | ||
122 | /* set configuration for RCS2# */ | |
123 | mem_stcfg |= TS_MASK; | |
124 | mem_stcfg &= ~TCSOE_MASK; | |
125 | mem_stcfg &= ~TOECS_MASK; | |
126 | mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS; | |
127 | break; | |
128 | ||
129 | case 1: | |
130 | mem_sttime = SBC_IDE_TIMING(PIO1); | |
131 | ||
132 | /* set configuration for RCS2# */ | |
133 | mem_stcfg |= TS_MASK; | |
134 | mem_stcfg &= ~TCSOE_MASK; | |
135 | mem_stcfg &= ~TOECS_MASK; | |
136 | mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS; | |
137 | break; | |
138 | ||
139 | case 2: | |
140 | mem_sttime = SBC_IDE_TIMING(PIO2); | |
141 | ||
142 | /* set configuration for RCS2# */ | |
143 | mem_stcfg &= ~TS_MASK; | |
144 | mem_stcfg &= ~TCSOE_MASK; | |
145 | mem_stcfg &= ~TOECS_MASK; | |
146 | mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS; | |
147 | break; | |
148 | ||
149 | case 3: | |
150 | mem_sttime = SBC_IDE_TIMING(PIO3); | |
151 | ||
152 | /* set configuration for RCS2# */ | |
153 | mem_stcfg &= ~TS_MASK; | |
154 | mem_stcfg &= ~TCSOE_MASK; | |
155 | mem_stcfg &= ~TOECS_MASK; | |
156 | mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS; | |
157 | ||
158 | break; | |
159 | ||
160 | case 4: | |
161 | mem_sttime = SBC_IDE_TIMING(PIO4); | |
162 | ||
163 | /* set configuration for RCS2# */ | |
164 | mem_stcfg &= ~TS_MASK; | |
165 | mem_stcfg &= ~TCSOE_MASK; | |
166 | mem_stcfg &= ~TOECS_MASK; | |
167 | mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS; | |
168 | break; | |
169 | } | |
170 | ||
171 | au_writel(mem_sttime,MEM_STTIME2); | |
172 | au_writel(mem_stcfg,MEM_STCFG2); | |
173 | ||
174 | speed = pio + XFER_PIO_0; | |
175 | ide_config_drive_speed(drive, speed); | |
26a940e2 PP |
176 | } |
177 | ||
178 | static int auide_tune_chipset (ide_drive_t *drive, u8 speed) | |
179 | { | |
8f29e650 JC |
180 | int mem_sttime; |
181 | int mem_stcfg; | |
26a940e2 | 182 | |
8f29e650 JC |
183 | mem_sttime = 0; |
184 | mem_stcfg = au_readl(MEM_STCFG2); | |
26a940e2 | 185 | |
8f29e650 JC |
186 | if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) { |
187 | auide_tune_drive(drive, speed - XFER_PIO_0); | |
188 | return 0; | |
189 | } | |
a523a175 | 190 | |
8f29e650 | 191 | switch(speed) { |
26a940e2 | 192 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
8f29e650 JC |
193 | case XFER_MW_DMA_2: |
194 | mem_sttime = SBC_IDE_TIMING(MDMA2); | |
195 | ||
196 | /* set configuration for RCS2# */ | |
197 | mem_stcfg &= ~TS_MASK; | |
198 | mem_stcfg &= ~TCSOE_MASK; | |
199 | mem_stcfg &= ~TOECS_MASK; | |
200 | mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS; | |
201 | ||
8f29e650 JC |
202 | break; |
203 | case XFER_MW_DMA_1: | |
204 | mem_sttime = SBC_IDE_TIMING(MDMA1); | |
205 | ||
206 | /* set configuration for RCS2# */ | |
207 | mem_stcfg &= ~TS_MASK; | |
208 | mem_stcfg &= ~TCSOE_MASK; | |
209 | mem_stcfg &= ~TOECS_MASK; | |
210 | mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS; | |
211 | ||
8f29e650 JC |
212 | break; |
213 | case XFER_MW_DMA_0: | |
214 | mem_sttime = SBC_IDE_TIMING(MDMA0); | |
215 | ||
216 | /* set configuration for RCS2# */ | |
217 | mem_stcfg |= TS_MASK; | |
218 | mem_stcfg &= ~TCSOE_MASK; | |
219 | mem_stcfg &= ~TOECS_MASK; | |
220 | mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS; | |
221 | ||
8f29e650 | 222 | break; |
26a940e2 | 223 | #endif |
8f29e650 JC |
224 | default: |
225 | return 1; | |
226 | } | |
a523a175 BZ |
227 | |
228 | if (ide_config_drive_speed(drive, speed)) | |
8f29e650 | 229 | return 1; |
26a940e2 | 230 | |
8f29e650 JC |
231 | au_writel(mem_sttime,MEM_STTIME2); |
232 | au_writel(mem_stcfg,MEM_STCFG2); | |
26a940e2 | 233 | |
8f29e650 | 234 | return 0; |
26a940e2 PP |
235 | } |
236 | ||
237 | /* | |
238 | * Multi-Word DMA + DbDMA functions | |
239 | */ | |
26a940e2 | 240 | |
8f29e650 | 241 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
26a940e2 PP |
242 | |
243 | static int auide_build_sglist(ide_drive_t *drive, struct request *rq) | |
244 | { | |
8f29e650 JC |
245 | ide_hwif_t *hwif = drive->hwif; |
246 | _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; | |
247 | struct scatterlist *sg = hwif->sg_table; | |
26a940e2 | 248 | |
8f29e650 | 249 | ide_map_sg(drive, rq); |
26a940e2 | 250 | |
8f29e650 JC |
251 | if (rq_data_dir(rq) == READ) |
252 | hwif->sg_dma_direction = DMA_FROM_DEVICE; | |
253 | else | |
254 | hwif->sg_dma_direction = DMA_TO_DEVICE; | |
26a940e2 | 255 | |
8f29e650 JC |
256 | return dma_map_sg(ahwif->dev, sg, hwif->sg_nents, |
257 | hwif->sg_dma_direction); | |
26a940e2 PP |
258 | } |
259 | ||
260 | static int auide_build_dmatable(ide_drive_t *drive) | |
261 | { | |
8f29e650 JC |
262 | int i, iswrite, count = 0; |
263 | ide_hwif_t *hwif = HWIF(drive); | |
264 | ||
265 | struct request *rq = HWGROUP(drive)->rq; | |
266 | ||
267 | _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; | |
268 | struct scatterlist *sg; | |
269 | ||
270 | iswrite = (rq_data_dir(rq) == WRITE); | |
271 | /* Save for interrupt context */ | |
272 | ahwif->drive = drive; | |
273 | ||
274 | /* Build sglist */ | |
275 | hwif->sg_nents = i = auide_build_sglist(drive, rq); | |
276 | ||
277 | if (!i) | |
278 | return 0; | |
279 | ||
280 | /* fill the descriptors */ | |
281 | sg = hwif->sg_table; | |
282 | while (i && sg_dma_len(sg)) { | |
283 | u32 cur_addr; | |
284 | u32 cur_len; | |
285 | ||
286 | cur_addr = sg_dma_address(sg); | |
287 | cur_len = sg_dma_len(sg); | |
288 | ||
289 | while (cur_len) { | |
290 | u32 flags = DDMA_FLAGS_NOIE; | |
291 | unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; | |
292 | ||
293 | if (++count >= PRD_ENTRIES) { | |
294 | printk(KERN_WARNING "%s: DMA table too small\n", | |
295 | drive->name); | |
296 | goto use_pio_instead; | |
297 | } | |
298 | ||
299 | /* Lets enable intr for the last descriptor only */ | |
300 | if (1==i) | |
301 | flags = DDMA_FLAGS_IE; | |
302 | else | |
303 | flags = DDMA_FLAGS_NOIE; | |
304 | ||
305 | if (iswrite) { | |
306 | if(!put_source_flags(ahwif->tx_chan, | |
307 | (void*)(page_address(sg->page) | |
308 | + sg->offset), | |
309 | tc, flags)) { | |
310 | printk(KERN_ERR "%s failed %d\n", | |
311 | __FUNCTION__, __LINE__); | |
26a940e2 | 312 | } |
8f29e650 | 313 | } else |
26a940e2 | 314 | { |
8f29e650 JC |
315 | if(!put_dest_flags(ahwif->rx_chan, |
316 | (void*)(page_address(sg->page) | |
317 | + sg->offset), | |
318 | tc, flags)) { | |
319 | printk(KERN_ERR "%s failed %d\n", | |
320 | __FUNCTION__, __LINE__); | |
26a940e2 | 321 | } |
8f29e650 | 322 | } |
26a940e2 | 323 | |
8f29e650 JC |
324 | cur_addr += tc; |
325 | cur_len -= tc; | |
326 | } | |
327 | sg++; | |
328 | i--; | |
329 | } | |
26a940e2 | 330 | |
8f29e650 JC |
331 | if (count) |
332 | return 1; | |
26a940e2 | 333 | |
8f29e650 JC |
334 | use_pio_instead: |
335 | dma_unmap_sg(ahwif->dev, | |
336 | hwif->sg_table, | |
337 | hwif->sg_nents, | |
338 | hwif->sg_dma_direction); | |
26a940e2 | 339 | |
8f29e650 | 340 | return 0; /* revert to PIO for this request */ |
26a940e2 PP |
341 | } |
342 | ||
343 | static int auide_dma_end(ide_drive_t *drive) | |
344 | { | |
8f29e650 JC |
345 | ide_hwif_t *hwif = HWIF(drive); |
346 | _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; | |
26a940e2 | 347 | |
8f29e650 JC |
348 | if (hwif->sg_nents) { |
349 | dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents, | |
350 | hwif->sg_dma_direction); | |
351 | hwif->sg_nents = 0; | |
352 | } | |
26a940e2 | 353 | |
8f29e650 | 354 | return 0; |
26a940e2 PP |
355 | } |
356 | ||
357 | static void auide_dma_start(ide_drive_t *drive ) | |
358 | { | |
26a940e2 PP |
359 | } |
360 | ||
26a940e2 PP |
361 | |
362 | static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command) | |
363 | { | |
8f29e650 JC |
364 | /* issue cmd to drive */ |
365 | ide_execute_command(drive, command, &ide_dma_intr, | |
366 | (2*WAIT_CMD), NULL); | |
26a940e2 PP |
367 | } |
368 | ||
369 | static int auide_dma_setup(ide_drive_t *drive) | |
8f29e650 JC |
370 | { |
371 | struct request *rq = HWGROUP(drive)->rq; | |
26a940e2 | 372 | |
8f29e650 JC |
373 | if (!auide_build_dmatable(drive)) { |
374 | ide_map_sg(drive, rq); | |
375 | return 1; | |
376 | } | |
26a940e2 | 377 | |
8f29e650 JC |
378 | drive->waiting_for_dma = 1; |
379 | return 0; | |
26a940e2 PP |
380 | } |
381 | ||
382 | static int auide_dma_check(ide_drive_t *drive) | |
383 | { | |
75b1d975 | 384 | u8 speed = ide_max_dma_mode(drive); |
8f29e650 JC |
385 | |
386 | if( dbdma_init_done == 0 ){ | |
387 | auide_hwif.white_list = ide_in_drive_list(drive->id, | |
388 | dma_white_list); | |
389 | auide_hwif.black_list = ide_in_drive_list(drive->id, | |
390 | dma_black_list); | |
391 | auide_hwif.drive = drive; | |
392 | auide_ddma_init(&auide_hwif); | |
393 | dbdma_init_done = 1; | |
394 | } | |
26a940e2 | 395 | |
8f29e650 JC |
396 | /* Is the drive in our DMA black list? */ |
397 | ||
398 | if ( auide_hwif.black_list ) { | |
399 | drive->using_dma = 0; | |
400 | ||
401 | /* Borrowed the warning message from ide-dma.c */ | |
26a940e2 | 402 | |
8f29e650 JC |
403 | printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n", |
404 | drive->name, drive->id->model); | |
405 | } | |
406 | else | |
407 | drive->using_dma = 1; | |
408 | ||
8f29e650 | 409 | if (drive->autodma && (speed & XFER_MODE) != XFER_PIO) |
3608b5d7 | 410 | return 0; |
8f29e650 | 411 | |
3608b5d7 | 412 | return -1; |
26a940e2 PP |
413 | } |
414 | ||
415 | static int auide_dma_test_irq(ide_drive_t *drive) | |
8f29e650 JC |
416 | { |
417 | if (drive->waiting_for_dma == 0) | |
418 | printk(KERN_WARNING "%s: ide_dma_test_irq \ | |
26a940e2 PP |
419 | called while not waiting\n", drive->name); |
420 | ||
8f29e650 JC |
421 | /* If dbdma didn't execute the STOP command yet, the |
422 | * active bit is still set | |
26a940e2 | 423 | */ |
8f29e650 JC |
424 | drive->waiting_for_dma++; |
425 | if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) { | |
426 | printk(KERN_WARNING "%s: timeout waiting for ddma to \ | |
26a940e2 | 427 | complete\n", drive->name); |
8f29e650 JC |
428 | return 1; |
429 | } | |
430 | udelay(10); | |
431 | return 0; | |
26a940e2 PP |
432 | } |
433 | ||
ccf35289 | 434 | static void auide_dma_host_on(ide_drive_t *drive) |
26a940e2 | 435 | { |
26a940e2 PP |
436 | } |
437 | ||
438 | static int auide_dma_on(ide_drive_t *drive) | |
439 | { | |
8f29e650 | 440 | drive->using_dma = 1; |
ccf35289 BZ |
441 | |
442 | return 0; | |
26a940e2 PP |
443 | } |
444 | ||
7469aaf6 | 445 | static void auide_dma_host_off(ide_drive_t *drive) |
26a940e2 | 446 | { |
26a940e2 PP |
447 | } |
448 | ||
7469aaf6 | 449 | static void auide_dma_off_quietly(ide_drive_t *drive) |
26a940e2 | 450 | { |
8f29e650 | 451 | drive->using_dma = 0; |
26a940e2 PP |
452 | } |
453 | ||
841d2a9b | 454 | static void auide_dma_lost_irq(ide_drive_t *drive) |
26a940e2 | 455 | { |
8f29e650 | 456 | printk(KERN_ERR "%s: IRQ lost\n", drive->name); |
26a940e2 PP |
457 | } |
458 | ||
53e62d3a | 459 | static void auide_ddma_tx_callback(int irq, void *param) |
26a940e2 | 460 | { |
8f29e650 JC |
461 | _auide_hwif *ahwif = (_auide_hwif*)param; |
462 | ahwif->drive->waiting_for_dma = 0; | |
26a940e2 PP |
463 | } |
464 | ||
53e62d3a | 465 | static void auide_ddma_rx_callback(int irq, void *param) |
26a940e2 | 466 | { |
8f29e650 JC |
467 | _auide_hwif *ahwif = (_auide_hwif*)param; |
468 | ahwif->drive->waiting_for_dma = 0; | |
469 | } | |
470 | ||
471 | #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ | |
26a940e2 | 472 | |
8f29e650 JC |
473 | static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags) |
474 | { | |
475 | dev->dev_id = dev_id; | |
476 | dev->dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR; | |
477 | dev->dev_intlevel = 0; | |
478 | dev->dev_intpolarity = 0; | |
479 | dev->dev_tsize = tsize; | |
480 | dev->dev_devwidth = devwidth; | |
481 | dev->dev_flags = flags; | |
26a940e2 | 482 | } |
8f29e650 JC |
483 | |
484 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) | |
26a940e2 | 485 | |
c283f5db | 486 | static void auide_dma_timeout(ide_drive_t *drive) |
26a940e2 | 487 | { |
c283f5db | 488 | ide_hwif_t *hwif = HWIF(drive); |
26a940e2 | 489 | |
8f29e650 | 490 | printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name); |
26a940e2 | 491 | |
c283f5db SS |
492 | if (hwif->ide_dma_test_irq(drive)) |
493 | return; | |
26a940e2 | 494 | |
c283f5db | 495 | hwif->ide_dma_end(drive); |
26a940e2 | 496 | } |
8f29e650 | 497 | |
26a940e2 | 498 | |
8f29e650 JC |
499 | static int auide_ddma_init(_auide_hwif *auide) { |
500 | ||
501 | dbdev_tab_t source_dev_tab, target_dev_tab; | |
502 | u32 dev_id, tsize, devwidth, flags; | |
503 | ide_hwif_t *hwif = auide->hwif; | |
26a940e2 | 504 | |
8f29e650 | 505 | dev_id = AU1XXX_ATA_DDMA_REQ; |
26a940e2 | 506 | |
8f29e650 JC |
507 | if (auide->white_list || auide->black_list) { |
508 | tsize = 8; | |
509 | devwidth = 32; | |
510 | } | |
511 | else { | |
512 | tsize = 1; | |
513 | devwidth = 16; | |
514 | ||
515 | printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model); | |
516 | printk(KERN_ERR " please read 'Documentation/mips/AU1xxx_IDE.README'"); | |
517 | } | |
26a940e2 | 518 | |
8f29e650 JC |
519 | #ifdef IDE_AU1XXX_BURSTMODE |
520 | flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; | |
26a940e2 | 521 | #else |
8f29e650 | 522 | flags = DEV_FLAGS_SYNC; |
26a940e2 PP |
523 | #endif |
524 | ||
8f29e650 JC |
525 | /* setup dev_tab for tx channel */ |
526 | auide_init_dbdma_dev( &source_dev_tab, | |
527 | dev_id, | |
528 | tsize, devwidth, DEV_FLAGS_OUT | flags); | |
529 | auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
530 | ||
531 | auide_init_dbdma_dev( &source_dev_tab, | |
532 | dev_id, | |
533 | tsize, devwidth, DEV_FLAGS_IN | flags); | |
534 | auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
535 | ||
536 | /* We also need to add a target device for the DMA */ | |
537 | auide_init_dbdma_dev( &target_dev_tab, | |
538 | (u32)DSCR_CMD0_ALWAYS, | |
539 | tsize, devwidth, DEV_FLAGS_ANYUSE); | |
540 | auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); | |
541 | ||
542 | /* Get a channel for TX */ | |
543 | auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id, | |
544 | auide->tx_dev_id, | |
545 | auide_ddma_tx_callback, | |
546 | (void*)auide); | |
547 | ||
548 | /* Get a channel for RX */ | |
549 | auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, | |
550 | auide->target_dev_id, | |
551 | auide_ddma_rx_callback, | |
552 | (void*)auide); | |
553 | ||
554 | auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, | |
555 | NUM_DESCRIPTORS); | |
556 | auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, | |
557 | NUM_DESCRIPTORS); | |
558 | ||
559 | hwif->dmatable_cpu = dma_alloc_coherent(auide->dev, | |
560 | PRD_ENTRIES * PRD_BYTES, /* 1 Page */ | |
561 | &hwif->dmatable_dma, GFP_KERNEL); | |
562 | ||
563 | au1xxx_dbdma_start( auide->tx_chan ); | |
564 | au1xxx_dbdma_start( auide->rx_chan ); | |
565 | ||
566 | return 0; | |
567 | } | |
26a940e2 | 568 | #else |
8f29e650 JC |
569 | |
570 | static int auide_ddma_init( _auide_hwif *auide ) | |
571 | { | |
572 | dbdev_tab_t source_dev_tab; | |
573 | int flags; | |
26a940e2 | 574 | |
8f29e650 JC |
575 | #ifdef IDE_AU1XXX_BURSTMODE |
576 | flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; | |
577 | #else | |
578 | flags = DEV_FLAGS_SYNC; | |
26a940e2 | 579 | #endif |
26a940e2 | 580 | |
8f29e650 JC |
581 | /* setup dev_tab for tx channel */ |
582 | auide_init_dbdma_dev( &source_dev_tab, | |
583 | (u32)DSCR_CMD0_ALWAYS, | |
584 | 8, 32, DEV_FLAGS_OUT | flags); | |
585 | auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
586 | ||
587 | auide_init_dbdma_dev( &source_dev_tab, | |
588 | (u32)DSCR_CMD0_ALWAYS, | |
589 | 8, 32, DEV_FLAGS_IN | flags); | |
590 | auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
591 | ||
592 | /* Get a channel for TX */ | |
593 | auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS, | |
594 | auide->tx_dev_id, | |
595 | NULL, | |
596 | (void*)auide); | |
597 | ||
598 | /* Get a channel for RX */ | |
599 | auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, | |
600 | DSCR_CMD0_ALWAYS, | |
601 | NULL, | |
602 | (void*)auide); | |
603 | ||
604 | auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, | |
605 | NUM_DESCRIPTORS); | |
606 | auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, | |
607 | NUM_DESCRIPTORS); | |
608 | ||
609 | au1xxx_dbdma_start( auide->tx_chan ); | |
610 | au1xxx_dbdma_start( auide->rx_chan ); | |
611 | ||
612 | return 0; | |
26a940e2 | 613 | } |
8f29e650 | 614 | #endif |
26a940e2 PP |
615 | |
616 | static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif) | |
617 | { | |
8f29e650 JC |
618 | int i; |
619 | unsigned long *ata_regs = hw->io_ports; | |
620 | ||
621 | /* FIXME? */ | |
622 | for (i = 0; i < IDE_CONTROL_OFFSET; i++) { | |
623 | *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET); | |
624 | } | |
625 | ||
626 | /* set the Alternative Status register */ | |
627 | *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET); | |
26a940e2 PP |
628 | } |
629 | ||
630 | static int au_ide_probe(struct device *dev) | |
631 | { | |
632 | struct platform_device *pdev = to_platform_device(dev); | |
8f29e650 JC |
633 | _auide_hwif *ahwif = &auide_hwif; |
634 | ide_hwif_t *hwif; | |
26a940e2 | 635 | struct resource *res; |
1918fd63 | 636 | hw_regs_t *hw; |
26a940e2 PP |
637 | int ret = 0; |
638 | ||
639 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) | |
8f29e650 | 640 | char *mode = "MWDMA2"; |
26a940e2 | 641 | #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) |
8f29e650 | 642 | char *mode = "PIO+DDMA(offload)"; |
26a940e2 PP |
643 | #endif |
644 | ||
8f29e650 JC |
645 | memset(&auide_hwif, 0, sizeof(_auide_hwif)); |
646 | auide_hwif.dev = 0; | |
26a940e2 PP |
647 | |
648 | ahwif->dev = dev; | |
649 | ahwif->irq = platform_get_irq(pdev, 0); | |
650 | ||
651 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
652 | ||
653 | if (res == NULL) { | |
654 | pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id); | |
655 | ret = -ENODEV; | |
48944738 DV |
656 | goto out; |
657 | } | |
658 | if (ahwif->irq < 0) { | |
659 | pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id); | |
660 | ret = -ENODEV; | |
26a940e2 PP |
661 | goto out; |
662 | } | |
663 | ||
8f29e650 | 664 | if (!request_mem_region (res->start, res->end-res->start, pdev->name)) { |
26a940e2 | 665 | pr_debug("%s: request_mem_region failed\n", DRV_NAME); |
8f29e650 | 666 | ret = -EBUSY; |
26a940e2 | 667 | goto out; |
8f29e650 | 668 | } |
26a940e2 PP |
669 | |
670 | ahwif->regbase = (u32)ioremap(res->start, res->end-res->start); | |
671 | if (ahwif->regbase == 0) { | |
672 | ret = -ENOMEM; | |
673 | goto out; | |
674 | } | |
675 | ||
8f29e650 JC |
676 | /* FIXME: This might possibly break PCMCIA IDE devices */ |
677 | ||
678 | hwif = &ide_hwifs[pdev->id]; | |
1918fd63 | 679 | hw = &hwif->hw; |
8f29e650 JC |
680 | hwif->irq = hw->irq = ahwif->irq; |
681 | hwif->chipset = ide_au1xxx; | |
26a940e2 | 682 | |
8f29e650 | 683 | auide_setup_ports(hw, ahwif); |
26a940e2 PP |
684 | memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports)); |
685 | ||
8f29e650 | 686 | hwif->ultra_mask = 0x0; /* Disable Ultra DMA */ |
26a940e2 | 687 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
8f29e650 JC |
688 | hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */ |
689 | hwif->swdma_mask = 0x00; | |
26a940e2 | 690 | #else |
8f29e650 JC |
691 | hwif->mwdma_mask = 0x0; |
692 | hwif->swdma_mask = 0x0; | |
693 | #endif | |
694 | ||
695 | hwif->noprobe = 0; | |
696 | hwif->drives[0].unmask = 1; | |
697 | hwif->drives[1].unmask = 1; | |
698 | ||
699 | /* hold should be on in all cases */ | |
700 | hwif->hold = 1; | |
2ad1e558 BZ |
701 | |
702 | hwif->mmio = 1; | |
8f29e650 JC |
703 | |
704 | /* If the user has selected DDMA assisted copies, | |
705 | then set up a few local I/O function entry points | |
706 | */ | |
707 | ||
708 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA | |
709 | hwif->INSW = auide_insw; | |
710 | hwif->OUTSW = auide_outsw; | |
26a940e2 | 711 | #endif |
8f29e650 JC |
712 | |
713 | hwif->tuneproc = &auide_tune_drive; | |
714 | hwif->speedproc = &auide_tune_chipset; | |
26a940e2 PP |
715 | |
716 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA | |
7469aaf6 | 717 | hwif->dma_off_quietly = &auide_dma_off_quietly; |
c283f5db | 718 | hwif->dma_timeout = &auide_dma_timeout; |
8f29e650 JC |
719 | |
720 | hwif->ide_dma_check = &auide_dma_check; | |
721 | hwif->dma_exec_cmd = &auide_dma_exec_cmd; | |
722 | hwif->dma_start = &auide_dma_start; | |
723 | hwif->ide_dma_end = &auide_dma_end; | |
724 | hwif->dma_setup = &auide_dma_setup; | |
725 | hwif->ide_dma_test_irq = &auide_dma_test_irq; | |
7469aaf6 | 726 | hwif->dma_host_off = &auide_dma_host_off; |
ccf35289 | 727 | hwif->dma_host_on = &auide_dma_host_on; |
841d2a9b | 728 | hwif->dma_lost_irq = &auide_dma_lost_irq; |
8f29e650 JC |
729 | hwif->ide_dma_on = &auide_dma_on; |
730 | ||
731 | hwif->autodma = 1; | |
732 | hwif->drives[0].autodma = hwif->autodma; | |
733 | hwif->drives[1].autodma = hwif->autodma; | |
734 | hwif->atapi_dma = 1; | |
735 | ||
26a940e2 | 736 | #else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ |
8f29e650 JC |
737 | hwif->autodma = 0; |
738 | hwif->channel = 0; | |
739 | hwif->hold = 1; | |
740 | hwif->select_data = 0; /* no chipset-specific code */ | |
741 | hwif->config_data = 0; /* no chipset-specific code */ | |
742 | ||
743 | hwif->drives[0].autodma = 0; | |
744 | hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */ | |
26a940e2 | 745 | #endif |
8f29e650 | 746 | hwif->drives[0].no_io_32bit = 1; |
26a940e2 | 747 | |
8f29e650 JC |
748 | auide_hwif.hwif = hwif; |
749 | hwif->hwif_data = &auide_hwif; | |
26a940e2 | 750 | |
8f29e650 JC |
751 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA |
752 | auide_ddma_init(&auide_hwif); | |
753 | dbdma_init_done = 1; | |
26a940e2 PP |
754 | #endif |
755 | ||
756 | probe_hwif_init(hwif); | |
5cbf79cd BZ |
757 | |
758 | ide_proc_register_port(hwif); | |
759 | ||
26a940e2 PP |
760 | dev_set_drvdata(dev, hwif); |
761 | ||
8f29e650 | 762 | printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode ); |
26a940e2 | 763 | |
8f29e650 JC |
764 | out: |
765 | return ret; | |
26a940e2 PP |
766 | } |
767 | ||
768 | static int au_ide_remove(struct device *dev) | |
769 | { | |
770 | struct platform_device *pdev = to_platform_device(dev); | |
771 | struct resource *res; | |
772 | ide_hwif_t *hwif = dev_get_drvdata(dev); | |
8f29e650 | 773 | _auide_hwif *ahwif = &auide_hwif; |
26a940e2 PP |
774 | |
775 | ide_unregister(hwif - ide_hwifs); | |
776 | ||
777 | iounmap((void *)ahwif->regbase); | |
778 | ||
779 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
780 | release_mem_region(res->start, res->end - res->start); | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
785 | static struct device_driver au1200_ide_driver = { | |
786 | .name = "au1200-ide", | |
787 | .bus = &platform_bus_type, | |
788 | .probe = au_ide_probe, | |
789 | .remove = au_ide_remove, | |
790 | }; | |
791 | ||
792 | static int __init au_ide_init(void) | |
793 | { | |
794 | return driver_register(&au1200_ide_driver); | |
795 | } | |
796 | ||
8f29e650 | 797 | static void __exit au_ide_exit(void) |
26a940e2 PP |
798 | { |
799 | driver_unregister(&au1200_ide_driver); | |
800 | } | |
801 | ||
26a940e2 PP |
802 | MODULE_LICENSE("GPL"); |
803 | MODULE_DESCRIPTION("AU1200 IDE driver"); | |
804 | ||
805 | module_init(au_ide_init); | |
806 | module_exit(au_ide_exit); |