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26a940e2 PP |
1 | /* |
2 | * linux/drivers/ide/mips/au1xxx-ide.c version 01.30.00 Aug. 02 2005 | |
3 | * | |
4 | * BRIEF MODULE DESCRIPTION | |
5 | * AMD Alchemy Au1xxx IDE interface routines over the Static Bus | |
6 | * | |
7 | * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it under | |
10 | * the terms of the GNU General Public License as published by the Free Software | |
11 | * Foundation; either version 2 of the License, or (at your option) any later | |
12 | * version. | |
13 | * | |
14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, | |
15 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND | |
16 | * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR | |
17 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
18 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
19 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
20 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
21 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
22 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
23 | * POSSIBILITY OF SUCH DAMAGE. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License along with | |
26 | * this program; if not, write to the Free Software Foundation, Inc., | |
27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
28 | * | |
29 | * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE | |
30 | * Interface and Linux Device Driver" Application Note. | |
31 | */ | |
26a940e2 PP |
32 | #include <linux/types.h> |
33 | #include <linux/module.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/delay.h> | |
8f29e650 JC |
36 | #include <linux/platform_device.h> |
37 | ||
26a940e2 PP |
38 | #include <linux/init.h> |
39 | #include <linux/ide.h> | |
40 | #include <linux/sysdev.h> | |
41 | ||
42 | #include <linux/dma-mapping.h> | |
43 | ||
8f29e650 JC |
44 | #include "ide-timing.h" |
45 | ||
26a940e2 PP |
46 | #include <asm/io.h> |
47 | #include <asm/mach-au1x00/au1xxx.h> | |
48 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
49 | ||
26a940e2 PP |
50 | #include <asm/mach-au1x00/au1xxx_ide.h> |
51 | ||
52 | #define DRV_NAME "au1200-ide" | |
53 | #define DRV_VERSION "1.0" | |
8f29e650 | 54 | #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>" |
26a940e2 | 55 | |
8f29e650 JC |
56 | /* enable the burstmode in the dbdma */ |
57 | #define IDE_AU1XXX_BURSTMODE 1 | |
26a940e2 | 58 | |
8f29e650 JC |
59 | static _auide_hwif auide_hwif; |
60 | static int dbdma_init_done; | |
26a940e2 | 61 | |
26a940e2 PP |
62 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) |
63 | ||
8f29e650 | 64 | void auide_insw(unsigned long port, void *addr, u32 count) |
26a940e2 | 65 | { |
8f29e650 JC |
66 | _auide_hwif *ahwif = &auide_hwif; |
67 | chan_tab_t *ctp; | |
68 | au1x_ddma_desc_t *dp; | |
26a940e2 | 69 | |
8f29e650 JC |
70 | if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, |
71 | DDMA_FLAGS_NOIE)) { | |
72 | printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__); | |
73 | return; | |
74 | } | |
75 | ctp = *((chan_tab_t **)ahwif->rx_chan); | |
76 | dp = ctp->cur_ptr; | |
77 | while (dp->dscr_cmd0 & DSCR_CMD0_V) | |
78 | ; | |
79 | ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); | |
26a940e2 PP |
80 | } |
81 | ||
8f29e650 | 82 | void auide_outsw(unsigned long port, void *addr, u32 count) |
26a940e2 | 83 | { |
8f29e650 JC |
84 | _auide_hwif *ahwif = &auide_hwif; |
85 | chan_tab_t *ctp; | |
86 | au1x_ddma_desc_t *dp; | |
26a940e2 | 87 | |
8f29e650 JC |
88 | if(!put_source_flags(ahwif->tx_chan, (void*)addr, |
89 | count << 1, DDMA_FLAGS_NOIE)) { | |
90 | printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__); | |
91 | return; | |
92 | } | |
93 | ctp = *((chan_tab_t **)ahwif->tx_chan); | |
94 | dp = ctp->cur_ptr; | |
95 | while (dp->dscr_cmd0 & DSCR_CMD0_V) | |
96 | ; | |
97 | ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); | |
26a940e2 PP |
98 | } |
99 | ||
26a940e2 | 100 | #endif |
26a940e2 | 101 | |
26bcb879 | 102 | static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio) |
26a940e2 | 103 | { |
88b2b32b | 104 | int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); |
8f29e650 JC |
105 | |
106 | /* set pio mode! */ | |
107 | switch(pio) { | |
108 | case 0: | |
109 | mem_sttime = SBC_IDE_TIMING(PIO0); | |
110 | ||
111 | /* set configuration for RCS2# */ | |
112 | mem_stcfg |= TS_MASK; | |
113 | mem_stcfg &= ~TCSOE_MASK; | |
114 | mem_stcfg &= ~TOECS_MASK; | |
115 | mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS; | |
116 | break; | |
117 | ||
118 | case 1: | |
119 | mem_sttime = SBC_IDE_TIMING(PIO1); | |
120 | ||
121 | /* set configuration for RCS2# */ | |
122 | mem_stcfg |= TS_MASK; | |
123 | mem_stcfg &= ~TCSOE_MASK; | |
124 | mem_stcfg &= ~TOECS_MASK; | |
125 | mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS; | |
126 | break; | |
127 | ||
128 | case 2: | |
129 | mem_sttime = SBC_IDE_TIMING(PIO2); | |
130 | ||
131 | /* set configuration for RCS2# */ | |
132 | mem_stcfg &= ~TS_MASK; | |
133 | mem_stcfg &= ~TCSOE_MASK; | |
134 | mem_stcfg &= ~TOECS_MASK; | |
135 | mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS; | |
136 | break; | |
137 | ||
138 | case 3: | |
139 | mem_sttime = SBC_IDE_TIMING(PIO3); | |
140 | ||
141 | /* set configuration for RCS2# */ | |
142 | mem_stcfg &= ~TS_MASK; | |
143 | mem_stcfg &= ~TCSOE_MASK; | |
144 | mem_stcfg &= ~TOECS_MASK; | |
145 | mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS; | |
146 | ||
147 | break; | |
148 | ||
149 | case 4: | |
150 | mem_sttime = SBC_IDE_TIMING(PIO4); | |
151 | ||
152 | /* set configuration for RCS2# */ | |
153 | mem_stcfg &= ~TS_MASK; | |
154 | mem_stcfg &= ~TCSOE_MASK; | |
155 | mem_stcfg &= ~TOECS_MASK; | |
156 | mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS; | |
157 | break; | |
158 | } | |
159 | ||
160 | au_writel(mem_sttime,MEM_STTIME2); | |
161 | au_writel(mem_stcfg,MEM_STCFG2); | |
26a940e2 PP |
162 | } |
163 | ||
88b2b32b | 164 | static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed) |
26a940e2 | 165 | { |
88b2b32b | 166 | int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); |
26a940e2 | 167 | |
8f29e650 | 168 | switch(speed) { |
26a940e2 | 169 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
8f29e650 JC |
170 | case XFER_MW_DMA_2: |
171 | mem_sttime = SBC_IDE_TIMING(MDMA2); | |
172 | ||
173 | /* set configuration for RCS2# */ | |
174 | mem_stcfg &= ~TS_MASK; | |
175 | mem_stcfg &= ~TCSOE_MASK; | |
176 | mem_stcfg &= ~TOECS_MASK; | |
177 | mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS; | |
178 | ||
8f29e650 JC |
179 | break; |
180 | case XFER_MW_DMA_1: | |
181 | mem_sttime = SBC_IDE_TIMING(MDMA1); | |
182 | ||
183 | /* set configuration for RCS2# */ | |
184 | mem_stcfg &= ~TS_MASK; | |
185 | mem_stcfg &= ~TCSOE_MASK; | |
186 | mem_stcfg &= ~TOECS_MASK; | |
187 | mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS; | |
188 | ||
8f29e650 JC |
189 | break; |
190 | case XFER_MW_DMA_0: | |
191 | mem_sttime = SBC_IDE_TIMING(MDMA0); | |
192 | ||
193 | /* set configuration for RCS2# */ | |
194 | mem_stcfg |= TS_MASK; | |
195 | mem_stcfg &= ~TCSOE_MASK; | |
196 | mem_stcfg &= ~TOECS_MASK; | |
197 | mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS; | |
198 | ||
8f29e650 | 199 | break; |
26a940e2 | 200 | #endif |
8f29e650 | 201 | default: |
88b2b32b | 202 | return; |
8f29e650 | 203 | } |
a523a175 | 204 | |
8f29e650 JC |
205 | au_writel(mem_sttime,MEM_STTIME2); |
206 | au_writel(mem_stcfg,MEM_STCFG2); | |
26a940e2 PP |
207 | } |
208 | ||
209 | /* | |
210 | * Multi-Word DMA + DbDMA functions | |
211 | */ | |
26a940e2 | 212 | |
8f29e650 | 213 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
26a940e2 PP |
214 | |
215 | static int auide_build_sglist(ide_drive_t *drive, struct request *rq) | |
216 | { | |
8f29e650 JC |
217 | ide_hwif_t *hwif = drive->hwif; |
218 | _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; | |
219 | struct scatterlist *sg = hwif->sg_table; | |
26a940e2 | 220 | |
8f29e650 | 221 | ide_map_sg(drive, rq); |
26a940e2 | 222 | |
8f29e650 JC |
223 | if (rq_data_dir(rq) == READ) |
224 | hwif->sg_dma_direction = DMA_FROM_DEVICE; | |
225 | else | |
226 | hwif->sg_dma_direction = DMA_TO_DEVICE; | |
26a940e2 | 227 | |
8f29e650 JC |
228 | return dma_map_sg(ahwif->dev, sg, hwif->sg_nents, |
229 | hwif->sg_dma_direction); | |
26a940e2 PP |
230 | } |
231 | ||
232 | static int auide_build_dmatable(ide_drive_t *drive) | |
233 | { | |
8f29e650 JC |
234 | int i, iswrite, count = 0; |
235 | ide_hwif_t *hwif = HWIF(drive); | |
236 | ||
237 | struct request *rq = HWGROUP(drive)->rq; | |
238 | ||
239 | _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; | |
240 | struct scatterlist *sg; | |
241 | ||
242 | iswrite = (rq_data_dir(rq) == WRITE); | |
243 | /* Save for interrupt context */ | |
244 | ahwif->drive = drive; | |
245 | ||
246 | /* Build sglist */ | |
247 | hwif->sg_nents = i = auide_build_sglist(drive, rq); | |
248 | ||
249 | if (!i) | |
250 | return 0; | |
251 | ||
252 | /* fill the descriptors */ | |
253 | sg = hwif->sg_table; | |
254 | while (i && sg_dma_len(sg)) { | |
255 | u32 cur_addr; | |
256 | u32 cur_len; | |
257 | ||
258 | cur_addr = sg_dma_address(sg); | |
259 | cur_len = sg_dma_len(sg); | |
260 | ||
261 | while (cur_len) { | |
262 | u32 flags = DDMA_FLAGS_NOIE; | |
263 | unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; | |
264 | ||
265 | if (++count >= PRD_ENTRIES) { | |
266 | printk(KERN_WARNING "%s: DMA table too small\n", | |
267 | drive->name); | |
268 | goto use_pio_instead; | |
269 | } | |
270 | ||
271 | /* Lets enable intr for the last descriptor only */ | |
272 | if (1==i) | |
273 | flags = DDMA_FLAGS_IE; | |
274 | else | |
275 | flags = DDMA_FLAGS_NOIE; | |
276 | ||
277 | if (iswrite) { | |
278 | if(!put_source_flags(ahwif->tx_chan, | |
45711f1a | 279 | (void*) sg_virt(sg), |
8f29e650 JC |
280 | tc, flags)) { |
281 | printk(KERN_ERR "%s failed %d\n", | |
282 | __FUNCTION__, __LINE__); | |
26a940e2 | 283 | } |
8f29e650 | 284 | } else |
26a940e2 | 285 | { |
8f29e650 | 286 | if(!put_dest_flags(ahwif->rx_chan, |
45711f1a | 287 | (void*) sg_virt(sg), |
8f29e650 JC |
288 | tc, flags)) { |
289 | printk(KERN_ERR "%s failed %d\n", | |
290 | __FUNCTION__, __LINE__); | |
26a940e2 | 291 | } |
8f29e650 | 292 | } |
26a940e2 | 293 | |
8f29e650 JC |
294 | cur_addr += tc; |
295 | cur_len -= tc; | |
296 | } | |
55c16a70 | 297 | sg = sg_next(sg); |
8f29e650 JC |
298 | i--; |
299 | } | |
26a940e2 | 300 | |
8f29e650 JC |
301 | if (count) |
302 | return 1; | |
26a940e2 | 303 | |
8f29e650 JC |
304 | use_pio_instead: |
305 | dma_unmap_sg(ahwif->dev, | |
306 | hwif->sg_table, | |
307 | hwif->sg_nents, | |
308 | hwif->sg_dma_direction); | |
26a940e2 | 309 | |
8f29e650 | 310 | return 0; /* revert to PIO for this request */ |
26a940e2 PP |
311 | } |
312 | ||
313 | static int auide_dma_end(ide_drive_t *drive) | |
314 | { | |
8f29e650 JC |
315 | ide_hwif_t *hwif = HWIF(drive); |
316 | _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; | |
26a940e2 | 317 | |
8f29e650 JC |
318 | if (hwif->sg_nents) { |
319 | dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents, | |
320 | hwif->sg_dma_direction); | |
321 | hwif->sg_nents = 0; | |
322 | } | |
26a940e2 | 323 | |
8f29e650 | 324 | return 0; |
26a940e2 PP |
325 | } |
326 | ||
327 | static void auide_dma_start(ide_drive_t *drive ) | |
328 | { | |
26a940e2 PP |
329 | } |
330 | ||
26a940e2 PP |
331 | |
332 | static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command) | |
333 | { | |
8f29e650 JC |
334 | /* issue cmd to drive */ |
335 | ide_execute_command(drive, command, &ide_dma_intr, | |
336 | (2*WAIT_CMD), NULL); | |
26a940e2 PP |
337 | } |
338 | ||
339 | static int auide_dma_setup(ide_drive_t *drive) | |
8f29e650 JC |
340 | { |
341 | struct request *rq = HWGROUP(drive)->rq; | |
26a940e2 | 342 | |
8f29e650 JC |
343 | if (!auide_build_dmatable(drive)) { |
344 | ide_map_sg(drive, rq); | |
345 | return 1; | |
346 | } | |
26a940e2 | 347 | |
8f29e650 JC |
348 | drive->waiting_for_dma = 1; |
349 | return 0; | |
26a940e2 PP |
350 | } |
351 | ||
8446f659 | 352 | static u8 auide_mdma_filter(ide_drive_t *drive) |
26a940e2 | 353 | { |
8446f659 BZ |
354 | /* |
355 | * FIXME: ->white_list and ->black_list are based on completely bogus | |
356 | * ->ide_dma_check implementation which didn't set neither the host | |
357 | * controller timings nor the device for the desired transfer mode. | |
358 | * | |
359 | * They should be either removed or 0x00 MWDMA mask should be | |
360 | * returned for devices on the ->black_list. | |
361 | */ | |
8f29e650 | 362 | |
8446f659 | 363 | if (dbdma_init_done == 0) { |
8f29e650 JC |
364 | auide_hwif.white_list = ide_in_drive_list(drive->id, |
365 | dma_white_list); | |
366 | auide_hwif.black_list = ide_in_drive_list(drive->id, | |
367 | dma_black_list); | |
368 | auide_hwif.drive = drive; | |
369 | auide_ddma_init(&auide_hwif); | |
370 | dbdma_init_done = 1; | |
371 | } | |
26a940e2 | 372 | |
8f29e650 | 373 | /* Is the drive in our DMA black list? */ |
8446f659 | 374 | if (auide_hwif.black_list) |
8f29e650 | 375 | printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n", |
8446f659 | 376 | drive->name, drive->id->model); |
8f29e650 | 377 | |
8446f659 BZ |
378 | return drive->hwif->mwdma_mask; |
379 | } | |
380 | ||
26a940e2 | 381 | static int auide_dma_test_irq(ide_drive_t *drive) |
8f29e650 JC |
382 | { |
383 | if (drive->waiting_for_dma == 0) | |
384 | printk(KERN_WARNING "%s: ide_dma_test_irq \ | |
26a940e2 PP |
385 | called while not waiting\n", drive->name); |
386 | ||
8f29e650 JC |
387 | /* If dbdma didn't execute the STOP command yet, the |
388 | * active bit is still set | |
26a940e2 | 389 | */ |
8f29e650 JC |
390 | drive->waiting_for_dma++; |
391 | if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) { | |
392 | printk(KERN_WARNING "%s: timeout waiting for ddma to \ | |
26a940e2 | 393 | complete\n", drive->name); |
8f29e650 JC |
394 | return 1; |
395 | } | |
396 | udelay(10); | |
397 | return 0; | |
26a940e2 PP |
398 | } |
399 | ||
ccf35289 | 400 | static void auide_dma_host_on(ide_drive_t *drive) |
26a940e2 | 401 | { |
26a940e2 PP |
402 | } |
403 | ||
404 | static int auide_dma_on(ide_drive_t *drive) | |
405 | { | |
8f29e650 | 406 | drive->using_dma = 1; |
ccf35289 BZ |
407 | |
408 | return 0; | |
26a940e2 PP |
409 | } |
410 | ||
7469aaf6 | 411 | static void auide_dma_host_off(ide_drive_t *drive) |
26a940e2 | 412 | { |
26a940e2 PP |
413 | } |
414 | ||
7469aaf6 | 415 | static void auide_dma_off_quietly(ide_drive_t *drive) |
26a940e2 | 416 | { |
8f29e650 | 417 | drive->using_dma = 0; |
26a940e2 PP |
418 | } |
419 | ||
841d2a9b | 420 | static void auide_dma_lost_irq(ide_drive_t *drive) |
26a940e2 | 421 | { |
8f29e650 | 422 | printk(KERN_ERR "%s: IRQ lost\n", drive->name); |
26a940e2 PP |
423 | } |
424 | ||
53e62d3a | 425 | static void auide_ddma_tx_callback(int irq, void *param) |
26a940e2 | 426 | { |
8f29e650 JC |
427 | _auide_hwif *ahwif = (_auide_hwif*)param; |
428 | ahwif->drive->waiting_for_dma = 0; | |
26a940e2 PP |
429 | } |
430 | ||
53e62d3a | 431 | static void auide_ddma_rx_callback(int irq, void *param) |
26a940e2 | 432 | { |
8f29e650 JC |
433 | _auide_hwif *ahwif = (_auide_hwif*)param; |
434 | ahwif->drive->waiting_for_dma = 0; | |
435 | } | |
436 | ||
437 | #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ | |
26a940e2 | 438 | |
8f29e650 JC |
439 | static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags) |
440 | { | |
441 | dev->dev_id = dev_id; | |
442 | dev->dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR; | |
443 | dev->dev_intlevel = 0; | |
444 | dev->dev_intpolarity = 0; | |
445 | dev->dev_tsize = tsize; | |
446 | dev->dev_devwidth = devwidth; | |
447 | dev->dev_flags = flags; | |
26a940e2 | 448 | } |
8f29e650 JC |
449 | |
450 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) | |
26a940e2 | 451 | |
c283f5db | 452 | static void auide_dma_timeout(ide_drive_t *drive) |
26a940e2 | 453 | { |
c283f5db | 454 | ide_hwif_t *hwif = HWIF(drive); |
26a940e2 | 455 | |
8f29e650 | 456 | printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name); |
26a940e2 | 457 | |
c283f5db SS |
458 | if (hwif->ide_dma_test_irq(drive)) |
459 | return; | |
26a940e2 | 460 | |
c283f5db | 461 | hwif->ide_dma_end(drive); |
26a940e2 | 462 | } |
8f29e650 | 463 | |
26a940e2 | 464 | |
8f29e650 JC |
465 | static int auide_ddma_init(_auide_hwif *auide) { |
466 | ||
467 | dbdev_tab_t source_dev_tab, target_dev_tab; | |
468 | u32 dev_id, tsize, devwidth, flags; | |
469 | ide_hwif_t *hwif = auide->hwif; | |
26a940e2 | 470 | |
8f29e650 | 471 | dev_id = AU1XXX_ATA_DDMA_REQ; |
26a940e2 | 472 | |
8f29e650 JC |
473 | if (auide->white_list || auide->black_list) { |
474 | tsize = 8; | |
475 | devwidth = 32; | |
476 | } | |
477 | else { | |
478 | tsize = 1; | |
479 | devwidth = 16; | |
480 | ||
481 | printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model); | |
482 | printk(KERN_ERR " please read 'Documentation/mips/AU1xxx_IDE.README'"); | |
483 | } | |
26a940e2 | 484 | |
8f29e650 JC |
485 | #ifdef IDE_AU1XXX_BURSTMODE |
486 | flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; | |
26a940e2 | 487 | #else |
8f29e650 | 488 | flags = DEV_FLAGS_SYNC; |
26a940e2 PP |
489 | #endif |
490 | ||
8f29e650 JC |
491 | /* setup dev_tab for tx channel */ |
492 | auide_init_dbdma_dev( &source_dev_tab, | |
493 | dev_id, | |
494 | tsize, devwidth, DEV_FLAGS_OUT | flags); | |
495 | auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
496 | ||
497 | auide_init_dbdma_dev( &source_dev_tab, | |
498 | dev_id, | |
499 | tsize, devwidth, DEV_FLAGS_IN | flags); | |
500 | auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
501 | ||
502 | /* We also need to add a target device for the DMA */ | |
503 | auide_init_dbdma_dev( &target_dev_tab, | |
504 | (u32)DSCR_CMD0_ALWAYS, | |
505 | tsize, devwidth, DEV_FLAGS_ANYUSE); | |
506 | auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); | |
507 | ||
508 | /* Get a channel for TX */ | |
509 | auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id, | |
510 | auide->tx_dev_id, | |
511 | auide_ddma_tx_callback, | |
512 | (void*)auide); | |
513 | ||
514 | /* Get a channel for RX */ | |
515 | auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, | |
516 | auide->target_dev_id, | |
517 | auide_ddma_rx_callback, | |
518 | (void*)auide); | |
519 | ||
520 | auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, | |
521 | NUM_DESCRIPTORS); | |
522 | auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, | |
523 | NUM_DESCRIPTORS); | |
524 | ||
525 | hwif->dmatable_cpu = dma_alloc_coherent(auide->dev, | |
526 | PRD_ENTRIES * PRD_BYTES, /* 1 Page */ | |
527 | &hwif->dmatable_dma, GFP_KERNEL); | |
528 | ||
529 | au1xxx_dbdma_start( auide->tx_chan ); | |
530 | au1xxx_dbdma_start( auide->rx_chan ); | |
531 | ||
532 | return 0; | |
533 | } | |
26a940e2 | 534 | #else |
8f29e650 JC |
535 | |
536 | static int auide_ddma_init( _auide_hwif *auide ) | |
537 | { | |
538 | dbdev_tab_t source_dev_tab; | |
539 | int flags; | |
26a940e2 | 540 | |
8f29e650 JC |
541 | #ifdef IDE_AU1XXX_BURSTMODE |
542 | flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; | |
543 | #else | |
544 | flags = DEV_FLAGS_SYNC; | |
26a940e2 | 545 | #endif |
26a940e2 | 546 | |
8f29e650 JC |
547 | /* setup dev_tab for tx channel */ |
548 | auide_init_dbdma_dev( &source_dev_tab, | |
549 | (u32)DSCR_CMD0_ALWAYS, | |
550 | 8, 32, DEV_FLAGS_OUT | flags); | |
551 | auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
552 | ||
553 | auide_init_dbdma_dev( &source_dev_tab, | |
554 | (u32)DSCR_CMD0_ALWAYS, | |
555 | 8, 32, DEV_FLAGS_IN | flags); | |
556 | auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
557 | ||
558 | /* Get a channel for TX */ | |
559 | auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS, | |
560 | auide->tx_dev_id, | |
561 | NULL, | |
562 | (void*)auide); | |
563 | ||
564 | /* Get a channel for RX */ | |
565 | auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, | |
566 | DSCR_CMD0_ALWAYS, | |
567 | NULL, | |
568 | (void*)auide); | |
569 | ||
570 | auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, | |
571 | NUM_DESCRIPTORS); | |
572 | auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, | |
573 | NUM_DESCRIPTORS); | |
574 | ||
575 | au1xxx_dbdma_start( auide->tx_chan ); | |
576 | au1xxx_dbdma_start( auide->rx_chan ); | |
577 | ||
578 | return 0; | |
26a940e2 | 579 | } |
8f29e650 | 580 | #endif |
26a940e2 PP |
581 | |
582 | static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif) | |
583 | { | |
8f29e650 JC |
584 | int i; |
585 | unsigned long *ata_regs = hw->io_ports; | |
586 | ||
587 | /* FIXME? */ | |
588 | for (i = 0; i < IDE_CONTROL_OFFSET; i++) { | |
589 | *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET); | |
590 | } | |
591 | ||
592 | /* set the Alternative Status register */ | |
593 | *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET); | |
26a940e2 PP |
594 | } |
595 | ||
596 | static int au_ide_probe(struct device *dev) | |
597 | { | |
598 | struct platform_device *pdev = to_platform_device(dev); | |
8f29e650 JC |
599 | _auide_hwif *ahwif = &auide_hwif; |
600 | ide_hwif_t *hwif; | |
26a940e2 PP |
601 | struct resource *res; |
602 | int ret = 0; | |
8447d9d5 | 603 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
9239b333 | 604 | hw_regs_t hw; |
26a940e2 PP |
605 | |
606 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) | |
8f29e650 | 607 | char *mode = "MWDMA2"; |
26a940e2 | 608 | #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) |
8f29e650 | 609 | char *mode = "PIO+DDMA(offload)"; |
26a940e2 PP |
610 | #endif |
611 | ||
8f29e650 JC |
612 | memset(&auide_hwif, 0, sizeof(_auide_hwif)); |
613 | auide_hwif.dev = 0; | |
26a940e2 PP |
614 | |
615 | ahwif->dev = dev; | |
616 | ahwif->irq = platform_get_irq(pdev, 0); | |
617 | ||
618 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
619 | ||
620 | if (res == NULL) { | |
621 | pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id); | |
622 | ret = -ENODEV; | |
48944738 DV |
623 | goto out; |
624 | } | |
625 | if (ahwif->irq < 0) { | |
626 | pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id); | |
627 | ret = -ENODEV; | |
26a940e2 PP |
628 | goto out; |
629 | } | |
630 | ||
8f29e650 | 631 | if (!request_mem_region (res->start, res->end-res->start, pdev->name)) { |
26a940e2 | 632 | pr_debug("%s: request_mem_region failed\n", DRV_NAME); |
8f29e650 | 633 | ret = -EBUSY; |
26a940e2 | 634 | goto out; |
8f29e650 | 635 | } |
26a940e2 PP |
636 | |
637 | ahwif->regbase = (u32)ioremap(res->start, res->end-res->start); | |
638 | if (ahwif->regbase == 0) { | |
639 | ret = -ENOMEM; | |
640 | goto out; | |
641 | } | |
642 | ||
8f29e650 JC |
643 | /* FIXME: This might possibly break PCMCIA IDE devices */ |
644 | ||
645 | hwif = &ide_hwifs[pdev->id]; | |
9239b333 | 646 | hwif->irq = ahwif->irq; |
8f29e650 | 647 | hwif->chipset = ide_au1xxx; |
26a940e2 | 648 | |
9239b333 BZ |
649 | memset(&hw, 0, sizeof(hw)); |
650 | auide_setup_ports(&hw, ahwif); | |
651 | memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports)); | |
26a940e2 | 652 | |
8f29e650 | 653 | hwif->ultra_mask = 0x0; /* Disable Ultra DMA */ |
26a940e2 | 654 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
8f29e650 JC |
655 | hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */ |
656 | hwif->swdma_mask = 0x00; | |
26a940e2 | 657 | #else |
8f29e650 JC |
658 | hwif->mwdma_mask = 0x0; |
659 | hwif->swdma_mask = 0x0; | |
660 | #endif | |
661 | ||
4099d143 | 662 | hwif->pio_mask = ATA_PIO4; |
88b2b32b | 663 | hwif->host_flags = IDE_HFLAG_POST_SET_MODE; |
4099d143 | 664 | |
8f29e650 JC |
665 | hwif->noprobe = 0; |
666 | hwif->drives[0].unmask = 1; | |
667 | hwif->drives[1].unmask = 1; | |
668 | ||
669 | /* hold should be on in all cases */ | |
670 | hwif->hold = 1; | |
2ad1e558 BZ |
671 | |
672 | hwif->mmio = 1; | |
8f29e650 JC |
673 | |
674 | /* If the user has selected DDMA assisted copies, | |
675 | then set up a few local I/O function entry points | |
676 | */ | |
677 | ||
678 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA | |
679 | hwif->INSW = auide_insw; | |
680 | hwif->OUTSW = auide_outsw; | |
26a940e2 | 681 | #endif |
8f29e650 | 682 | |
26bcb879 | 683 | hwif->set_pio_mode = &au1xxx_set_pio_mode; |
88b2b32b | 684 | hwif->set_dma_mode = &auide_set_dma_mode; |
26a940e2 PP |
685 | |
686 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA | |
7469aaf6 | 687 | hwif->dma_off_quietly = &auide_dma_off_quietly; |
c283f5db | 688 | hwif->dma_timeout = &auide_dma_timeout; |
8f29e650 | 689 | |
8446f659 BZ |
690 | hwif->mdma_filter = &auide_mdma_filter; |
691 | ||
8f29e650 JC |
692 | hwif->dma_exec_cmd = &auide_dma_exec_cmd; |
693 | hwif->dma_start = &auide_dma_start; | |
694 | hwif->ide_dma_end = &auide_dma_end; | |
695 | hwif->dma_setup = &auide_dma_setup; | |
696 | hwif->ide_dma_test_irq = &auide_dma_test_irq; | |
7469aaf6 | 697 | hwif->dma_host_off = &auide_dma_host_off; |
ccf35289 | 698 | hwif->dma_host_on = &auide_dma_host_on; |
841d2a9b | 699 | hwif->dma_lost_irq = &auide_dma_lost_irq; |
8f29e650 | 700 | hwif->ide_dma_on = &auide_dma_on; |
26a940e2 | 701 | #else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ |
8f29e650 JC |
702 | hwif->channel = 0; |
703 | hwif->hold = 1; | |
704 | hwif->select_data = 0; /* no chipset-specific code */ | |
705 | hwif->config_data = 0; /* no chipset-specific code */ | |
706 | ||
8f29e650 | 707 | hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */ |
a05e2faa | 708 | hwif->drives[1].autotune = 1; |
26a940e2 | 709 | #endif |
a05e2faa BZ |
710 | hwif->drives[0].no_io_32bit = 1; |
711 | hwif->drives[1].no_io_32bit = 1; | |
26a940e2 | 712 | |
8f29e650 JC |
713 | auide_hwif.hwif = hwif; |
714 | hwif->hwif_data = &auide_hwif; | |
26a940e2 | 715 | |
8f29e650 JC |
716 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA |
717 | auide_ddma_init(&auide_hwif); | |
718 | dbdma_init_done = 1; | |
26a940e2 PP |
719 | #endif |
720 | ||
8447d9d5 | 721 | idx[0] = hwif->index; |
5cbf79cd | 722 | |
8447d9d5 | 723 | ide_device_add(idx); |
5cbf79cd | 724 | |
26a940e2 PP |
725 | dev_set_drvdata(dev, hwif); |
726 | ||
8f29e650 | 727 | printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode ); |
26a940e2 | 728 | |
8f29e650 JC |
729 | out: |
730 | return ret; | |
26a940e2 PP |
731 | } |
732 | ||
733 | static int au_ide_remove(struct device *dev) | |
734 | { | |
735 | struct platform_device *pdev = to_platform_device(dev); | |
736 | struct resource *res; | |
737 | ide_hwif_t *hwif = dev_get_drvdata(dev); | |
8f29e650 | 738 | _auide_hwif *ahwif = &auide_hwif; |
26a940e2 PP |
739 | |
740 | ide_unregister(hwif - ide_hwifs); | |
741 | ||
742 | iounmap((void *)ahwif->regbase); | |
743 | ||
744 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
745 | release_mem_region(res->start, res->end - res->start); | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
750 | static struct device_driver au1200_ide_driver = { | |
751 | .name = "au1200-ide", | |
752 | .bus = &platform_bus_type, | |
753 | .probe = au_ide_probe, | |
754 | .remove = au_ide_remove, | |
755 | }; | |
756 | ||
757 | static int __init au_ide_init(void) | |
758 | { | |
759 | return driver_register(&au1200_ide_driver); | |
760 | } | |
761 | ||
8f29e650 | 762 | static void __exit au_ide_exit(void) |
26a940e2 PP |
763 | { |
764 | driver_unregister(&au1200_ide_driver); | |
765 | } | |
766 | ||
26a940e2 PP |
767 | MODULE_LICENSE("GPL"); |
768 | MODULE_DESCRIPTION("AU1200 IDE driver"); | |
769 | ||
770 | module_init(au_ide_init); | |
771 | module_exit(au_ide_exit); |