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26a940e2 PP |
1 | /* |
2 | * linux/drivers/ide/mips/au1xxx-ide.c version 01.30.00 Aug. 02 2005 | |
3 | * | |
4 | * BRIEF MODULE DESCRIPTION | |
5 | * AMD Alchemy Au1xxx IDE interface routines over the Static Bus | |
6 | * | |
7 | * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it under | |
10 | * the terms of the GNU General Public License as published by the Free Software | |
11 | * Foundation; either version 2 of the License, or (at your option) any later | |
12 | * version. | |
13 | * | |
14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, | |
15 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND | |
16 | * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR | |
17 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
18 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
19 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
20 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
21 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
22 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
23 | * POSSIBILITY OF SUCH DAMAGE. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License along with | |
26 | * this program; if not, write to the Free Software Foundation, Inc., | |
27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
28 | * | |
29 | * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE | |
30 | * Interface and Linux Device Driver" Application Note. | |
31 | */ | |
26a940e2 PP |
32 | #include <linux/types.h> |
33 | #include <linux/module.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/delay.h> | |
8f29e650 JC |
36 | #include <linux/platform_device.h> |
37 | ||
26a940e2 PP |
38 | #include <linux/init.h> |
39 | #include <linux/ide.h> | |
40 | #include <linux/sysdev.h> | |
41 | ||
42 | #include <linux/dma-mapping.h> | |
43 | ||
8f29e650 JC |
44 | #include "ide-timing.h" |
45 | ||
26a940e2 PP |
46 | #include <asm/io.h> |
47 | #include <asm/mach-au1x00/au1xxx.h> | |
48 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
49 | ||
26a940e2 PP |
50 | #include <asm/mach-au1x00/au1xxx_ide.h> |
51 | ||
52 | #define DRV_NAME "au1200-ide" | |
53 | #define DRV_VERSION "1.0" | |
8f29e650 | 54 | #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>" |
26a940e2 | 55 | |
8f29e650 JC |
56 | /* enable the burstmode in the dbdma */ |
57 | #define IDE_AU1XXX_BURSTMODE 1 | |
26a940e2 | 58 | |
8f29e650 JC |
59 | static _auide_hwif auide_hwif; |
60 | static int dbdma_init_done; | |
26a940e2 | 61 | |
26a940e2 PP |
62 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) |
63 | ||
8f29e650 | 64 | void auide_insw(unsigned long port, void *addr, u32 count) |
26a940e2 | 65 | { |
8f29e650 JC |
66 | _auide_hwif *ahwif = &auide_hwif; |
67 | chan_tab_t *ctp; | |
68 | au1x_ddma_desc_t *dp; | |
26a940e2 | 69 | |
8f29e650 JC |
70 | if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, |
71 | DDMA_FLAGS_NOIE)) { | |
72 | printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__); | |
73 | return; | |
74 | } | |
75 | ctp = *((chan_tab_t **)ahwif->rx_chan); | |
76 | dp = ctp->cur_ptr; | |
77 | while (dp->dscr_cmd0 & DSCR_CMD0_V) | |
78 | ; | |
79 | ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); | |
26a940e2 PP |
80 | } |
81 | ||
8f29e650 | 82 | void auide_outsw(unsigned long port, void *addr, u32 count) |
26a940e2 | 83 | { |
8f29e650 JC |
84 | _auide_hwif *ahwif = &auide_hwif; |
85 | chan_tab_t *ctp; | |
86 | au1x_ddma_desc_t *dp; | |
26a940e2 | 87 | |
8f29e650 JC |
88 | if(!put_source_flags(ahwif->tx_chan, (void*)addr, |
89 | count << 1, DDMA_FLAGS_NOIE)) { | |
90 | printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__); | |
91 | return; | |
92 | } | |
93 | ctp = *((chan_tab_t **)ahwif->tx_chan); | |
94 | dp = ctp->cur_ptr; | |
95 | while (dp->dscr_cmd0 & DSCR_CMD0_V) | |
96 | ; | |
97 | ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); | |
26a940e2 PP |
98 | } |
99 | ||
26a940e2 | 100 | #endif |
26a940e2 | 101 | |
26bcb879 | 102 | static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio) |
26a940e2 | 103 | { |
88b2b32b | 104 | int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); |
8f29e650 JC |
105 | |
106 | /* set pio mode! */ | |
107 | switch(pio) { | |
108 | case 0: | |
109 | mem_sttime = SBC_IDE_TIMING(PIO0); | |
110 | ||
111 | /* set configuration for RCS2# */ | |
112 | mem_stcfg |= TS_MASK; | |
113 | mem_stcfg &= ~TCSOE_MASK; | |
114 | mem_stcfg &= ~TOECS_MASK; | |
115 | mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS; | |
116 | break; | |
117 | ||
118 | case 1: | |
119 | mem_sttime = SBC_IDE_TIMING(PIO1); | |
120 | ||
121 | /* set configuration for RCS2# */ | |
122 | mem_stcfg |= TS_MASK; | |
123 | mem_stcfg &= ~TCSOE_MASK; | |
124 | mem_stcfg &= ~TOECS_MASK; | |
125 | mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS; | |
126 | break; | |
127 | ||
128 | case 2: | |
129 | mem_sttime = SBC_IDE_TIMING(PIO2); | |
130 | ||
131 | /* set configuration for RCS2# */ | |
132 | mem_stcfg &= ~TS_MASK; | |
133 | mem_stcfg &= ~TCSOE_MASK; | |
134 | mem_stcfg &= ~TOECS_MASK; | |
135 | mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS; | |
136 | break; | |
137 | ||
138 | case 3: | |
139 | mem_sttime = SBC_IDE_TIMING(PIO3); | |
140 | ||
141 | /* set configuration for RCS2# */ | |
142 | mem_stcfg &= ~TS_MASK; | |
143 | mem_stcfg &= ~TCSOE_MASK; | |
144 | mem_stcfg &= ~TOECS_MASK; | |
145 | mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS; | |
146 | ||
147 | break; | |
148 | ||
149 | case 4: | |
150 | mem_sttime = SBC_IDE_TIMING(PIO4); | |
151 | ||
152 | /* set configuration for RCS2# */ | |
153 | mem_stcfg &= ~TS_MASK; | |
154 | mem_stcfg &= ~TCSOE_MASK; | |
155 | mem_stcfg &= ~TOECS_MASK; | |
156 | mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS; | |
157 | break; | |
158 | } | |
159 | ||
160 | au_writel(mem_sttime,MEM_STTIME2); | |
161 | au_writel(mem_stcfg,MEM_STCFG2); | |
26a940e2 PP |
162 | } |
163 | ||
88b2b32b | 164 | static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed) |
26a940e2 | 165 | { |
88b2b32b | 166 | int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2); |
26a940e2 | 167 | |
8f29e650 | 168 | switch(speed) { |
26a940e2 | 169 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
8f29e650 JC |
170 | case XFER_MW_DMA_2: |
171 | mem_sttime = SBC_IDE_TIMING(MDMA2); | |
172 | ||
173 | /* set configuration for RCS2# */ | |
174 | mem_stcfg &= ~TS_MASK; | |
175 | mem_stcfg &= ~TCSOE_MASK; | |
176 | mem_stcfg &= ~TOECS_MASK; | |
177 | mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS; | |
178 | ||
8f29e650 JC |
179 | break; |
180 | case XFER_MW_DMA_1: | |
181 | mem_sttime = SBC_IDE_TIMING(MDMA1); | |
182 | ||
183 | /* set configuration for RCS2# */ | |
184 | mem_stcfg &= ~TS_MASK; | |
185 | mem_stcfg &= ~TCSOE_MASK; | |
186 | mem_stcfg &= ~TOECS_MASK; | |
187 | mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS; | |
188 | ||
8f29e650 JC |
189 | break; |
190 | case XFER_MW_DMA_0: | |
191 | mem_sttime = SBC_IDE_TIMING(MDMA0); | |
192 | ||
193 | /* set configuration for RCS2# */ | |
194 | mem_stcfg |= TS_MASK; | |
195 | mem_stcfg &= ~TCSOE_MASK; | |
196 | mem_stcfg &= ~TOECS_MASK; | |
197 | mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS; | |
198 | ||
8f29e650 | 199 | break; |
26a940e2 | 200 | #endif |
8f29e650 | 201 | default: |
88b2b32b | 202 | return; |
8f29e650 | 203 | } |
a523a175 | 204 | |
8f29e650 JC |
205 | au_writel(mem_sttime,MEM_STTIME2); |
206 | au_writel(mem_stcfg,MEM_STCFG2); | |
26a940e2 PP |
207 | } |
208 | ||
209 | /* | |
210 | * Multi-Word DMA + DbDMA functions | |
211 | */ | |
26a940e2 | 212 | |
8f29e650 | 213 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
26a940e2 PP |
214 | |
215 | static int auide_build_sglist(ide_drive_t *drive, struct request *rq) | |
216 | { | |
8f29e650 JC |
217 | ide_hwif_t *hwif = drive->hwif; |
218 | _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; | |
219 | struct scatterlist *sg = hwif->sg_table; | |
26a940e2 | 220 | |
8f29e650 | 221 | ide_map_sg(drive, rq); |
26a940e2 | 222 | |
8f29e650 JC |
223 | if (rq_data_dir(rq) == READ) |
224 | hwif->sg_dma_direction = DMA_FROM_DEVICE; | |
225 | else | |
226 | hwif->sg_dma_direction = DMA_TO_DEVICE; | |
26a940e2 | 227 | |
8f29e650 JC |
228 | return dma_map_sg(ahwif->dev, sg, hwif->sg_nents, |
229 | hwif->sg_dma_direction); | |
26a940e2 PP |
230 | } |
231 | ||
232 | static int auide_build_dmatable(ide_drive_t *drive) | |
233 | { | |
8f29e650 JC |
234 | int i, iswrite, count = 0; |
235 | ide_hwif_t *hwif = HWIF(drive); | |
236 | ||
237 | struct request *rq = HWGROUP(drive)->rq; | |
238 | ||
239 | _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; | |
240 | struct scatterlist *sg; | |
241 | ||
242 | iswrite = (rq_data_dir(rq) == WRITE); | |
243 | /* Save for interrupt context */ | |
244 | ahwif->drive = drive; | |
245 | ||
246 | /* Build sglist */ | |
247 | hwif->sg_nents = i = auide_build_sglist(drive, rq); | |
248 | ||
249 | if (!i) | |
250 | return 0; | |
251 | ||
252 | /* fill the descriptors */ | |
253 | sg = hwif->sg_table; | |
254 | while (i && sg_dma_len(sg)) { | |
255 | u32 cur_addr; | |
256 | u32 cur_len; | |
257 | ||
258 | cur_addr = sg_dma_address(sg); | |
259 | cur_len = sg_dma_len(sg); | |
260 | ||
261 | while (cur_len) { | |
262 | u32 flags = DDMA_FLAGS_NOIE; | |
263 | unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00; | |
264 | ||
265 | if (++count >= PRD_ENTRIES) { | |
266 | printk(KERN_WARNING "%s: DMA table too small\n", | |
267 | drive->name); | |
268 | goto use_pio_instead; | |
269 | } | |
270 | ||
271 | /* Lets enable intr for the last descriptor only */ | |
272 | if (1==i) | |
273 | flags = DDMA_FLAGS_IE; | |
274 | else | |
275 | flags = DDMA_FLAGS_NOIE; | |
276 | ||
277 | if (iswrite) { | |
278 | if(!put_source_flags(ahwif->tx_chan, | |
279 | (void*)(page_address(sg->page) | |
280 | + sg->offset), | |
281 | tc, flags)) { | |
282 | printk(KERN_ERR "%s failed %d\n", | |
283 | __FUNCTION__, __LINE__); | |
26a940e2 | 284 | } |
8f29e650 | 285 | } else |
26a940e2 | 286 | { |
8f29e650 JC |
287 | if(!put_dest_flags(ahwif->rx_chan, |
288 | (void*)(page_address(sg->page) | |
289 | + sg->offset), | |
290 | tc, flags)) { | |
291 | printk(KERN_ERR "%s failed %d\n", | |
292 | __FUNCTION__, __LINE__); | |
26a940e2 | 293 | } |
8f29e650 | 294 | } |
26a940e2 | 295 | |
8f29e650 JC |
296 | cur_addr += tc; |
297 | cur_len -= tc; | |
298 | } | |
299 | sg++; | |
300 | i--; | |
301 | } | |
26a940e2 | 302 | |
8f29e650 JC |
303 | if (count) |
304 | return 1; | |
26a940e2 | 305 | |
8f29e650 JC |
306 | use_pio_instead: |
307 | dma_unmap_sg(ahwif->dev, | |
308 | hwif->sg_table, | |
309 | hwif->sg_nents, | |
310 | hwif->sg_dma_direction); | |
26a940e2 | 311 | |
8f29e650 | 312 | return 0; /* revert to PIO for this request */ |
26a940e2 PP |
313 | } |
314 | ||
315 | static int auide_dma_end(ide_drive_t *drive) | |
316 | { | |
8f29e650 JC |
317 | ide_hwif_t *hwif = HWIF(drive); |
318 | _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data; | |
26a940e2 | 319 | |
8f29e650 JC |
320 | if (hwif->sg_nents) { |
321 | dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents, | |
322 | hwif->sg_dma_direction); | |
323 | hwif->sg_nents = 0; | |
324 | } | |
26a940e2 | 325 | |
8f29e650 | 326 | return 0; |
26a940e2 PP |
327 | } |
328 | ||
329 | static void auide_dma_start(ide_drive_t *drive ) | |
330 | { | |
26a940e2 PP |
331 | } |
332 | ||
26a940e2 PP |
333 | |
334 | static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command) | |
335 | { | |
8f29e650 JC |
336 | /* issue cmd to drive */ |
337 | ide_execute_command(drive, command, &ide_dma_intr, | |
338 | (2*WAIT_CMD), NULL); | |
26a940e2 PP |
339 | } |
340 | ||
341 | static int auide_dma_setup(ide_drive_t *drive) | |
8f29e650 JC |
342 | { |
343 | struct request *rq = HWGROUP(drive)->rq; | |
26a940e2 | 344 | |
8f29e650 JC |
345 | if (!auide_build_dmatable(drive)) { |
346 | ide_map_sg(drive, rq); | |
347 | return 1; | |
348 | } | |
26a940e2 | 349 | |
8f29e650 JC |
350 | drive->waiting_for_dma = 1; |
351 | return 0; | |
26a940e2 PP |
352 | } |
353 | ||
354 | static int auide_dma_check(ide_drive_t *drive) | |
355 | { | |
75b1d975 | 356 | u8 speed = ide_max_dma_mode(drive); |
8f29e650 JC |
357 | |
358 | if( dbdma_init_done == 0 ){ | |
359 | auide_hwif.white_list = ide_in_drive_list(drive->id, | |
360 | dma_white_list); | |
361 | auide_hwif.black_list = ide_in_drive_list(drive->id, | |
362 | dma_black_list); | |
363 | auide_hwif.drive = drive; | |
364 | auide_ddma_init(&auide_hwif); | |
365 | dbdma_init_done = 1; | |
366 | } | |
26a940e2 | 367 | |
8f29e650 JC |
368 | /* Is the drive in our DMA black list? */ |
369 | ||
370 | if ( auide_hwif.black_list ) { | |
371 | drive->using_dma = 0; | |
372 | ||
373 | /* Borrowed the warning message from ide-dma.c */ | |
26a940e2 | 374 | |
8f29e650 JC |
375 | printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n", |
376 | drive->name, drive->id->model); | |
377 | } | |
378 | else | |
379 | drive->using_dma = 1; | |
380 | ||
8f29e650 | 381 | if (drive->autodma && (speed & XFER_MODE) != XFER_PIO) |
3608b5d7 | 382 | return 0; |
8f29e650 | 383 | |
3608b5d7 | 384 | return -1; |
26a940e2 PP |
385 | } |
386 | ||
387 | static int auide_dma_test_irq(ide_drive_t *drive) | |
8f29e650 JC |
388 | { |
389 | if (drive->waiting_for_dma == 0) | |
390 | printk(KERN_WARNING "%s: ide_dma_test_irq \ | |
26a940e2 PP |
391 | called while not waiting\n", drive->name); |
392 | ||
8f29e650 JC |
393 | /* If dbdma didn't execute the STOP command yet, the |
394 | * active bit is still set | |
26a940e2 | 395 | */ |
8f29e650 JC |
396 | drive->waiting_for_dma++; |
397 | if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) { | |
398 | printk(KERN_WARNING "%s: timeout waiting for ddma to \ | |
26a940e2 | 399 | complete\n", drive->name); |
8f29e650 JC |
400 | return 1; |
401 | } | |
402 | udelay(10); | |
403 | return 0; | |
26a940e2 PP |
404 | } |
405 | ||
ccf35289 | 406 | static void auide_dma_host_on(ide_drive_t *drive) |
26a940e2 | 407 | { |
26a940e2 PP |
408 | } |
409 | ||
410 | static int auide_dma_on(ide_drive_t *drive) | |
411 | { | |
8f29e650 | 412 | drive->using_dma = 1; |
ccf35289 BZ |
413 | |
414 | return 0; | |
26a940e2 PP |
415 | } |
416 | ||
7469aaf6 | 417 | static void auide_dma_host_off(ide_drive_t *drive) |
26a940e2 | 418 | { |
26a940e2 PP |
419 | } |
420 | ||
7469aaf6 | 421 | static void auide_dma_off_quietly(ide_drive_t *drive) |
26a940e2 | 422 | { |
8f29e650 | 423 | drive->using_dma = 0; |
26a940e2 PP |
424 | } |
425 | ||
841d2a9b | 426 | static void auide_dma_lost_irq(ide_drive_t *drive) |
26a940e2 | 427 | { |
8f29e650 | 428 | printk(KERN_ERR "%s: IRQ lost\n", drive->name); |
26a940e2 PP |
429 | } |
430 | ||
53e62d3a | 431 | static void auide_ddma_tx_callback(int irq, void *param) |
26a940e2 | 432 | { |
8f29e650 JC |
433 | _auide_hwif *ahwif = (_auide_hwif*)param; |
434 | ahwif->drive->waiting_for_dma = 0; | |
26a940e2 PP |
435 | } |
436 | ||
53e62d3a | 437 | static void auide_ddma_rx_callback(int irq, void *param) |
26a940e2 | 438 | { |
8f29e650 JC |
439 | _auide_hwif *ahwif = (_auide_hwif*)param; |
440 | ahwif->drive->waiting_for_dma = 0; | |
441 | } | |
442 | ||
443 | #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ | |
26a940e2 | 444 | |
8f29e650 JC |
445 | static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags) |
446 | { | |
447 | dev->dev_id = dev_id; | |
448 | dev->dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR; | |
449 | dev->dev_intlevel = 0; | |
450 | dev->dev_intpolarity = 0; | |
451 | dev->dev_tsize = tsize; | |
452 | dev->dev_devwidth = devwidth; | |
453 | dev->dev_flags = flags; | |
26a940e2 | 454 | } |
8f29e650 JC |
455 | |
456 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) | |
26a940e2 | 457 | |
c283f5db | 458 | static void auide_dma_timeout(ide_drive_t *drive) |
26a940e2 | 459 | { |
c283f5db | 460 | ide_hwif_t *hwif = HWIF(drive); |
26a940e2 | 461 | |
8f29e650 | 462 | printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name); |
26a940e2 | 463 | |
c283f5db SS |
464 | if (hwif->ide_dma_test_irq(drive)) |
465 | return; | |
26a940e2 | 466 | |
c283f5db | 467 | hwif->ide_dma_end(drive); |
26a940e2 | 468 | } |
8f29e650 | 469 | |
26a940e2 | 470 | |
8f29e650 JC |
471 | static int auide_ddma_init(_auide_hwif *auide) { |
472 | ||
473 | dbdev_tab_t source_dev_tab, target_dev_tab; | |
474 | u32 dev_id, tsize, devwidth, flags; | |
475 | ide_hwif_t *hwif = auide->hwif; | |
26a940e2 | 476 | |
8f29e650 | 477 | dev_id = AU1XXX_ATA_DDMA_REQ; |
26a940e2 | 478 | |
8f29e650 JC |
479 | if (auide->white_list || auide->black_list) { |
480 | tsize = 8; | |
481 | devwidth = 32; | |
482 | } | |
483 | else { | |
484 | tsize = 1; | |
485 | devwidth = 16; | |
486 | ||
487 | printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model); | |
488 | printk(KERN_ERR " please read 'Documentation/mips/AU1xxx_IDE.README'"); | |
489 | } | |
26a940e2 | 490 | |
8f29e650 JC |
491 | #ifdef IDE_AU1XXX_BURSTMODE |
492 | flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; | |
26a940e2 | 493 | #else |
8f29e650 | 494 | flags = DEV_FLAGS_SYNC; |
26a940e2 PP |
495 | #endif |
496 | ||
8f29e650 JC |
497 | /* setup dev_tab for tx channel */ |
498 | auide_init_dbdma_dev( &source_dev_tab, | |
499 | dev_id, | |
500 | tsize, devwidth, DEV_FLAGS_OUT | flags); | |
501 | auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
502 | ||
503 | auide_init_dbdma_dev( &source_dev_tab, | |
504 | dev_id, | |
505 | tsize, devwidth, DEV_FLAGS_IN | flags); | |
506 | auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
507 | ||
508 | /* We also need to add a target device for the DMA */ | |
509 | auide_init_dbdma_dev( &target_dev_tab, | |
510 | (u32)DSCR_CMD0_ALWAYS, | |
511 | tsize, devwidth, DEV_FLAGS_ANYUSE); | |
512 | auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); | |
513 | ||
514 | /* Get a channel for TX */ | |
515 | auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id, | |
516 | auide->tx_dev_id, | |
517 | auide_ddma_tx_callback, | |
518 | (void*)auide); | |
519 | ||
520 | /* Get a channel for RX */ | |
521 | auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, | |
522 | auide->target_dev_id, | |
523 | auide_ddma_rx_callback, | |
524 | (void*)auide); | |
525 | ||
526 | auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, | |
527 | NUM_DESCRIPTORS); | |
528 | auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, | |
529 | NUM_DESCRIPTORS); | |
530 | ||
531 | hwif->dmatable_cpu = dma_alloc_coherent(auide->dev, | |
532 | PRD_ENTRIES * PRD_BYTES, /* 1 Page */ | |
533 | &hwif->dmatable_dma, GFP_KERNEL); | |
534 | ||
535 | au1xxx_dbdma_start( auide->tx_chan ); | |
536 | au1xxx_dbdma_start( auide->rx_chan ); | |
537 | ||
538 | return 0; | |
539 | } | |
26a940e2 | 540 | #else |
8f29e650 JC |
541 | |
542 | static int auide_ddma_init( _auide_hwif *auide ) | |
543 | { | |
544 | dbdev_tab_t source_dev_tab; | |
545 | int flags; | |
26a940e2 | 546 | |
8f29e650 JC |
547 | #ifdef IDE_AU1XXX_BURSTMODE |
548 | flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; | |
549 | #else | |
550 | flags = DEV_FLAGS_SYNC; | |
26a940e2 | 551 | #endif |
26a940e2 | 552 | |
8f29e650 JC |
553 | /* setup dev_tab for tx channel */ |
554 | auide_init_dbdma_dev( &source_dev_tab, | |
555 | (u32)DSCR_CMD0_ALWAYS, | |
556 | 8, 32, DEV_FLAGS_OUT | flags); | |
557 | auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
558 | ||
559 | auide_init_dbdma_dev( &source_dev_tab, | |
560 | (u32)DSCR_CMD0_ALWAYS, | |
561 | 8, 32, DEV_FLAGS_IN | flags); | |
562 | auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); | |
563 | ||
564 | /* Get a channel for TX */ | |
565 | auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS, | |
566 | auide->tx_dev_id, | |
567 | NULL, | |
568 | (void*)auide); | |
569 | ||
570 | /* Get a channel for RX */ | |
571 | auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, | |
572 | DSCR_CMD0_ALWAYS, | |
573 | NULL, | |
574 | (void*)auide); | |
575 | ||
576 | auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, | |
577 | NUM_DESCRIPTORS); | |
578 | auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, | |
579 | NUM_DESCRIPTORS); | |
580 | ||
581 | au1xxx_dbdma_start( auide->tx_chan ); | |
582 | au1xxx_dbdma_start( auide->rx_chan ); | |
583 | ||
584 | return 0; | |
26a940e2 | 585 | } |
8f29e650 | 586 | #endif |
26a940e2 PP |
587 | |
588 | static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif) | |
589 | { | |
8f29e650 JC |
590 | int i; |
591 | unsigned long *ata_regs = hw->io_ports; | |
592 | ||
593 | /* FIXME? */ | |
594 | for (i = 0; i < IDE_CONTROL_OFFSET; i++) { | |
595 | *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET); | |
596 | } | |
597 | ||
598 | /* set the Alternative Status register */ | |
599 | *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET); | |
26a940e2 PP |
600 | } |
601 | ||
602 | static int au_ide_probe(struct device *dev) | |
603 | { | |
604 | struct platform_device *pdev = to_platform_device(dev); | |
8f29e650 JC |
605 | _auide_hwif *ahwif = &auide_hwif; |
606 | ide_hwif_t *hwif; | |
26a940e2 | 607 | struct resource *res; |
1918fd63 | 608 | hw_regs_t *hw; |
26a940e2 PP |
609 | int ret = 0; |
610 | ||
611 | #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA) | |
8f29e650 | 612 | char *mode = "MWDMA2"; |
26a940e2 | 613 | #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) |
8f29e650 | 614 | char *mode = "PIO+DDMA(offload)"; |
26a940e2 PP |
615 | #endif |
616 | ||
8f29e650 JC |
617 | memset(&auide_hwif, 0, sizeof(_auide_hwif)); |
618 | auide_hwif.dev = 0; | |
26a940e2 PP |
619 | |
620 | ahwif->dev = dev; | |
621 | ahwif->irq = platform_get_irq(pdev, 0); | |
622 | ||
623 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
624 | ||
625 | if (res == NULL) { | |
626 | pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id); | |
627 | ret = -ENODEV; | |
48944738 DV |
628 | goto out; |
629 | } | |
630 | if (ahwif->irq < 0) { | |
631 | pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id); | |
632 | ret = -ENODEV; | |
26a940e2 PP |
633 | goto out; |
634 | } | |
635 | ||
8f29e650 | 636 | if (!request_mem_region (res->start, res->end-res->start, pdev->name)) { |
26a940e2 | 637 | pr_debug("%s: request_mem_region failed\n", DRV_NAME); |
8f29e650 | 638 | ret = -EBUSY; |
26a940e2 | 639 | goto out; |
8f29e650 | 640 | } |
26a940e2 PP |
641 | |
642 | ahwif->regbase = (u32)ioremap(res->start, res->end-res->start); | |
643 | if (ahwif->regbase == 0) { | |
644 | ret = -ENOMEM; | |
645 | goto out; | |
646 | } | |
647 | ||
8f29e650 JC |
648 | /* FIXME: This might possibly break PCMCIA IDE devices */ |
649 | ||
650 | hwif = &ide_hwifs[pdev->id]; | |
1918fd63 | 651 | hw = &hwif->hw; |
8f29e650 JC |
652 | hwif->irq = hw->irq = ahwif->irq; |
653 | hwif->chipset = ide_au1xxx; | |
26a940e2 | 654 | |
8f29e650 | 655 | auide_setup_ports(hw, ahwif); |
26a940e2 PP |
656 | memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports)); |
657 | ||
8f29e650 | 658 | hwif->ultra_mask = 0x0; /* Disable Ultra DMA */ |
26a940e2 | 659 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA |
8f29e650 JC |
660 | hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */ |
661 | hwif->swdma_mask = 0x00; | |
26a940e2 | 662 | #else |
8f29e650 JC |
663 | hwif->mwdma_mask = 0x0; |
664 | hwif->swdma_mask = 0x0; | |
665 | #endif | |
666 | ||
4099d143 | 667 | hwif->pio_mask = ATA_PIO4; |
88b2b32b | 668 | hwif->host_flags = IDE_HFLAG_POST_SET_MODE; |
4099d143 | 669 | |
8f29e650 JC |
670 | hwif->noprobe = 0; |
671 | hwif->drives[0].unmask = 1; | |
672 | hwif->drives[1].unmask = 1; | |
673 | ||
674 | /* hold should be on in all cases */ | |
675 | hwif->hold = 1; | |
2ad1e558 BZ |
676 | |
677 | hwif->mmio = 1; | |
8f29e650 JC |
678 | |
679 | /* If the user has selected DDMA assisted copies, | |
680 | then set up a few local I/O function entry points | |
681 | */ | |
682 | ||
683 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA | |
684 | hwif->INSW = auide_insw; | |
685 | hwif->OUTSW = auide_outsw; | |
26a940e2 | 686 | #endif |
8f29e650 | 687 | |
26bcb879 | 688 | hwif->set_pio_mode = &au1xxx_set_pio_mode; |
88b2b32b | 689 | hwif->set_dma_mode = &auide_set_dma_mode; |
26a940e2 PP |
690 | |
691 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA | |
7469aaf6 | 692 | hwif->dma_off_quietly = &auide_dma_off_quietly; |
c283f5db | 693 | hwif->dma_timeout = &auide_dma_timeout; |
8f29e650 JC |
694 | |
695 | hwif->ide_dma_check = &auide_dma_check; | |
696 | hwif->dma_exec_cmd = &auide_dma_exec_cmd; | |
697 | hwif->dma_start = &auide_dma_start; | |
698 | hwif->ide_dma_end = &auide_dma_end; | |
699 | hwif->dma_setup = &auide_dma_setup; | |
700 | hwif->ide_dma_test_irq = &auide_dma_test_irq; | |
7469aaf6 | 701 | hwif->dma_host_off = &auide_dma_host_off; |
ccf35289 | 702 | hwif->dma_host_on = &auide_dma_host_on; |
841d2a9b | 703 | hwif->dma_lost_irq = &auide_dma_lost_irq; |
8f29e650 JC |
704 | hwif->ide_dma_on = &auide_dma_on; |
705 | ||
706 | hwif->autodma = 1; | |
707 | hwif->drives[0].autodma = hwif->autodma; | |
708 | hwif->drives[1].autodma = hwif->autodma; | |
709 | hwif->atapi_dma = 1; | |
710 | ||
26a940e2 | 711 | #else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */ |
8f29e650 JC |
712 | hwif->autodma = 0; |
713 | hwif->channel = 0; | |
714 | hwif->hold = 1; | |
715 | hwif->select_data = 0; /* no chipset-specific code */ | |
716 | hwif->config_data = 0; /* no chipset-specific code */ | |
717 | ||
718 | hwif->drives[0].autodma = 0; | |
719 | hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */ | |
26a940e2 | 720 | #endif |
8f29e650 | 721 | hwif->drives[0].no_io_32bit = 1; |
26a940e2 | 722 | |
8f29e650 JC |
723 | auide_hwif.hwif = hwif; |
724 | hwif->hwif_data = &auide_hwif; | |
26a940e2 | 725 | |
8f29e650 JC |
726 | #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA |
727 | auide_ddma_init(&auide_hwif); | |
728 | dbdma_init_done = 1; | |
26a940e2 PP |
729 | #endif |
730 | ||
731 | probe_hwif_init(hwif); | |
5cbf79cd BZ |
732 | |
733 | ide_proc_register_port(hwif); | |
734 | ||
26a940e2 PP |
735 | dev_set_drvdata(dev, hwif); |
736 | ||
8f29e650 | 737 | printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode ); |
26a940e2 | 738 | |
8f29e650 JC |
739 | out: |
740 | return ret; | |
26a940e2 PP |
741 | } |
742 | ||
743 | static int au_ide_remove(struct device *dev) | |
744 | { | |
745 | struct platform_device *pdev = to_platform_device(dev); | |
746 | struct resource *res; | |
747 | ide_hwif_t *hwif = dev_get_drvdata(dev); | |
8f29e650 | 748 | _auide_hwif *ahwif = &auide_hwif; |
26a940e2 PP |
749 | |
750 | ide_unregister(hwif - ide_hwifs); | |
751 | ||
752 | iounmap((void *)ahwif->regbase); | |
753 | ||
754 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
755 | release_mem_region(res->start, res->end - res->start); | |
756 | ||
757 | return 0; | |
758 | } | |
759 | ||
760 | static struct device_driver au1200_ide_driver = { | |
761 | .name = "au1200-ide", | |
762 | .bus = &platform_bus_type, | |
763 | .probe = au_ide_probe, | |
764 | .remove = au_ide_remove, | |
765 | }; | |
766 | ||
767 | static int __init au_ide_init(void) | |
768 | { | |
769 | return driver_register(&au1200_ide_driver); | |
770 | } | |
771 | ||
8f29e650 | 772 | static void __exit au_ide_exit(void) |
26a940e2 PP |
773 | { |
774 | driver_unregister(&au1200_ide_driver); | |
775 | } | |
776 | ||
26a940e2 PP |
777 | MODULE_LICENSE("GPL"); |
778 | MODULE_DESCRIPTION("AU1200 IDE driver"); | |
779 | ||
780 | module_init(au_ide_init); | |
781 | module_exit(au_ide_exit); |