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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com> |
3 | * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be> | |
4 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org> | |
6 | * | |
7 | * Inspired by an earlier effort from David S. Miller <davem@redhat.com> | |
8 | */ | |
9 | ||
1da177e4 LT |
10 | #include <linux/module.h> |
11 | #include <linux/types.h> | |
12 | #include <linux/kernel.h> | |
1da177e4 | 13 | #include <linux/interrupt.h> |
1da177e4 LT |
14 | #include <linux/pci.h> |
15 | #include <linux/delay.h> | |
16 | #include <linux/ide.h> | |
17 | #include <linux/init.h> | |
18 | ||
19 | #include <asm/io.h> | |
20 | ||
ced3ec8a BZ |
21 | #define DRV_NAME "ns87415" |
22 | ||
1da177e4 LT |
23 | #ifdef CONFIG_SUPERIO |
24 | /* SUPERIO 87560 is a PoS chip that NatSem denies exists. | |
25 | * Unfortunately, it's built-in on all Astro-based PA-RISC workstations | |
26 | * which use the integrated NS87514 cell for CD-ROM support. | |
27 | * i.e we have to support for CD-ROM installs. | |
28 | * See drivers/parisc/superio.c for more gory details. | |
29 | */ | |
30 | #include <asm/superio.h> | |
31 | ||
1da177e4 LT |
32 | #define SUPERIO_IDE_MAX_RETRIES 25 |
33 | ||
34 | /* Because of a defect in Super I/O, all reads of the PCI DMA status | |
35 | * registers, IDE status register and the IDE select register need to be | |
36 | * retried | |
37 | */ | |
38 | static u8 superio_ide_inb (unsigned long port) | |
39 | { | |
761052e6 BZ |
40 | u8 tmp; |
41 | int retries = SUPERIO_IDE_MAX_RETRIES; | |
42 | ||
43 | /* printk(" [ reading port 0x%x with retry ] ", port); */ | |
1da177e4 | 44 | |
761052e6 BZ |
45 | do { |
46 | tmp = inb(port); | |
47 | if (tmp == 0) | |
48 | udelay(50); | |
49 | } while (tmp == 0 && retries-- > 0); | |
50 | ||
51 | return tmp; | |
1da177e4 LT |
52 | } |
53 | ||
b73c7ee2 BZ |
54 | static u8 superio_read_status(ide_hwif_t *hwif) |
55 | { | |
56 | return superio_ide_inb(hwif->io_ports.status_addr); | |
57 | } | |
58 | ||
b2f951aa BZ |
59 | static u8 superio_read_sff_dma_status(ide_hwif_t *hwif) |
60 | { | |
cab7f8ed | 61 | return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS); |
b2f951aa BZ |
62 | } |
63 | ||
ea23b8ba BZ |
64 | static void superio_tf_read(ide_drive_t *drive, ide_task_t *task) |
65 | { | |
66 | struct ide_io_ports *io_ports = &drive->hwif->io_ports; | |
67 | struct ide_taskfile *tf = &task->tf; | |
68 | ||
69 | if (task->tf_flags & IDE_TFLAG_IN_DATA) { | |
70 | u16 data = inw(io_ports->data_addr); | |
71 | ||
72 | tf->data = data & 0xff; | |
73 | tf->hob_data = (data >> 8) & 0xff; | |
74 | } | |
75 | ||
76 | /* be sure we're looking at the low order bits */ | |
ff074883 | 77 | outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr); |
ea23b8ba | 78 | |
92eb4380 BZ |
79 | if (task->tf_flags & IDE_TFLAG_IN_FEATURE) |
80 | tf->feature = inb(io_ports->feature_addr); | |
ea23b8ba BZ |
81 | if (task->tf_flags & IDE_TFLAG_IN_NSECT) |
82 | tf->nsect = inb(io_ports->nsect_addr); | |
83 | if (task->tf_flags & IDE_TFLAG_IN_LBAL) | |
84 | tf->lbal = inb(io_ports->lbal_addr); | |
85 | if (task->tf_flags & IDE_TFLAG_IN_LBAM) | |
86 | tf->lbam = inb(io_ports->lbam_addr); | |
87 | if (task->tf_flags & IDE_TFLAG_IN_LBAH) | |
88 | tf->lbah = inb(io_ports->lbah_addr); | |
89 | if (task->tf_flags & IDE_TFLAG_IN_DEVICE) | |
90 | tf->device = superio_ide_inb(io_ports->device_addr); | |
91 | ||
92 | if (task->tf_flags & IDE_TFLAG_LBA48) { | |
ff074883 | 93 | outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr); |
ea23b8ba BZ |
94 | |
95 | if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE) | |
96 | tf->hob_feature = inb(io_ports->feature_addr); | |
97 | if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT) | |
98 | tf->hob_nsect = inb(io_ports->nsect_addr); | |
99 | if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL) | |
100 | tf->hob_lbal = inb(io_ports->lbal_addr); | |
101 | if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM) | |
102 | tf->hob_lbam = inb(io_ports->lbam_addr); | |
103 | if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH) | |
104 | tf->hob_lbah = inb(io_ports->lbah_addr); | |
105 | } | |
106 | } | |
107 | ||
374e042c BZ |
108 | static const struct ide_tp_ops superio_tp_ops = { |
109 | .exec_command = ide_exec_command, | |
110 | .read_status = superio_read_status, | |
111 | .read_altstatus = ide_read_altstatus, | |
112 | .read_sff_dma_status = superio_read_sff_dma_status, | |
113 | ||
114 | .set_irq = ide_set_irq, | |
115 | ||
116 | .tf_load = ide_tf_load, | |
117 | .tf_read = superio_tf_read, | |
118 | ||
119 | .input_data = ide_input_data, | |
120 | .output_data = ide_output_data, | |
121 | }; | |
122 | ||
123 | static void __devinit superio_init_iops(struct hwif_s *hwif) | |
1da177e4 | 124 | { |
36501650 | 125 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
761052e6 | 126 | u32 dma_stat; |
36501650 | 127 | u8 port = hwif->channel, tmp; |
1da177e4 | 128 | |
761052e6 | 129 | dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa); |
1da177e4 LT |
130 | |
131 | /* Clear error/interrupt, enable dma */ | |
761052e6 BZ |
132 | tmp = superio_ide_inb(dma_stat); |
133 | outb(tmp | 0x66, dma_stat); | |
1da177e4 LT |
134 | } |
135 | #endif | |
136 | ||
137 | static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 }; | |
138 | ||
139 | /* | |
97100fc8 | 140 | * This routine either enables/disables (according to IDE_DFLAG_PRESENT) |
1da177e4 LT |
141 | * the IRQ associated with the port (HWIF(drive)), |
142 | * and selects either PIO or DMA handshaking for the next I/O operation. | |
143 | */ | |
144 | static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma) | |
145 | { | |
146 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 147 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 148 | unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data; |
1da177e4 LT |
149 | unsigned long flags; |
150 | ||
151 | local_irq_save(flags); | |
152 | new = *old; | |
153 | ||
154 | /* Adjust IRQ enable bit */ | |
155 | bit = 1 << (8 + hwif->channel); | |
97100fc8 BZ |
156 | |
157 | if (drive->dev_flags & IDE_DFLAG_PRESENT) | |
158 | new &= ~bit; | |
159 | else | |
160 | new |= bit; | |
1da177e4 LT |
161 | |
162 | /* Select PIO or DMA, DMA may only be selected for one drive/channel. */ | |
123995b9 BZ |
163 | bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1)); |
164 | other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1)); | |
1da177e4 LT |
165 | new = use_dma ? ((new & ~other) | bit) : (new & ~bit); |
166 | ||
167 | if (new != *old) { | |
168 | unsigned char stat; | |
169 | ||
170 | /* | |
171 | * Don't change DMA engine settings while Write Buffers | |
172 | * are busy. | |
173 | */ | |
174 | (void) pci_read_config_byte(dev, 0x43, &stat); | |
175 | while (stat & 0x03) { | |
176 | udelay(1); | |
177 | (void) pci_read_config_byte(dev, 0x43, &stat); | |
178 | } | |
179 | ||
180 | *old = new; | |
181 | (void) pci_write_config_dword(dev, 0x40, new); | |
182 | ||
183 | /* | |
184 | * And let things settle... | |
185 | */ | |
186 | udelay(10); | |
187 | } | |
188 | ||
189 | local_irq_restore(flags); | |
190 | } | |
191 | ||
192 | static void ns87415_selectproc (ide_drive_t *drive) | |
193 | { | |
97100fc8 BZ |
194 | ns87415_prepare_drive(drive, |
195 | !!(drive->dev_flags & IDE_DFLAG_USING_DMA)); | |
1da177e4 LT |
196 | } |
197 | ||
5e37bdc0 | 198 | static int ns87415_dma_end(ide_drive_t *drive) |
1da177e4 LT |
199 | { |
200 | ide_hwif_t *hwif = HWIF(drive); | |
201 | u8 dma_stat = 0, dma_cmd = 0; | |
202 | ||
203 | drive->waiting_for_dma = 0; | |
374e042c | 204 | dma_stat = hwif->tp_ops->read_sff_dma_status(hwif); |
cab7f8ed BZ |
205 | /* get DMA command mode */ |
206 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); | |
1da177e4 | 207 | /* stop DMA */ |
cab7f8ed | 208 | outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); |
1da177e4 | 209 | /* from ERRATA: clear the INTR & ERROR bits */ |
cab7f8ed BZ |
210 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
211 | outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD); | |
1da177e4 LT |
212 | /* and free any DMA resources */ |
213 | ide_destroy_dmatable(drive); | |
214 | /* verify good DMA status */ | |
215 | return (dma_stat & 7) != 4; | |
216 | } | |
217 | ||
5e37bdc0 | 218 | static int ns87415_dma_setup(ide_drive_t *drive) |
1da177e4 LT |
219 | { |
220 | /* select DMA xfer */ | |
221 | ns87415_prepare_drive(drive, 1); | |
222 | if (!ide_dma_setup(drive)) | |
223 | return 0; | |
224 | /* DMA failed: select PIO xfer */ | |
225 | ns87415_prepare_drive(drive, 0); | |
226 | return 1; | |
227 | } | |
228 | ||
c20530ed | 229 | static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif) |
1da177e4 | 230 | { |
36501650 | 231 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
232 | unsigned int ctrl, using_inta; |
233 | u8 progif; | |
234 | #ifdef __sparc_v9__ | |
235 | int timeout; | |
236 | u8 stat; | |
237 | #endif | |
238 | ||
1da177e4 LT |
239 | /* |
240 | * We cannot probe for IRQ: both ports share common IRQ on INTA. | |
241 | * Also, leave IRQ masked during drive probing, to prevent infinite | |
242 | * interrupts from a potentially floating INTA.. | |
243 | * | |
244 | * IRQs get unmasked in selectproc when drive is first used. | |
245 | */ | |
246 | (void) pci_read_config_dword(dev, 0x40, &ctrl); | |
247 | (void) pci_read_config_byte(dev, 0x09, &progif); | |
248 | /* is irq in "native" mode? */ | |
249 | using_inta = progif & (1 << (hwif->channel << 1)); | |
250 | if (!using_inta) | |
251 | using_inta = ctrl & (1 << (4 + hwif->channel)); | |
252 | if (hwif->mate) { | |
253 | hwif->select_data = hwif->mate->select_data; | |
254 | } else { | |
255 | hwif->select_data = (unsigned long) | |
256 | &ns87415_control[ns87415_count++]; | |
257 | ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */ | |
258 | if (using_inta) | |
259 | ctrl &= ~(1 << 6); /* unmask INTA */ | |
260 | *((unsigned int *)hwif->select_data) = ctrl; | |
261 | (void) pci_write_config_dword(dev, 0x40, ctrl); | |
262 | ||
263 | /* | |
264 | * Set prefetch size to 512 bytes for both ports, | |
265 | * but don't turn on/off prefetching here. | |
266 | */ | |
267 | pci_write_config_byte(dev, 0x55, 0xee); | |
268 | ||
269 | #ifdef __sparc_v9__ | |
270 | /* | |
9d501529 BZ |
271 | * XXX: Reset the device, if we don't it will not respond to |
272 | * SELECT_DRIVE() properly during first ide_probe_port(). | |
1da177e4 LT |
273 | */ |
274 | timeout = 10000; | |
4c3032d8 | 275 | outb(12, hwif->io_ports.ctl_addr); |
1da177e4 | 276 | udelay(10); |
4c3032d8 | 277 | outb(8, hwif->io_ports.ctl_addr); |
1da177e4 LT |
278 | do { |
279 | udelay(50); | |
374e042c | 280 | stat = hwif->tp_ops->read_status(hwif); |
3a7d2484 BZ |
281 | if (stat == 0xff) |
282 | break; | |
283 | } while ((stat & ATA_BUSY) && --timeout); | |
1da177e4 LT |
284 | #endif |
285 | } | |
286 | ||
287 | if (!using_inta) | |
a861beb1 | 288 | hwif->irq = __ide_default_irq(hwif->io_ports.data_addr); |
1da177e4 LT |
289 | else if (!hwif->irq && hwif->mate && hwif->mate->irq) |
290 | hwif->irq = hwif->mate->irq; /* share IRQ with mate */ | |
291 | ||
292 | if (!hwif->dma_base) | |
293 | return; | |
294 | ||
cab7f8ed | 295 | outb(0x60, hwif->dma_base + ATA_DMA_STATUS); |
1da177e4 LT |
296 | } |
297 | ||
ac95beed BZ |
298 | static const struct ide_port_ops ns87415_port_ops = { |
299 | .selectproc = ns87415_selectproc, | |
300 | }; | |
301 | ||
f37afdac BZ |
302 | static const struct ide_dma_ops ns87415_dma_ops = { |
303 | .dma_host_set = ide_dma_host_set, | |
5e37bdc0 | 304 | .dma_setup = ns87415_dma_setup, |
f37afdac BZ |
305 | .dma_exec_cmd = ide_dma_exec_cmd, |
306 | .dma_start = ide_dma_start, | |
5e37bdc0 | 307 | .dma_end = ns87415_dma_end, |
f37afdac BZ |
308 | .dma_test_irq = ide_dma_test_irq, |
309 | .dma_lost_irq = ide_dma_lost_irq, | |
310 | .dma_timeout = ide_dma_timeout, | |
5e37bdc0 BZ |
311 | }; |
312 | ||
85620436 | 313 | static const struct ide_port_info ns87415_chipset __devinitdata = { |
ced3ec8a | 314 | .name = DRV_NAME, |
1da177e4 | 315 | .init_hwif = init_hwif_ns87415, |
ac95beed | 316 | .port_ops = &ns87415_port_ops, |
5e37bdc0 | 317 | .dma_ops = &ns87415_dma_ops, |
33c1002e | 318 | .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA | |
5e71d9c5 | 319 | IDE_HFLAG_NO_ATAPI_DMA, |
1da177e4 LT |
320 | }; |
321 | ||
322 | static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
323 | { | |
374e042c BZ |
324 | struct ide_port_info d = ns87415_chipset; |
325 | ||
326 | #ifdef CONFIG_SUPERIO | |
327 | if (PCI_SLOT(dev->devfn) == 0xE) { | |
328 | /* Built-in - assume it's under superio. */ | |
329 | d.init_iops = superio_init_iops; | |
330 | d.tp_ops = &superio_tp_ops; | |
331 | } | |
332 | #endif | |
6cdf6eb3 | 333 | return ide_pci_init_one(dev, &d, NULL); |
1da177e4 LT |
334 | } |
335 | ||
9cbcc5e3 BZ |
336 | static const struct pci_device_id ns87415_pci_tbl[] = { |
337 | { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 }, | |
1da177e4 LT |
338 | { 0, }, |
339 | }; | |
340 | MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl); | |
341 | ||
a9ab09e2 | 342 | static struct pci_driver ns87415_pci_driver = { |
1da177e4 LT |
343 | .name = "NS87415_IDE", |
344 | .id_table = ns87415_pci_tbl, | |
345 | .probe = ns87415_init_one, | |
aa6e518d | 346 | .remove = ide_pci_remove, |
feb22b7f BZ |
347 | .suspend = ide_pci_suspend, |
348 | .resume = ide_pci_resume, | |
1da177e4 LT |
349 | }; |
350 | ||
82ab1eec | 351 | static int __init ns87415_ide_init(void) |
1da177e4 | 352 | { |
a9ab09e2 | 353 | return ide_pci_register_driver(&ns87415_pci_driver); |
1da177e4 LT |
354 | } |
355 | ||
aa6e518d BZ |
356 | static void __exit ns87415_ide_exit(void) |
357 | { | |
a9ab09e2 | 358 | pci_unregister_driver(&ns87415_pci_driver); |
aa6e518d BZ |
359 | } |
360 | ||
1da177e4 | 361 | module_init(ns87415_ide_init); |
aa6e518d | 362 | module_exit(ns87415_ide_exit); |
1da177e4 LT |
363 | |
364 | MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick"); | |
365 | MODULE_DESCRIPTION("PCI driver module for NS87415 IDE"); | |
366 | MODULE_LICENSE("GPL"); |