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Commit | Line | Data |
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1da177e4 | 1 | /* |
6d78013b | 2 | * linux/drivers/ide/pci/aec62xx.c Version 0.24 May 24, 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> | |
826a1b65 | 5 | * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 LT |
6 | * |
7 | */ | |
8 | ||
9 | #include <linux/module.h> | |
1da177e4 LT |
10 | #include <linux/types.h> |
11 | #include <linux/pci.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/hdreg.h> | |
14 | #include <linux/ide.h> | |
15 | #include <linux/init.h> | |
16 | ||
17 | #include <asm/io.h> | |
18 | ||
19 | struct chipset_bus_clock_list_entry { | |
20 | u8 xfer_speed; | |
21 | u8 chipset_settings; | |
22 | u8 ultra_settings; | |
23 | }; | |
24 | ||
f201f504 | 25 | static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = { |
1da177e4 LT |
26 | { XFER_UDMA_6, 0x31, 0x07 }, |
27 | { XFER_UDMA_5, 0x31, 0x06 }, | |
28 | { XFER_UDMA_4, 0x31, 0x05 }, | |
29 | { XFER_UDMA_3, 0x31, 0x04 }, | |
30 | { XFER_UDMA_2, 0x31, 0x03 }, | |
31 | { XFER_UDMA_1, 0x31, 0x02 }, | |
32 | { XFER_UDMA_0, 0x31, 0x01 }, | |
33 | ||
34 | { XFER_MW_DMA_2, 0x31, 0x00 }, | |
35 | { XFER_MW_DMA_1, 0x31, 0x00 }, | |
36 | { XFER_MW_DMA_0, 0x0a, 0x00 }, | |
37 | { XFER_PIO_4, 0x31, 0x00 }, | |
38 | { XFER_PIO_3, 0x33, 0x00 }, | |
39 | { XFER_PIO_2, 0x08, 0x00 }, | |
40 | { XFER_PIO_1, 0x0a, 0x00 }, | |
41 | { XFER_PIO_0, 0x00, 0x00 }, | |
42 | { 0, 0x00, 0x00 } | |
43 | }; | |
44 | ||
f201f504 | 45 | static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = { |
1da177e4 LT |
46 | { XFER_UDMA_6, 0x41, 0x06 }, |
47 | { XFER_UDMA_5, 0x41, 0x05 }, | |
48 | { XFER_UDMA_4, 0x41, 0x04 }, | |
49 | { XFER_UDMA_3, 0x41, 0x03 }, | |
50 | { XFER_UDMA_2, 0x41, 0x02 }, | |
51 | { XFER_UDMA_1, 0x41, 0x01 }, | |
52 | { XFER_UDMA_0, 0x41, 0x01 }, | |
53 | ||
54 | { XFER_MW_DMA_2, 0x41, 0x00 }, | |
55 | { XFER_MW_DMA_1, 0x42, 0x00 }, | |
56 | { XFER_MW_DMA_0, 0x7a, 0x00 }, | |
57 | { XFER_PIO_4, 0x41, 0x00 }, | |
58 | { XFER_PIO_3, 0x43, 0x00 }, | |
59 | { XFER_PIO_2, 0x78, 0x00 }, | |
60 | { XFER_PIO_1, 0x7a, 0x00 }, | |
61 | { XFER_PIO_0, 0x70, 0x00 }, | |
62 | { 0, 0x00, 0x00 } | |
63 | }; | |
64 | ||
65 | #define BUSCLOCK(D) \ | |
66 | ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D))) | |
67 | ||
1da177e4 LT |
68 | |
69 | /* | |
70 | * TO DO: active tuning and correction of cards without a bios. | |
71 | */ | |
72 | static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table) | |
73 | { | |
74 | for ( ; chipset_table->xfer_speed ; chipset_table++) | |
75 | if (chipset_table->xfer_speed == speed) { | |
76 | return chipset_table->chipset_settings; | |
77 | } | |
78 | return chipset_table->chipset_settings; | |
79 | } | |
80 | ||
81 | static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table) | |
82 | { | |
83 | for ( ; chipset_table->xfer_speed ; chipset_table++) | |
84 | if (chipset_table->xfer_speed == speed) { | |
85 | return chipset_table->ultra_settings; | |
86 | } | |
87 | return chipset_table->ultra_settings; | |
88 | } | |
89 | ||
88b2b32b | 90 | static void aec6210_set_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
91 | { |
92 | ide_hwif_t *hwif = HWIF(drive); | |
93 | struct pci_dev *dev = hwif->pci_dev; | |
94 | u16 d_conf = 0; | |
1da177e4 LT |
95 | u8 ultra = 0, ultra_conf = 0; |
96 | u8 tmp0 = 0, tmp1 = 0, tmp2 = 0; | |
97 | unsigned long flags; | |
98 | ||
99 | local_irq_save(flags); | |
100 | /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */ | |
101 | pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf); | |
102 | tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev)); | |
103 | d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf); | |
104 | pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf); | |
105 | ||
106 | tmp1 = 0x00; | |
107 | tmp2 = 0x00; | |
108 | pci_read_config_byte(dev, 0x54, &ultra); | |
109 | tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn)))); | |
110 | ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev)); | |
111 | tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn)))); | |
112 | pci_write_config_byte(dev, 0x54, tmp2); | |
113 | local_irq_restore(flags); | |
1da177e4 LT |
114 | } |
115 | ||
88b2b32b | 116 | static void aec6260_set_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
117 | { |
118 | ide_hwif_t *hwif = HWIF(drive); | |
119 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 LT |
120 | u8 unit = (drive->select.b.unit & 0x01); |
121 | u8 tmp1 = 0, tmp2 = 0; | |
122 | u8 ultra = 0, drive_conf = 0, ultra_conf = 0; | |
123 | unsigned long flags; | |
124 | ||
125 | local_irq_save(flags); | |
126 | /* high 4-bits: Active, low 4-bits: Recovery */ | |
127 | pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf); | |
128 | drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev)); | |
129 | pci_write_config_byte(dev, 0x40|drive->dn, drive_conf); | |
130 | ||
131 | pci_read_config_byte(dev, (0x44|hwif->channel), &ultra); | |
132 | tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit)))); | |
133 | ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev)); | |
134 | tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit)))); | |
135 | pci_write_config_byte(dev, (0x44|hwif->channel), tmp2); | |
136 | local_irq_restore(flags); | |
1da177e4 LT |
137 | } |
138 | ||
26bcb879 | 139 | static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 140 | { |
88b2b32b | 141 | drive->hwif->set_dma_mode(drive, pio + XFER_PIO_0); |
1da177e4 LT |
142 | } |
143 | ||
144 | static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive) | |
145 | { | |
29e744d0 | 146 | if (ide_tune_dma(drive)) |
3608b5d7 | 147 | return 0; |
1da177e4 | 148 | |
d8f4469d | 149 | if (ide_use_fast_pio(drive)) |
26bcb879 | 150 | ide_set_max_pio(drive); |
d8f4469d | 151 | |
3608b5d7 | 152 | return -1; |
1da177e4 LT |
153 | } |
154 | ||
841d2a9b | 155 | static void aec62xx_dma_lost_irq (ide_drive_t *drive) |
1da177e4 | 156 | { |
841d2a9b | 157 | switch (HWIF(drive)->pci_dev->device) { |
1da177e4 LT |
158 | case PCI_DEVICE_ID_ARTOP_ATP860: |
159 | case PCI_DEVICE_ID_ARTOP_ATP860R: | |
160 | case PCI_DEVICE_ID_ARTOP_ATP865: | |
161 | case PCI_DEVICE_ID_ARTOP_ATP865R: | |
162 | printk(" AEC62XX time out "); | |
1da177e4 LT |
163 | default: |
164 | break; | |
165 | } | |
1da177e4 LT |
166 | } |
167 | ||
168 | static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name) | |
169 | { | |
170 | int bus_speed = system_bus_clock(); | |
171 | ||
1da177e4 LT |
172 | if (bus_speed <= 33) |
173 | pci_set_drvdata(dev, (void *) aec6xxx_33_base); | |
174 | else | |
175 | pci_set_drvdata(dev, (void *) aec6xxx_34_base); | |
176 | ||
d237bf49 TV |
177 | /* These are necessary to get AEC6280 Macintosh cards to work */ |
178 | if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) || | |
179 | (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) { | |
180 | u8 reg49h = 0, reg4ah = 0; | |
181 | /* Clear reset and test bits. */ | |
182 | pci_read_config_byte(dev, 0x49, ®49h); | |
183 | pci_write_config_byte(dev, 0x49, reg49h & ~0x30); | |
184 | /* Enable chip interrupt output. */ | |
185 | pci_read_config_byte(dev, 0x4a, ®4ah); | |
186 | pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01); | |
187 | /* Enable burst mode. */ | |
188 | pci_read_config_byte(dev, 0x4a, ®4ah); | |
189 | pci_write_config_byte(dev, 0x4a, reg4ah | 0x80); | |
190 | } | |
191 | ||
1da177e4 LT |
192 | return dev->irq; |
193 | } | |
194 | ||
195 | static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif) | |
196 | { | |
1b9da32a SS |
197 | struct pci_dev *dev = hwif->pci_dev; |
198 | u8 reg54 = 0, mask = hwif->channel ? 0xf0 : 0x0f; | |
199 | unsigned long flags; | |
18137207 | 200 | |
26bcb879 | 201 | hwif->set_pio_mode = &aec_set_pio_mode; |
1da177e4 | 202 | |
6d78013b SS |
203 | if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) { |
204 | if(hwif->mate) | |
205 | hwif->mate->serialized = hwif->serialized = 1; | |
88b2b32b | 206 | hwif->set_dma_mode = &aec6210_set_mode; |
6d78013b | 207 | } else |
88b2b32b | 208 | hwif->set_dma_mode = &aec6260_set_mode; |
1da177e4 LT |
209 | |
210 | if (!hwif->dma_base) { | |
1b9da32a | 211 | hwif->drives[0].autotune = hwif->drives[1].autotune = 1; |
1da177e4 LT |
212 | return; |
213 | } | |
214 | ||
18137207 | 215 | hwif->ultra_mask = hwif->cds->udma_mask; |
1da177e4 | 216 | hwif->mwdma_mask = 0x07; |
1da177e4 LT |
217 | |
218 | hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate; | |
841d2a9b | 219 | hwif->dma_lost_irq = &aec62xx_dma_lost_irq; |
826a1b65 | 220 | |
1da177e4 | 221 | if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) { |
1da177e4 | 222 | spin_lock_irqsave(&ide_lock, flags); |
1b9da32a SS |
223 | pci_read_config_byte (dev, 0x54, ®54); |
224 | pci_write_config_byte(dev, 0x54, (reg54 & ~mask)); | |
1da177e4 | 225 | spin_unlock_irqrestore(&ide_lock, flags); |
49521f97 | 226 | } else if (hwif->cbl != ATA_CBL_PATA40_SHORT) { |
1b9da32a SS |
227 | u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01; |
228 | ||
1da177e4 | 229 | pci_read_config_byte(hwif->pci_dev, 0x49, &ata66); |
49521f97 BZ |
230 | |
231 | hwif->cbl = (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; | |
1da177e4 LT |
232 | } |
233 | ||
1b9da32a SS |
234 | if (!noautodma) |
235 | hwif->autodma = 1; | |
236 | hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma; | |
1da177e4 LT |
237 | } |
238 | ||
239 | static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d) | |
240 | { | |
241 | return ide_setup_pci_device(dev, d); | |
242 | } | |
243 | ||
244 | static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d) | |
245 | { | |
b1d19db4 | 246 | unsigned long dma_base = pci_resource_start(dev, 4); |
1da177e4 | 247 | |
b1d19db4 SS |
248 | if (inb(dma_base + 2) & 0x10) { |
249 | d->name = (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R) ? | |
250 | "AEC6880R" : "AEC6880"; | |
251 | d->udma_mask = 0x7f; /* udma0-6 */ | |
1da177e4 LT |
252 | } |
253 | ||
254 | return ide_setup_pci_device(dev, d); | |
255 | } | |
256 | ||
257 | static ide_pci_device_t aec62xx_chipsets[] __devinitdata = { | |
258 | { /* 0 */ | |
259 | .name = "AEC6210", | |
260 | .init_setup = init_setup_aec62xx, | |
261 | .init_chipset = init_chipset_aec62xx, | |
262 | .init_hwif = init_hwif_aec62xx, | |
1da177e4 LT |
263 | .autodma = AUTODMA, |
264 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, | |
265 | .bootable = OFF_BOARD, | |
4099d143 | 266 | .pio_mask = ATA_PIO4, |
18137207 | 267 | .udma_mask = 0x07, /* udma0-2 */ |
1da177e4 LT |
268 | },{ /* 1 */ |
269 | .name = "AEC6260", | |
270 | .init_setup = init_setup_aec62xx, | |
271 | .init_chipset = init_chipset_aec62xx, | |
272 | .init_hwif = init_hwif_aec62xx, | |
1da177e4 LT |
273 | .autodma = NOAUTODMA, |
274 | .bootable = OFF_BOARD, | |
4099d143 | 275 | .pio_mask = ATA_PIO4, |
18137207 | 276 | .udma_mask = 0x1f, /* udma0-4 */ |
1da177e4 LT |
277 | },{ /* 2 */ |
278 | .name = "AEC6260R", | |
279 | .init_setup = init_setup_aec62xx, | |
280 | .init_chipset = init_chipset_aec62xx, | |
281 | .init_hwif = init_hwif_aec62xx, | |
1da177e4 LT |
282 | .autodma = AUTODMA, |
283 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, | |
284 | .bootable = NEVER_BOARD, | |
4099d143 | 285 | .pio_mask = ATA_PIO4, |
18137207 | 286 | .udma_mask = 0x1f, /* udma0-4 */ |
1da177e4 | 287 | },{ /* 3 */ |
b1d19db4 | 288 | .name = "AEC6280", |
1da177e4 LT |
289 | .init_setup = init_setup_aec6x80, |
290 | .init_chipset = init_chipset_aec62xx, | |
291 | .init_hwif = init_hwif_aec62xx, | |
1da177e4 LT |
292 | .autodma = AUTODMA, |
293 | .bootable = OFF_BOARD, | |
4099d143 | 294 | .pio_mask = ATA_PIO4, |
18137207 | 295 | .udma_mask = 0x3f, /* udma0-5 */ |
1da177e4 | 296 | },{ /* 4 */ |
b1d19db4 | 297 | .name = "AEC6280R", |
1da177e4 LT |
298 | .init_setup = init_setup_aec6x80, |
299 | .init_chipset = init_chipset_aec62xx, | |
300 | .init_hwif = init_hwif_aec62xx, | |
1da177e4 LT |
301 | .autodma = AUTODMA, |
302 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, | |
303 | .bootable = OFF_BOARD, | |
4099d143 | 304 | .pio_mask = ATA_PIO4, |
18137207 | 305 | .udma_mask = 0x3f, /* udma0-5 */ |
1da177e4 LT |
306 | } |
307 | }; | |
308 | ||
309 | /** | |
310 | * aec62xx_init_one - called when a AEC is found | |
311 | * @dev: the aec62xx device | |
312 | * @id: the matching pci id | |
313 | * | |
314 | * Called when the PCI registration layer (or the IDE initialization) | |
315 | * finds a device matching our IDE device tables. | |
b1d19db4 SS |
316 | * |
317 | * NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R] | |
318 | * chips, pass a local copy of 'struct pci_device_id' down the call chain. | |
1da177e4 LT |
319 | */ |
320 | ||
321 | static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
322 | { | |
b1d19db4 | 323 | ide_pci_device_t d = aec62xx_chipsets[id->driver_data]; |
1da177e4 | 324 | |
b1d19db4 | 325 | return d.init_setup(dev, &d); |
1da177e4 LT |
326 | } |
327 | ||
28a2a3f5 AC |
328 | static struct pci_device_id aec62xx_pci_tbl[] = { |
329 | { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
330 | { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, | |
331 | { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 }, | |
332 | { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 }, | |
333 | { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, | |
1da177e4 LT |
334 | { 0, }, |
335 | }; | |
336 | MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl); | |
337 | ||
338 | static struct pci_driver driver = { | |
339 | .name = "AEC62xx_IDE", | |
340 | .id_table = aec62xx_pci_tbl, | |
341 | .probe = aec62xx_init_one, | |
342 | }; | |
343 | ||
82ab1eec | 344 | static int __init aec62xx_ide_init(void) |
1da177e4 LT |
345 | { |
346 | return ide_pci_register_driver(&driver); | |
347 | } | |
348 | ||
349 | module_init(aec62xx_ide_init); | |
350 | ||
351 | MODULE_AUTHOR("Andre Hedrick"); | |
352 | MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE"); | |
353 | MODULE_LICENSE("GPL"); |