]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
b1d19db4 | 2 | * linux/drivers/ide/pci/aec62xx.c Version 0.22 Apr 23, 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> | |
826a1b65 | 5 | * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 LT |
6 | * |
7 | */ | |
8 | ||
9 | #include <linux/module.h> | |
1da177e4 LT |
10 | #include <linux/types.h> |
11 | #include <linux/pci.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/hdreg.h> | |
14 | #include <linux/ide.h> | |
15 | #include <linux/init.h> | |
16 | ||
17 | #include <asm/io.h> | |
18 | ||
19 | struct chipset_bus_clock_list_entry { | |
20 | u8 xfer_speed; | |
21 | u8 chipset_settings; | |
22 | u8 ultra_settings; | |
23 | }; | |
24 | ||
f201f504 | 25 | static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = { |
1da177e4 LT |
26 | { XFER_UDMA_6, 0x31, 0x07 }, |
27 | { XFER_UDMA_5, 0x31, 0x06 }, | |
28 | { XFER_UDMA_4, 0x31, 0x05 }, | |
29 | { XFER_UDMA_3, 0x31, 0x04 }, | |
30 | { XFER_UDMA_2, 0x31, 0x03 }, | |
31 | { XFER_UDMA_1, 0x31, 0x02 }, | |
32 | { XFER_UDMA_0, 0x31, 0x01 }, | |
33 | ||
34 | { XFER_MW_DMA_2, 0x31, 0x00 }, | |
35 | { XFER_MW_DMA_1, 0x31, 0x00 }, | |
36 | { XFER_MW_DMA_0, 0x0a, 0x00 }, | |
37 | { XFER_PIO_4, 0x31, 0x00 }, | |
38 | { XFER_PIO_3, 0x33, 0x00 }, | |
39 | { XFER_PIO_2, 0x08, 0x00 }, | |
40 | { XFER_PIO_1, 0x0a, 0x00 }, | |
41 | { XFER_PIO_0, 0x00, 0x00 }, | |
42 | { 0, 0x00, 0x00 } | |
43 | }; | |
44 | ||
f201f504 | 45 | static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = { |
1da177e4 LT |
46 | { XFER_UDMA_6, 0x41, 0x06 }, |
47 | { XFER_UDMA_5, 0x41, 0x05 }, | |
48 | { XFER_UDMA_4, 0x41, 0x04 }, | |
49 | { XFER_UDMA_3, 0x41, 0x03 }, | |
50 | { XFER_UDMA_2, 0x41, 0x02 }, | |
51 | { XFER_UDMA_1, 0x41, 0x01 }, | |
52 | { XFER_UDMA_0, 0x41, 0x01 }, | |
53 | ||
54 | { XFER_MW_DMA_2, 0x41, 0x00 }, | |
55 | { XFER_MW_DMA_1, 0x42, 0x00 }, | |
56 | { XFER_MW_DMA_0, 0x7a, 0x00 }, | |
57 | { XFER_PIO_4, 0x41, 0x00 }, | |
58 | { XFER_PIO_3, 0x43, 0x00 }, | |
59 | { XFER_PIO_2, 0x78, 0x00 }, | |
60 | { XFER_PIO_1, 0x7a, 0x00 }, | |
61 | { XFER_PIO_0, 0x70, 0x00 }, | |
62 | { 0, 0x00, 0x00 } | |
63 | }; | |
64 | ||
65 | #define BUSCLOCK(D) \ | |
66 | ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D))) | |
67 | ||
1da177e4 LT |
68 | |
69 | /* | |
70 | * TO DO: active tuning and correction of cards without a bios. | |
71 | */ | |
72 | static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table) | |
73 | { | |
74 | for ( ; chipset_table->xfer_speed ; chipset_table++) | |
75 | if (chipset_table->xfer_speed == speed) { | |
76 | return chipset_table->chipset_settings; | |
77 | } | |
78 | return chipset_table->chipset_settings; | |
79 | } | |
80 | ||
81 | static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table) | |
82 | { | |
83 | for ( ; chipset_table->xfer_speed ; chipset_table++) | |
84 | if (chipset_table->xfer_speed == speed) { | |
85 | return chipset_table->ultra_settings; | |
86 | } | |
87 | return chipset_table->ultra_settings; | |
88 | } | |
89 | ||
1da177e4 LT |
90 | static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed) |
91 | { | |
92 | ide_hwif_t *hwif = HWIF(drive); | |
93 | struct pci_dev *dev = hwif->pci_dev; | |
94 | u16 d_conf = 0; | |
2d5eaa6d | 95 | u8 speed = ide_rate_filter(drive, xferspeed); |
1da177e4 LT |
96 | u8 ultra = 0, ultra_conf = 0; |
97 | u8 tmp0 = 0, tmp1 = 0, tmp2 = 0; | |
98 | unsigned long flags; | |
99 | ||
100 | local_irq_save(flags); | |
101 | /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */ | |
102 | pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf); | |
103 | tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev)); | |
104 | d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf); | |
105 | pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf); | |
106 | ||
107 | tmp1 = 0x00; | |
108 | tmp2 = 0x00; | |
109 | pci_read_config_byte(dev, 0x54, &ultra); | |
110 | tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn)))); | |
111 | ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev)); | |
112 | tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn)))); | |
113 | pci_write_config_byte(dev, 0x54, tmp2); | |
114 | local_irq_restore(flags); | |
115 | return(ide_config_drive_speed(drive, speed)); | |
116 | } | |
117 | ||
118 | static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed) | |
119 | { | |
120 | ide_hwif_t *hwif = HWIF(drive); | |
121 | struct pci_dev *dev = hwif->pci_dev; | |
2d5eaa6d | 122 | u8 speed = ide_rate_filter(drive, xferspeed); |
1da177e4 LT |
123 | u8 unit = (drive->select.b.unit & 0x01); |
124 | u8 tmp1 = 0, tmp2 = 0; | |
125 | u8 ultra = 0, drive_conf = 0, ultra_conf = 0; | |
126 | unsigned long flags; | |
127 | ||
128 | local_irq_save(flags); | |
129 | /* high 4-bits: Active, low 4-bits: Recovery */ | |
130 | pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf); | |
131 | drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev)); | |
132 | pci_write_config_byte(dev, 0x40|drive->dn, drive_conf); | |
133 | ||
134 | pci_read_config_byte(dev, (0x44|hwif->channel), &ultra); | |
135 | tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit)))); | |
136 | ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev)); | |
137 | tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit)))); | |
138 | pci_write_config_byte(dev, (0x44|hwif->channel), tmp2); | |
139 | local_irq_restore(flags); | |
140 | return(ide_config_drive_speed(drive, speed)); | |
141 | } | |
142 | ||
143 | static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed) | |
144 | { | |
145 | switch (HWIF(drive)->pci_dev->device) { | |
146 | case PCI_DEVICE_ID_ARTOP_ATP865: | |
147 | case PCI_DEVICE_ID_ARTOP_ATP865R: | |
148 | case PCI_DEVICE_ID_ARTOP_ATP860: | |
149 | case PCI_DEVICE_ID_ARTOP_ATP860R: | |
150 | return ((int) aec6260_tune_chipset(drive, speed)); | |
151 | case PCI_DEVICE_ID_ARTOP_ATP850UF: | |
152 | return ((int) aec6210_tune_chipset(drive, speed)); | |
153 | default: | |
154 | return -1; | |
155 | } | |
156 | } | |
157 | ||
1da177e4 LT |
158 | static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio) |
159 | { | |
826a1b65 SS |
160 | pio = ide_get_best_pio_mode(drive, pio, 4, NULL); |
161 | (void) aec62xx_tune_chipset(drive, pio + XFER_PIO_0); | |
1da177e4 LT |
162 | } |
163 | ||
164 | static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive) | |
165 | { | |
29e744d0 | 166 | if (ide_tune_dma(drive)) |
3608b5d7 | 167 | return 0; |
1da177e4 | 168 | |
d8f4469d | 169 | if (ide_use_fast_pio(drive)) |
826a1b65 | 170 | aec62xx_tune_drive(drive, 255); |
d8f4469d | 171 | |
3608b5d7 | 172 | return -1; |
1da177e4 LT |
173 | } |
174 | ||
841d2a9b | 175 | static void aec62xx_dma_lost_irq (ide_drive_t *drive) |
1da177e4 | 176 | { |
841d2a9b | 177 | switch (HWIF(drive)->pci_dev->device) { |
1da177e4 LT |
178 | case PCI_DEVICE_ID_ARTOP_ATP860: |
179 | case PCI_DEVICE_ID_ARTOP_ATP860R: | |
180 | case PCI_DEVICE_ID_ARTOP_ATP865: | |
181 | case PCI_DEVICE_ID_ARTOP_ATP865R: | |
182 | printk(" AEC62XX time out "); | |
1da177e4 LT |
183 | default: |
184 | break; | |
185 | } | |
1da177e4 LT |
186 | } |
187 | ||
188 | static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name) | |
189 | { | |
190 | int bus_speed = system_bus_clock(); | |
191 | ||
192 | if (dev->resource[PCI_ROM_RESOURCE].start) { | |
193 | pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); | |
08f46de9 GKH |
194 | printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, |
195 | (unsigned long)dev->resource[PCI_ROM_RESOURCE].start); | |
1da177e4 LT |
196 | } |
197 | ||
198 | if (bus_speed <= 33) | |
199 | pci_set_drvdata(dev, (void *) aec6xxx_33_base); | |
200 | else | |
201 | pci_set_drvdata(dev, (void *) aec6xxx_34_base); | |
202 | ||
d237bf49 TV |
203 | /* These are necessary to get AEC6280 Macintosh cards to work */ |
204 | if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) || | |
205 | (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) { | |
206 | u8 reg49h = 0, reg4ah = 0; | |
207 | /* Clear reset and test bits. */ | |
208 | pci_read_config_byte(dev, 0x49, ®49h); | |
209 | pci_write_config_byte(dev, 0x49, reg49h & ~0x30); | |
210 | /* Enable chip interrupt output. */ | |
211 | pci_read_config_byte(dev, 0x4a, ®4ah); | |
212 | pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01); | |
213 | /* Enable burst mode. */ | |
214 | pci_read_config_byte(dev, 0x4a, ®4ah); | |
215 | pci_write_config_byte(dev, 0x4a, reg4ah | 0x80); | |
216 | } | |
217 | ||
1da177e4 LT |
218 | return dev->irq; |
219 | } | |
220 | ||
221 | static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif) | |
222 | { | |
18137207 BZ |
223 | struct pci_dev *dev = hwif->pci_dev; |
224 | ||
1da177e4 LT |
225 | hwif->autodma = 0; |
226 | hwif->tuneproc = &aec62xx_tune_drive; | |
227 | hwif->speedproc = &aec62xx_tune_chipset; | |
228 | ||
18137207 | 229 | if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) |
1da177e4 | 230 | hwif->serialized = hwif->channel; |
1da177e4 LT |
231 | |
232 | if (hwif->mate) | |
233 | hwif->mate->serialized = hwif->serialized; | |
234 | ||
235 | if (!hwif->dma_base) { | |
236 | hwif->drives[0].autotune = 1; | |
237 | hwif->drives[1].autotune = 1; | |
238 | return; | |
239 | } | |
240 | ||
18137207 | 241 | hwif->ultra_mask = hwif->cds->udma_mask; |
1da177e4 | 242 | hwif->mwdma_mask = 0x07; |
1da177e4 LT |
243 | |
244 | hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate; | |
841d2a9b | 245 | hwif->dma_lost_irq = &aec62xx_dma_lost_irq; |
826a1b65 | 246 | |
1da177e4 LT |
247 | if (!noautodma) |
248 | hwif->autodma = 1; | |
249 | hwif->drives[0].autodma = hwif->autodma; | |
250 | hwif->drives[1].autodma = hwif->autodma; | |
251 | } | |
252 | ||
253 | static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase) | |
254 | { | |
255 | struct pci_dev *dev = hwif->pci_dev; | |
256 | ||
257 | if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) { | |
258 | u8 reg54h = 0; | |
259 | unsigned long flags; | |
260 | ||
261 | spin_lock_irqsave(&ide_lock, flags); | |
262 | pci_read_config_byte(dev, 0x54, ®54h); | |
263 | pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F)); | |
264 | spin_unlock_irqrestore(&ide_lock, flags); | |
265 | } else { | |
266 | u8 ata66 = 0; | |
267 | pci_read_config_byte(hwif->pci_dev, 0x49, &ata66); | |
268 | if (!(hwif->udma_four)) | |
269 | hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1; | |
270 | } | |
271 | ||
272 | ide_setup_dma(hwif, dmabase, 8); | |
273 | } | |
274 | ||
275 | static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d) | |
276 | { | |
277 | return ide_setup_pci_device(dev, d); | |
278 | } | |
279 | ||
280 | static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d) | |
281 | { | |
b1d19db4 | 282 | unsigned long dma_base = pci_resource_start(dev, 4); |
1da177e4 | 283 | |
b1d19db4 SS |
284 | if (inb(dma_base + 2) & 0x10) { |
285 | d->name = (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R) ? | |
286 | "AEC6880R" : "AEC6880"; | |
287 | d->udma_mask = 0x7f; /* udma0-6 */ | |
1da177e4 LT |
288 | } |
289 | ||
290 | return ide_setup_pci_device(dev, d); | |
291 | } | |
292 | ||
293 | static ide_pci_device_t aec62xx_chipsets[] __devinitdata = { | |
294 | { /* 0 */ | |
295 | .name = "AEC6210", | |
296 | .init_setup = init_setup_aec62xx, | |
297 | .init_chipset = init_chipset_aec62xx, | |
298 | .init_hwif = init_hwif_aec62xx, | |
299 | .init_dma = init_dma_aec62xx, | |
300 | .channels = 2, | |
301 | .autodma = AUTODMA, | |
302 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, | |
303 | .bootable = OFF_BOARD, | |
18137207 | 304 | .udma_mask = 0x07, /* udma0-2 */ |
1da177e4 LT |
305 | },{ /* 1 */ |
306 | .name = "AEC6260", | |
307 | .init_setup = init_setup_aec62xx, | |
308 | .init_chipset = init_chipset_aec62xx, | |
309 | .init_hwif = init_hwif_aec62xx, | |
310 | .init_dma = init_dma_aec62xx, | |
311 | .channels = 2, | |
312 | .autodma = NOAUTODMA, | |
313 | .bootable = OFF_BOARD, | |
18137207 | 314 | .udma_mask = 0x1f, /* udma0-4 */ |
1da177e4 LT |
315 | },{ /* 2 */ |
316 | .name = "AEC6260R", | |
317 | .init_setup = init_setup_aec62xx, | |
318 | .init_chipset = init_chipset_aec62xx, | |
319 | .init_hwif = init_hwif_aec62xx, | |
320 | .init_dma = init_dma_aec62xx, | |
321 | .channels = 2, | |
322 | .autodma = AUTODMA, | |
323 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, | |
324 | .bootable = NEVER_BOARD, | |
18137207 | 325 | .udma_mask = 0x1f, /* udma0-4 */ |
1da177e4 | 326 | },{ /* 3 */ |
b1d19db4 | 327 | .name = "AEC6280", |
1da177e4 LT |
328 | .init_setup = init_setup_aec6x80, |
329 | .init_chipset = init_chipset_aec62xx, | |
330 | .init_hwif = init_hwif_aec62xx, | |
331 | .init_dma = init_dma_aec62xx, | |
332 | .channels = 2, | |
333 | .autodma = AUTODMA, | |
334 | .bootable = OFF_BOARD, | |
18137207 | 335 | .udma_mask = 0x3f, /* udma0-5 */ |
1da177e4 | 336 | },{ /* 4 */ |
b1d19db4 | 337 | .name = "AEC6280R", |
1da177e4 LT |
338 | .init_setup = init_setup_aec6x80, |
339 | .init_chipset = init_chipset_aec62xx, | |
340 | .init_hwif = init_hwif_aec62xx, | |
341 | .init_dma = init_dma_aec62xx, | |
342 | .channels = 2, | |
343 | .autodma = AUTODMA, | |
344 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, | |
345 | .bootable = OFF_BOARD, | |
18137207 | 346 | .udma_mask = 0x3f, /* udma0-5 */ |
1da177e4 LT |
347 | } |
348 | }; | |
349 | ||
350 | /** | |
351 | * aec62xx_init_one - called when a AEC is found | |
352 | * @dev: the aec62xx device | |
353 | * @id: the matching pci id | |
354 | * | |
355 | * Called when the PCI registration layer (or the IDE initialization) | |
356 | * finds a device matching our IDE device tables. | |
b1d19db4 SS |
357 | * |
358 | * NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R] | |
359 | * chips, pass a local copy of 'struct pci_device_id' down the call chain. | |
1da177e4 LT |
360 | */ |
361 | ||
362 | static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
363 | { | |
b1d19db4 | 364 | ide_pci_device_t d = aec62xx_chipsets[id->driver_data]; |
1da177e4 | 365 | |
b1d19db4 | 366 | return d.init_setup(dev, &d); |
1da177e4 LT |
367 | } |
368 | ||
28a2a3f5 AC |
369 | static struct pci_device_id aec62xx_pci_tbl[] = { |
370 | { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
371 | { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, | |
372 | { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 }, | |
373 | { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 }, | |
374 | { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, | |
1da177e4 LT |
375 | { 0, }, |
376 | }; | |
377 | MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl); | |
378 | ||
379 | static struct pci_driver driver = { | |
380 | .name = "AEC62xx_IDE", | |
381 | .id_table = aec62xx_pci_tbl, | |
382 | .probe = aec62xx_init_one, | |
383 | }; | |
384 | ||
82ab1eec | 385 | static int __init aec62xx_ide_init(void) |
1da177e4 LT |
386 | { |
387 | return ide_pci_register_driver(&driver); | |
388 | } | |
389 | ||
390 | module_init(aec62xx_ide_init); | |
391 | ||
392 | MODULE_AUTHOR("Andre Hedrick"); | |
393 | MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE"); | |
394 | MODULE_LICENSE("GPL"); |