[mirror_ubuntu-zesty-kernel.git] / drivers / ide / pci / aec62xx.c

/*
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007		MontaVista Software, Inc. <source@mvista.com>
 *
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

struct chipset_bus_clock_list_entry {
	u8 xfer_speed;
	u8 chipset_settings;
	u8 ultra_settings;
};

static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
	{	XFER_UDMA_6,	0x31,	0x07	},
	{	XFER_UDMA_5,	0x31,	0x06	},
	{	XFER_UDMA_4,	0x31,	0x05	},
	{	XFER_UDMA_3,	0x31,	0x04	},
	{	XFER_UDMA_2,	0x31,	0x03	},
	{	XFER_UDMA_1,	0x31,	0x02	},
	{	XFER_UDMA_0,	0x31,	0x01	},

	{	XFER_MW_DMA_2,	0x31,	0x00	},
	{	XFER_MW_DMA_1,	0x31,	0x00	},
	{	XFER_MW_DMA_0,	0x0a,	0x00	},
	{	XFER_PIO_4,	0x31,	0x00	},
	{	XFER_PIO_3,	0x33,	0x00	},
	{	XFER_PIO_2,	0x08,	0x00	},
	{	XFER_PIO_1,	0x0a,	0x00	},
	{	XFER_PIO_0,	0x00,	0x00	},
	{	0,		0x00,	0x00	}
};

static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
	{	XFER_UDMA_6,	0x41,	0x06	},
	{	XFER_UDMA_5,	0x41,	0x05	},
	{	XFER_UDMA_4,	0x41,	0x04	},
	{	XFER_UDMA_3,	0x41,	0x03	},
	{	XFER_UDMA_2,	0x41,	0x02	},
	{	XFER_UDMA_1,	0x41,	0x01	},
	{	XFER_UDMA_0,	0x41,	0x01	},

	{	XFER_MW_DMA_2,	0x41,	0x00	},
	{	XFER_MW_DMA_1,	0x42,	0x00	},
	{	XFER_MW_DMA_0,	0x7a,	0x00	},
	{	XFER_PIO_4,	0x41,	0x00	},
	{	XFER_PIO_3,	0x43,	0x00	},
	{	XFER_PIO_2,	0x78,	0x00	},
	{	XFER_PIO_1,	0x7a,	0x00	},
	{	XFER_PIO_0,	0x70,	0x00	},
	{	0,		0x00,	0x00	}
};

/*
 * TO DO: active tuning and correction of cards without a bios.
 */
static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
{
	for ( ; chipset_table->xfer_speed ; chipset_table++)
		if (chipset_table->xfer_speed == speed) {
			return chipset_table->chipset_settings;
		}
	return chipset_table->chipset_settings;
}

static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
{
	for ( ; chipset_table->xfer_speed ; chipset_table++)
		if (chipset_table->xfer_speed == speed) {
			return chipset_table->ultra_settings;
		}
	return chipset_table->ultra_settings;
}

static void aec6210_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	struct ide_host *host	= pci_get_drvdata(dev);
	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
	u16 d_conf		= 0;
	u8 ultra = 0, ultra_conf = 0;
	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
	unsigned long flags;

	local_irq_save(flags);
	/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
	pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
	tmp0 = pci_bus_clock_list(speed, bus_clock);
	d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
	pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);

	tmp1 = 0x00;
	tmp2 = 0x00;
	pci_read_config_byte(dev, 0x54, &ultra);
	tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
	tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
	pci_write_config_byte(dev, 0x54, tmp2);
	local_irq_restore(flags);
}

static void aec6260_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	struct ide_host *host	= pci_get_drvdata(dev);
	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
	u8 unit		= (drive->select.b.unit & 0x01);
	u8 tmp1 = 0, tmp2 = 0;
	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
	unsigned long flags;

	local_irq_save(flags);
	/* high 4-bits: Active, low 4-bits: Recovery */
	pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
	drive_conf = pci_bus_clock_list(speed, bus_clock);
	pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);

	pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
	tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
	tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
	pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
	local_irq_restore(flags);
}

static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	drive->hwif->port_ops->set_dma_mode(drive, pio + XFER_PIO_0);
}

static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
{
	/* These are necessary to get AEC6280 Macintosh cards to work */
	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
	    (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
		u8 reg49h = 0, reg4ah = 0;
		/* Clear reset and test bits.  */
		pci_read_config_byte(dev, 0x49, &reg49h);
		pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
		/* Enable chip interrupt output.  */
		pci_read_config_byte(dev, 0x4a, &reg4ah);
		pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
		/* Enable burst mode. */
		pci_read_config_byte(dev, 0x4a, &reg4ah);
		pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
	}

	return dev->irq;
}

static u8 __devinit atp86x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;

	pci_read_config_byte(dev, 0x49, &ata66);

	return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

static const struct ide_port_ops atp850_port_ops = {
	.set_pio_mode		= aec_set_pio_mode,
	.set_dma_mode		= aec6210_set_mode,
};

static const struct ide_port_ops atp86x_port_ops = {
	.set_pio_mode		= aec_set_pio_mode,
	.set_dma_mode		= aec6260_set_mode,
	.cable_detect		= atp86x_cable_detect,
};

static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "AEC6210",
		.init_chipset	= init_chipset_aec62xx,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.port_ops	= &atp850_port_ops,
		.host_flags	= IDE_HFLAG_SERIALIZE |
				  IDE_HFLAG_NO_ATAPI_DMA |
				  IDE_HFLAG_NO_DSC |
				  IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},{	/* 1 */
		.name		= "AEC6260",
		.init_chipset	= init_chipset_aec62xx,
		.port_ops	= &atp86x_port_ops,
		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
				  IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA4,
	},{	/* 2 */
		.name		= "AEC6260R",
		.init_chipset	= init_chipset_aec62xx,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.port_ops	= &atp86x_port_ops,
		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
				  IDE_HFLAG_NON_BOOTABLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA4,
	},{	/* 3 */
		.name		= "AEC6280",
		.init_chipset	= init_chipset_aec62xx,
		.port_ops	= &atp86x_port_ops,
		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
				  IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},{	/* 4 */
		.name		= "AEC6280R",
		.init_chipset	= init_chipset_aec62xx,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.port_ops	= &atp86x_port_ops,
		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
				  IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	}
};

/**
 *	aec62xx_init_one	-	called when a AEC is found
 *	@dev: the aec62xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 *
 *	NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
 *	chips, pass a local copy of 'struct ide_port_info' down the call chain.
 */

static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct chipset_bus_clock_list_entry *bus_clock;
	struct ide_port_info d;
	u8 idx = id->driver_data;
	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
	int err;

	if (bus_speed <= 33)
		bus_clock = aec6xxx_33_base;
	else
		bus_clock = aec6xxx_34_base;

	err = pci_enable_device(dev);
	if (err)
		return err;

	d = aec62xx_chipsets[idx];

	if (idx == 3 || idx == 4) {
		unsigned long dma_base = pci_resource_start(dev, 4);

		if (inb(dma_base + 2) & 0x10) {
			d.name = (idx == 4) ? "AEC6880R" : "AEC6880";
			d.udma_mask = ATA_UDMA6;
		}
	}

	err = ide_pci_init_one(dev, &d, (void *)bus_clock);
	if (err)
		pci_disable_device(dev);

	return err;
}

static const struct pci_device_id aec62xx_pci_tbl[] = {
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860),   1 },
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R),  2 },
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865),   3 },
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R),  4 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "AEC62xx_IDE",
	.id_table	= aec62xx_pci_tbl,
	.probe		= aec62xx_init_one,
};

static int __init aec62xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(aec62xx_ide_init);

MODULE_AUTHOR("Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
826a1b65	3	* Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	4	*
	5	*/
	6
	7	#include <linux/module.h>
1da177e4 LT	8	#include <linux/types.h>
1da177e4 LT	9	#include <linux/pci.h>
1da177e4 LT	10	#include <linux/hdreg.h>
	11	#include <linux/ide.h>
	12	#include <linux/init.h>
	13
	14	#include <asm/io.h>
	15
	16	struct chipset_bus_clock_list_entry {
	17	u8 xfer_speed;
	18	u8 chipset_settings;
	19	u8 ultra_settings;
	20	};
	21
f201f504	22	static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
1da177e4 LT	23	{ XFER_UDMA_6, 0x31, 0x07 },
	24	{ XFER_UDMA_5, 0x31, 0x06 },
	25	{ XFER_UDMA_4, 0x31, 0x05 },
	26	{ XFER_UDMA_3, 0x31, 0x04 },
	27	{ XFER_UDMA_2, 0x31, 0x03 },
	28	{ XFER_UDMA_1, 0x31, 0x02 },
	29	{ XFER_UDMA_0, 0x31, 0x01 },
	30
	31	{ XFER_MW_DMA_2, 0x31, 0x00 },
	32	{ XFER_MW_DMA_1, 0x31, 0x00 },
	33	{ XFER_MW_DMA_0, 0x0a, 0x00 },
	34	{ XFER_PIO_4, 0x31, 0x00 },
	35	{ XFER_PIO_3, 0x33, 0x00 },
	36	{ XFER_PIO_2, 0x08, 0x00 },
	37	{ XFER_PIO_1, 0x0a, 0x00 },
	38	{ XFER_PIO_0, 0x00, 0x00 },
	39	{ 0, 0x00, 0x00 }
	40	};
	41
f201f504	42	static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
1da177e4 LT	43	{ XFER_UDMA_6, 0x41, 0x06 },
	44	{ XFER_UDMA_5, 0x41, 0x05 },
	45	{ XFER_UDMA_4, 0x41, 0x04 },
	46	{ XFER_UDMA_3, 0x41, 0x03 },
	47	{ XFER_UDMA_2, 0x41, 0x02 },
	48	{ XFER_UDMA_1, 0x41, 0x01 },
	49	{ XFER_UDMA_0, 0x41, 0x01 },
	50
	51	{ XFER_MW_DMA_2, 0x41, 0x00 },
	52	{ XFER_MW_DMA_1, 0x42, 0x00 },
	53	{ XFER_MW_DMA_0, 0x7a, 0x00 },
	54	{ XFER_PIO_4, 0x41, 0x00 },
	55	{ XFER_PIO_3, 0x43, 0x00 },
	56	{ XFER_PIO_2, 0x78, 0x00 },
	57	{ XFER_PIO_1, 0x7a, 0x00 },
	58	{ XFER_PIO_0, 0x70, 0x00 },
	59	{ 0, 0x00, 0x00 }
	60	};
	61
1da177e4 LT	62	/*
	63	* TO DO: active tuning and correction of cards without a bios.
	64	*/
	65	static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
	66	{
	67	for ( ; chipset_table->xfer_speed ; chipset_table++)
	68	if (chipset_table->xfer_speed == speed) {
	69	return chipset_table->chipset_settings;
	70	}
	71	return chipset_table->chipset_settings;
	72	}
	73
	74	static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
	75	{
	76	for ( ; chipset_table->xfer_speed ; chipset_table++)
	77	if (chipset_table->xfer_speed == speed) {
	78	return chipset_table->ultra_settings;
	79	}
	80	return chipset_table->ultra_settings;
	81	}
	82
88b2b32b	83	static void aec6210_set_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	84	{
1da177e4 LT	85	ide_hwif_t *hwif = HWIF(drive);
36501650	86	struct pci_dev *dev = to_pci_dev(hwif->dev);
60e57ed7 BZ	87	struct ide_host *host = pci_get_drvdata(dev);
60e57ed7 BZ	88	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
1da177e4	89	u16 d_conf = 0;
1da177e4 LT	90	u8 ultra = 0, ultra_conf = 0;
	91	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
	92	unsigned long flags;
	93
	94	local_irq_save(flags);
	95	/* 0x40\|(2drive->dn): Active, 0x41\|(2drive->dn): Recovery */
	96	pci_read_config_word(dev, 0x40\|(2*drive->dn), &d_conf);
60e57ed7	97	tmp0 = pci_bus_clock_list(speed, bus_clock);
1da177e4 LT	98	d_conf = ((tmp0 & 0xf0) << 4) \| (tmp0 & 0xf);
	99	pci_write_config_word(dev, 0x40\|(2*drive->dn), d_conf);
	100
	101	tmp1 = 0x00;
	102	tmp2 = 0x00;
	103	pci_read_config_byte(dev, 0x54, &ultra);
	104	tmp1 = ((0x00 << (2drive->dn)) \| (ultra & ~(3 << (2drive->dn))));
60e57ed7	105	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
1da177e4 LT	106	tmp2 = ((ultra_conf << (2drive->dn)) \| (tmp1 & ~(3 << (2drive->dn))));
	107	pci_write_config_byte(dev, 0x54, tmp2);
	108	local_irq_restore(flags);
1da177e4 LT	109	}
1da177e4 LT	110
88b2b32b	111	static void aec6260_set_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	112	{
1da177e4 LT	113	ide_hwif_t *hwif = HWIF(drive);
36501650	114	struct pci_dev *dev = to_pci_dev(hwif->dev);
60e57ed7 BZ	115	struct ide_host *host = pci_get_drvdata(dev);
60e57ed7 BZ	116	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
1da177e4 LT	117	u8 unit = (drive->select.b.unit & 0x01);
	118	u8 tmp1 = 0, tmp2 = 0;
	119	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
	120	unsigned long flags;
	121
	122	local_irq_save(flags);
	123	/* high 4-bits: Active, low 4-bits: Recovery */
	124	pci_read_config_byte(dev, 0x40\|drive->dn, &drive_conf);
60e57ed7	125	drive_conf = pci_bus_clock_list(speed, bus_clock);
1da177e4 LT	126	pci_write_config_byte(dev, 0x40\|drive->dn, drive_conf);
	127
	128	pci_read_config_byte(dev, (0x44\|hwif->channel), &ultra);
	129	tmp1 = ((0x00 << (4unit)) \| (ultra & ~(7 << (4unit))));
60e57ed7	130	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
1da177e4 LT	131	tmp2 = ((ultra_conf << (4unit)) \| (tmp1 & ~(7 << (4unit))));
	132	pci_write_config_byte(dev, (0x44\|hwif->channel), tmp2);
	133	local_irq_restore(flags);
1da177e4 LT	134	}
1da177e4 LT	135
26bcb879	136	static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	137	{
ac95beed	138	drive->hwif->port_ops->set_dma_mode(drive, pio + XFER_PIO_0);
1da177e4 LT	139	}
1da177e4 LT	140
1da177e4 LT	141	static unsigned int __devinit init_chipset_aec62xx(struct pci_dev dev, const char name)
1da177e4 LT	142	{
d237bf49 TV	143	/* These are necessary to get AEC6280 Macintosh cards to work */
	144	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) \|\|
	145	(dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
	146	u8 reg49h = 0, reg4ah = 0;
	147	/* Clear reset and test bits. */
	148	pci_read_config_byte(dev, 0x49, &reg49h);
	149	pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
	150	/* Enable chip interrupt output. */
	151	pci_read_config_byte(dev, 0x4a, &reg4ah);
	152	pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
	153	/* Enable burst mode. */
	154	pci_read_config_byte(dev, 0x4a, &reg4ah);
	155	pci_write_config_byte(dev, 0x4a, reg4ah \| 0x80);
	156	}
	157
1da177e4 LT	158	return dev->irq;
	159	}
	160
bfa14b42 BZ	161	static u8 __devinit atp86x_cable_detect(ide_hwif_t *hwif)
	162	{
	163	struct pci_dev *dev = to_pci_dev(hwif->dev);
	164	u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
	165
	166	pci_read_config_byte(dev, 0x49, &ata66);
	167
	168	return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
	169	}
	170
ac95beed BZ	171	static const struct ide_port_ops atp850_port_ops = {
	172	.set_pio_mode = aec_set_pio_mode,
	173	.set_dma_mode = aec6210_set_mode,
	174	};
1da177e4	175
ac95beed BZ	176	static const struct ide_port_ops atp86x_port_ops = {
	177	.set_pio_mode = aec_set_pio_mode,
	178	.set_dma_mode = aec6260_set_mode,
	179	.cable_detect = atp86x_cable_detect,
	180	};
1da177e4	181
85620436	182	static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
1da177e4 LT	183	{ /* 0 */
1da177e4 LT	184	.name = "AEC6210",
1da177e4	185	.init_chipset = init_chipset_aec62xx,
1da177e4	186	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
ac95beed	187	.port_ops = &atp850_port_ops,
1c51361a BZ	188	.host_flags = IDE_HFLAG_SERIALIZE \|
1c51361a BZ	189	IDE_HFLAG_NO_ATAPI_DMA \|
4166c199	190	IDE_HFLAG_NO_DSC \|
1c51361a	191	IDE_HFLAG_OFF_BOARD,
4099d143	192	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	193	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	194	.udma_mask = ATA_UDMA2,
1da177e4 LT	195	},{ /* 1 */
1da177e4 LT	196	.name = "AEC6260",
1da177e4	197	.init_chipset = init_chipset_aec62xx,
ac95beed	198	.port_ops = &atp86x_port_ops,
47b68788 BZ	199	.host_flags = IDE_HFLAG_NO_ATAPI_DMA \| IDE_HFLAG_NO_AUTODMA \|
47b68788 BZ	200	IDE_HFLAG_OFF_BOARD,
4099d143	201	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	202	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	203	.udma_mask = ATA_UDMA4,
1da177e4 LT	204	},{ /* 2 */
1da177e4 LT	205	.name = "AEC6260R",
1da177e4	206	.init_chipset = init_chipset_aec62xx,
1da177e4	207	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
ac95beed	208	.port_ops = &atp86x_port_ops,
4db90a14	209	.host_flags = IDE_HFLAG_NO_ATAPI_DMA \|
5e71d9c5	210	IDE_HFLAG_NON_BOOTABLE,
4099d143	211	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	212	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	213	.udma_mask = ATA_UDMA4,
1da177e4	214	},{ /* 3 */
b1d19db4	215	.name = "AEC6280",
1da177e4	216	.init_chipset = init_chipset_aec62xx,
ac95beed	217	.port_ops = &atp86x_port_ops,
4db90a14	218	.host_flags = IDE_HFLAG_NO_ATAPI_DMA \|
4db90a14	219	IDE_HFLAG_OFF_BOARD,
4099d143	220	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	221	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	222	.udma_mask = ATA_UDMA5,
1da177e4	223	},{ /* 4 */
b1d19db4	224	.name = "AEC6280R",
1da177e4	225	.init_chipset = init_chipset_aec62xx,
1da177e4	226	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
ac95beed	227	.port_ops = &atp86x_port_ops,
4db90a14	228	.host_flags = IDE_HFLAG_NO_ATAPI_DMA \|
4db90a14	229	IDE_HFLAG_OFF_BOARD,
4099d143	230	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	231	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	232	.udma_mask = ATA_UDMA5,
1da177e4 LT	233	}
	234	};
	235
	236	/**
	237	* aec62xx_init_one - called when a AEC is found
	238	* @dev: the aec62xx device
	239	* @id: the matching pci id
	240	*
	241	* Called when the PCI registration layer (or the IDE initialization)
	242	* finds a device matching our IDE device tables.
b1d19db4 SS	243	*
b1d19db4 SS	244	* NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
039788e1	245	* chips, pass a local copy of 'struct ide_port_info' down the call chain.
1da177e4	246	*/
039788e1	247
1da177e4 LT	248	static int __devinit aec62xx_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4 LT	249	{
60e57ed7	250	const struct chipset_bus_clock_list_entry *bus_clock;
039788e1	251	struct ide_port_info d;
df95f5ab	252	u8 idx = id->driver_data;
60e57ed7	253	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
b48d0817 AR	254	int err;
b48d0817 AR	255
60e57ed7 BZ	256	if (bus_speed <= 33)
	257	bus_clock = aec6xxx_33_base;
	258	else
	259	bus_clock = aec6xxx_34_base;
	260
b48d0817 AR	261	err = pci_enable_device(dev);
	262	if (err)
	263	return err;
df95f5ab BZ	264
	265	d = aec62xx_chipsets[idx];
	266
	267	if (idx == 3 \|\| idx == 4) {
	268	unsigned long dma_base = pci_resource_start(dev, 4);
	269
	270	if (inb(dma_base + 2) & 0x10) {
	271	d.name = (idx == 4) ? "AEC6880R" : "AEC6880";
	272	d.udma_mask = ATA_UDMA6;
	273	}
	274	}
1da177e4	275
60e57ed7	276	err = ide_pci_init_one(dev, &d, (void *)bus_clock);
b48d0817 AR	277	if (err)
	278	pci_disable_device(dev);
	279
	280	return err;
1da177e4 LT	281	}
1da177e4 LT	282
9cbcc5e3 BZ	283	static const struct pci_device_id aec62xx_pci_tbl[] = {
	284	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
	285	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860), 1 },
	286	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R), 2 },
	287	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865), 3 },
	288	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R), 4 },
1da177e4 LT	289	{ 0, },
	290	};
	291	MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
	292
	293	static struct pci_driver driver = {
	294	.name = "AEC62xx_IDE",
	295	.id_table = aec62xx_pci_tbl,
	296	.probe = aec62xx_init_one,
	297	};
	298
82ab1eec	299	static int __init aec62xx_ide_init(void)
1da177e4 LT	300	{
	301	return ide_pci_register_driver(&driver);
	302	}
	303
	304	module_init(aec62xx_ide_init);
	305
	306	MODULE_AUTHOR("Andre Hedrick");
	307	MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
	308	MODULE_LICENSE("GPL");