]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Version 2.13 | |
3 | * | |
4 | * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04 | |
5 | * IDE driver for Linux. | |
6 | * | |
7 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
8 | * | |
9 | * Based on the work of: | |
10 | * Andre Hedrick | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This program is free software; you can redistribute it and/or modify it | |
15 | * under the terms of the GNU General Public License version 2 as published by | |
16 | * the Free Software Foundation. | |
17 | */ | |
18 | ||
19 | #include <linux/config.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/ide.h> | |
27 | #include <asm/io.h> | |
28 | ||
29 | #include "ide-timing.h" | |
30 | ||
31 | #define DISPLAY_AMD_TIMINGS | |
32 | ||
33 | #define AMD_IDE_ENABLE (0x00 + amd_config->base) | |
34 | #define AMD_IDE_CONFIG (0x01 + amd_config->base) | |
35 | #define AMD_CABLE_DETECT (0x02 + amd_config->base) | |
36 | #define AMD_DRIVE_TIMING (0x08 + amd_config->base) | |
37 | #define AMD_8BIT_TIMING (0x0e + amd_config->base) | |
38 | #define AMD_ADDRESS_SETUP (0x0c + amd_config->base) | |
39 | #define AMD_UDMA_TIMING (0x10 + amd_config->base) | |
40 | ||
41 | #define AMD_UDMA 0x07 | |
42 | #define AMD_UDMA_33 0x01 | |
43 | #define AMD_UDMA_66 0x02 | |
44 | #define AMD_UDMA_100 0x03 | |
45 | #define AMD_UDMA_133 0x04 | |
46 | #define AMD_CHECK_SWDMA 0x08 | |
47 | #define AMD_BAD_SWDMA 0x10 | |
48 | #define AMD_BAD_FIFO 0x20 | |
49 | #define AMD_CHECK_SERENADE 0x40 | |
50 | ||
51 | /* | |
52 | * AMD SouthBridge chips. | |
53 | */ | |
54 | ||
55 | static struct amd_ide_chip { | |
56 | unsigned short id; | |
57 | unsigned long base; | |
58 | unsigned char flags; | |
59 | } amd_ide_chips[] = { | |
60 | { PCI_DEVICE_ID_AMD_COBRA_7401, 0x40, AMD_UDMA_33 | AMD_BAD_SWDMA }, | |
61 | { PCI_DEVICE_ID_AMD_VIPER_7409, 0x40, AMD_UDMA_66 | AMD_CHECK_SWDMA }, | |
62 | { PCI_DEVICE_ID_AMD_VIPER_7411, 0x40, AMD_UDMA_100 | AMD_BAD_FIFO }, | |
63 | { PCI_DEVICE_ID_AMD_OPUS_7441, 0x40, AMD_UDMA_100 }, | |
64 | { PCI_DEVICE_ID_AMD_8111_IDE, 0x40, AMD_UDMA_133 | AMD_CHECK_SERENADE }, | |
65 | { PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x50, AMD_UDMA_100 }, | |
66 | { PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x50, AMD_UDMA_133 }, | |
67 | { PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, 0x50, AMD_UDMA_133 }, | |
68 | { PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, 0x50, AMD_UDMA_133 }, | |
69 | { PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, 0x50, AMD_UDMA_133 }, | |
70 | { PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, 0x50, AMD_UDMA_133 }, | |
71 | { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, 0x50, AMD_UDMA_133 }, | |
72 | { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, 0x50, AMD_UDMA_133 }, | |
73 | { PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, 0x50, AMD_UDMA_133 }, | |
74 | { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, 0x50, AMD_UDMA_133 }, | |
75 | { 0 } | |
76 | }; | |
77 | ||
78 | static struct amd_ide_chip *amd_config; | |
79 | static ide_pci_device_t *amd_chipset; | |
80 | static unsigned int amd_80w; | |
81 | static unsigned int amd_clock; | |
82 | ||
83 | static char *amd_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" }; | |
84 | static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 }; | |
85 | ||
86 | /* | |
87 | * AMD /proc entry. | |
88 | */ | |
89 | ||
90 | #ifdef CONFIG_PROC_FS | |
91 | ||
92 | #include <linux/stat.h> | |
93 | #include <linux/proc_fs.h> | |
94 | ||
95 | static u8 amd74xx_proc; | |
96 | ||
97 | static unsigned char amd_udma2cyc[] = { 4, 6, 8, 10, 3, 2, 1, 15 }; | |
98 | static unsigned long amd_base; | |
99 | static struct pci_dev *bmide_dev; | |
100 | extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */ | |
101 | ||
102 | #define amd_print(format, arg...) p += sprintf(p, format "\n" , ## arg) | |
103 | #define amd_print_drive(name, format, arg...)\ | |
104 | p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n"); | |
105 | ||
106 | static int amd74xx_get_info(char *buffer, char **addr, off_t offset, int count) | |
107 | { | |
108 | int speed[4], cycle[4], setup[4], active[4], recover[4], den[4], | |
109 | uen[4], udma[4], active8b[4], recover8b[4]; | |
110 | struct pci_dev *dev = bmide_dev; | |
111 | unsigned int v, u, i; | |
112 | unsigned short c, w; | |
113 | unsigned char t; | |
114 | int len; | |
115 | char *p = buffer; | |
116 | ||
117 | amd_print("----------AMD BusMastering IDE Configuration----------------"); | |
118 | ||
119 | amd_print("Driver Version: 2.13"); | |
120 | amd_print("South Bridge: %s", pci_name(bmide_dev)); | |
121 | ||
122 | pci_read_config_byte(dev, PCI_REVISION_ID, &t); | |
123 | amd_print("Revision: IDE %#x", t); | |
124 | amd_print("Highest DMA rate: %s", amd_dma[amd_config->flags & AMD_UDMA]); | |
125 | ||
126 | amd_print("BM-DMA base: %#lx", amd_base); | |
127 | amd_print("PCI clock: %d.%dMHz", amd_clock / 1000, amd_clock / 100 % 10); | |
128 | ||
129 | amd_print("-----------------------Primary IDE-------Secondary IDE------"); | |
130 | ||
131 | pci_read_config_byte(dev, AMD_IDE_CONFIG, &t); | |
132 | amd_print("Prefetch Buffer: %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no"); | |
133 | amd_print("Post Write Buffer: %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no"); | |
134 | ||
135 | pci_read_config_byte(dev, AMD_IDE_ENABLE, &t); | |
136 | amd_print("Enabled: %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no"); | |
137 | ||
138 | c = inb(amd_base + 0x02) | (inb(amd_base + 0x0a) << 8); | |
139 | amd_print("Simplex only: %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no"); | |
140 | ||
141 | amd_print("Cable Type: %10s%20s", (amd_80w & 1) ? "80w" : "40w", (amd_80w & 2) ? "80w" : "40w"); | |
142 | ||
143 | if (!amd_clock) | |
144 | return p - buffer; | |
145 | ||
146 | amd_print("-------------------drive0----drive1----drive2----drive3-----"); | |
147 | ||
148 | pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t); | |
149 | pci_read_config_dword(dev, AMD_DRIVE_TIMING, &v); | |
150 | pci_read_config_word(dev, AMD_8BIT_TIMING, &w); | |
151 | pci_read_config_dword(dev, AMD_UDMA_TIMING, &u); | |
152 | ||
153 | for (i = 0; i < 4; i++) { | |
154 | setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1; | |
155 | recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1; | |
156 | active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1; | |
157 | active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1; | |
158 | recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1; | |
159 | ||
160 | udma[i] = amd_udma2cyc[((u >> ((3 - i) << 3)) & 0x7)]; | |
161 | uen[i] = ((u >> ((3 - i) << 3)) & 0x40) ? 1 : 0; | |
162 | den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2)); | |
163 | ||
164 | if (den[i] && uen[i] && udma[i] == 1) { | |
165 | speed[i] = amd_clock * 3; | |
166 | cycle[i] = 666666 / amd_clock; | |
167 | continue; | |
168 | } | |
169 | ||
170 | if (den[i] && uen[i] && udma[i] == 15) { | |
171 | speed[i] = amd_clock * 4; | |
172 | cycle[i] = 500000 / amd_clock; | |
173 | continue; | |
174 | } | |
175 | ||
176 | speed[i] = 4 * amd_clock / ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2); | |
177 | cycle[i] = 1000000 * ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2) / amd_clock / 2; | |
178 | } | |
179 | ||
180 | amd_print_drive("Transfer Mode: ", "%10s", den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO"); | |
181 | ||
182 | amd_print_drive("Address Setup: ", "%8dns", 1000000 * setup[i] / amd_clock); | |
183 | amd_print_drive("Cmd Active: ", "%8dns", 1000000 * active8b[i] / amd_clock); | |
184 | amd_print_drive("Cmd Recovery: ", "%8dns", 1000000 * recover8b[i] / amd_clock); | |
185 | amd_print_drive("Data Active: ", "%8dns", 1000000 * active[i] / amd_clock); | |
186 | amd_print_drive("Data Recovery: ", "%8dns", 1000000 * recover[i] / amd_clock); | |
187 | amd_print_drive("Cycle Time: ", "%8dns", cycle[i]); | |
188 | amd_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10); | |
189 | ||
190 | /* hoping p - buffer is less than 4K... */ | |
191 | len = (p - buffer) - offset; | |
192 | *addr = buffer + offset; | |
193 | ||
194 | return len > count ? count : len; | |
195 | } | |
196 | ||
197 | #endif | |
198 | ||
199 | /* | |
200 | * amd_set_speed() writes timing values to the chipset registers | |
201 | */ | |
202 | ||
203 | static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing) | |
204 | { | |
205 | unsigned char t; | |
206 | ||
207 | pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t); | |
208 | t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); | |
209 | pci_write_config_byte(dev, AMD_ADDRESS_SETUP, t); | |
210 | ||
211 | pci_write_config_byte(dev, AMD_8BIT_TIMING + (1 - (dn >> 1)), | |
212 | ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1)); | |
213 | ||
214 | pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn), | |
215 | ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1)); | |
216 | ||
217 | switch (amd_config->flags & AMD_UDMA) { | |
218 | case AMD_UDMA_33: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break; | |
219 | case AMD_UDMA_66: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break; | |
220 | case AMD_UDMA_100: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break; | |
221 | case AMD_UDMA_133: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break; | |
222 | default: return; | |
223 | } | |
224 | ||
225 | pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t); | |
226 | } | |
227 | ||
228 | /* | |
229 | * amd_set_drive() computes timing values configures the drive and | |
230 | * the chipset to a desired transfer mode. It also can be called | |
231 | * by upper layers. | |
232 | */ | |
233 | ||
234 | static int amd_set_drive(ide_drive_t *drive, u8 speed) | |
235 | { | |
236 | ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1); | |
237 | struct ide_timing t, p; | |
238 | int T, UT; | |
239 | ||
240 | if (speed != XFER_PIO_SLOW && speed != drive->current_speed) | |
241 | if (ide_config_drive_speed(drive, speed)) | |
242 | printk(KERN_WARNING "ide%d: Drive %d didn't accept speed setting. Oh, well.\n", | |
243 | drive->dn >> 1, drive->dn & 1); | |
244 | ||
245 | T = 1000000000 / amd_clock; | |
246 | UT = T / min_t(int, max_t(int, amd_config->flags & AMD_UDMA, 1), 2); | |
247 | ||
248 | ide_timing_compute(drive, speed, &t, T, UT); | |
249 | ||
250 | if (peer->present) { | |
251 | ide_timing_compute(peer, peer->current_speed, &p, T, UT); | |
252 | ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); | |
253 | } | |
254 | ||
255 | if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1; | |
256 | if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15; | |
257 | ||
258 | amd_set_speed(HWIF(drive)->pci_dev, drive->dn, &t); | |
259 | ||
260 | if (!drive->init_speed) | |
261 | drive->init_speed = speed; | |
262 | drive->current_speed = speed; | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
267 | /* | |
268 | * amd74xx_tune_drive() is a callback from upper layers for | |
269 | * PIO-only tuning. | |
270 | */ | |
271 | ||
272 | static void amd74xx_tune_drive(ide_drive_t *drive, u8 pio) | |
273 | { | |
274 | if (pio == 255) { | |
275 | amd_set_drive(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO)); | |
276 | return; | |
277 | } | |
278 | ||
279 | amd_set_drive(drive, XFER_PIO_0 + min_t(byte, pio, 5)); | |
280 | } | |
281 | ||
282 | /* | |
283 | * amd74xx_dmaproc() is a callback from upper layers that can do | |
284 | * a lot, but we use it for DMA/PIO tuning only, delegating everything | |
285 | * else to the default ide_dmaproc(). | |
286 | */ | |
287 | ||
288 | static int amd74xx_ide_dma_check(ide_drive_t *drive) | |
289 | { | |
290 | int w80 = HWIF(drive)->udma_four; | |
291 | ||
292 | u8 speed = ide_find_best_mode(drive, | |
293 | XFER_PIO | XFER_EPIO | XFER_MWDMA | XFER_UDMA | | |
294 | ((amd_config->flags & AMD_BAD_SWDMA) ? 0 : XFER_SWDMA) | | |
295 | (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_66 ? XFER_UDMA_66 : 0) | | |
296 | (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_100 ? XFER_UDMA_100 : 0) | | |
297 | (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_133 ? XFER_UDMA_133 : 0)); | |
298 | ||
299 | amd_set_drive(drive, speed); | |
300 | ||
301 | if (drive->autodma && (speed & XFER_MODE) != XFER_PIO) | |
302 | return HWIF(drive)->ide_dma_on(drive); | |
303 | return HWIF(drive)->ide_dma_off_quietly(drive); | |
304 | } | |
305 | ||
306 | /* | |
307 | * The initialization callback. Here we determine the IDE chip type | |
308 | * and initialize its drive independent registers. | |
309 | */ | |
310 | ||
311 | static unsigned int __init init_chipset_amd74xx(struct pci_dev *dev, const char *name) | |
312 | { | |
313 | unsigned char t; | |
314 | unsigned int u; | |
315 | int i; | |
316 | ||
317 | /* | |
318 | * Check for bad SWDMA. | |
319 | */ | |
320 | ||
321 | if (amd_config->flags & AMD_CHECK_SWDMA) { | |
322 | pci_read_config_byte(dev, PCI_REVISION_ID, &t); | |
323 | if (t <= 7) | |
324 | amd_config->flags |= AMD_BAD_SWDMA; | |
325 | } | |
326 | ||
327 | /* | |
328 | * Check 80-wire cable presence. | |
329 | */ | |
330 | ||
331 | switch (amd_config->flags & AMD_UDMA) { | |
332 | ||
333 | case AMD_UDMA_133: | |
334 | case AMD_UDMA_100: | |
335 | pci_read_config_byte(dev, AMD_CABLE_DETECT, &t); | |
336 | pci_read_config_dword(dev, AMD_UDMA_TIMING, &u); | |
337 | amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0); | |
338 | for (i = 24; i >= 0; i -= 8) | |
339 | if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) { | |
340 | printk(KERN_WARNING "%s: BIOS didn't set cable bits correctly. Enabling workaround.\n", | |
341 | amd_chipset->name); | |
342 | amd_80w |= (1 << (1 - (i >> 4))); | |
343 | } | |
344 | break; | |
345 | ||
346 | case AMD_UDMA_66: | |
347 | pci_read_config_dword(dev, AMD_UDMA_TIMING, &u); | |
348 | for (i = 24; i >= 0; i -= 8) | |
349 | if ((u >> i) & 4) | |
350 | amd_80w |= (1 << (1 - (i >> 4))); | |
351 | break; | |
352 | } | |
353 | ||
354 | /* | |
355 | * Take care of prefetch & postwrite. | |
356 | */ | |
357 | ||
358 | pci_read_config_byte(dev, AMD_IDE_CONFIG, &t); | |
359 | pci_write_config_byte(dev, AMD_IDE_CONFIG, | |
360 | (amd_config->flags & AMD_BAD_FIFO) ? (t & 0x0f) : (t | 0xf0)); | |
361 | ||
362 | /* | |
363 | * Take care of incorrectly wired Serenade mainboards. | |
364 | */ | |
365 | ||
366 | if ((amd_config->flags & AMD_CHECK_SERENADE) && | |
367 | dev->subsystem_vendor == PCI_VENDOR_ID_AMD && | |
368 | dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE) | |
369 | amd_config->flags = AMD_UDMA_100; | |
370 | ||
371 | /* | |
372 | * Determine the system bus clock. | |
373 | */ | |
374 | ||
375 | amd_clock = system_bus_clock() * 1000; | |
376 | ||
377 | switch (amd_clock) { | |
378 | case 33000: amd_clock = 33333; break; | |
379 | case 37000: amd_clock = 37500; break; | |
380 | case 41000: amd_clock = 41666; break; | |
381 | } | |
382 | ||
383 | if (amd_clock < 20000 || amd_clock > 50000) { | |
384 | printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n", | |
385 | amd_chipset->name, amd_clock); | |
386 | printk(KERN_WARNING "%s: Use ide0=ata66 if you want to assume 80-wire cable\n", | |
387 | amd_chipset->name); | |
388 | amd_clock = 33333; | |
389 | } | |
390 | ||
391 | /* | |
392 | * Print the boot message. | |
393 | */ | |
394 | ||
395 | pci_read_config_byte(dev, PCI_REVISION_ID, &t); | |
396 | printk(KERN_INFO "%s: %s (rev %02x) %s controller\n", | |
397 | amd_chipset->name, pci_name(dev), t, amd_dma[amd_config->flags & AMD_UDMA]); | |
398 | ||
399 | /* | |
400 | * Register /proc/ide/amd74xx entry | |
401 | */ | |
402 | ||
403 | #if defined(DISPLAY_AMD_TIMINGS) && defined(CONFIG_PROC_FS) | |
404 | if (!amd74xx_proc) { | |
405 | amd_base = pci_resource_start(dev, 4); | |
406 | bmide_dev = dev; | |
407 | ide_pci_create_host_proc("amd74xx", amd74xx_get_info); | |
408 | amd74xx_proc = 1; | |
409 | } | |
410 | #endif /* DISPLAY_AMD_TIMINGS && CONFIG_PROC_FS */ | |
411 | ||
412 | return dev->irq; | |
413 | } | |
414 | ||
415 | static void __init init_hwif_amd74xx(ide_hwif_t *hwif) | |
416 | { | |
417 | int i; | |
418 | ||
419 | if (hwif->irq == 0) /* 0 is bogus but will do for now */ | |
420 | hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel); | |
421 | ||
422 | hwif->autodma = 0; | |
423 | ||
424 | hwif->tuneproc = &amd74xx_tune_drive; | |
425 | hwif->speedproc = &amd_set_drive; | |
426 | ||
427 | for (i = 0; i < 2; i++) { | |
428 | hwif->drives[i].io_32bit = 1; | |
429 | hwif->drives[i].unmask = 1; | |
430 | hwif->drives[i].autotune = 1; | |
431 | hwif->drives[i].dn = hwif->channel * 2 + i; | |
432 | } | |
433 | ||
434 | if (!hwif->dma_base) | |
435 | return; | |
436 | ||
437 | hwif->atapi_dma = 1; | |
438 | hwif->ultra_mask = 0x7f; | |
439 | hwif->mwdma_mask = 0x07; | |
440 | hwif->swdma_mask = 0x07; | |
441 | ||
442 | if (!hwif->udma_four) | |
443 | hwif->udma_four = (amd_80w >> hwif->channel) & 1; | |
444 | hwif->ide_dma_check = &amd74xx_ide_dma_check; | |
445 | if (!noautodma) | |
446 | hwif->autodma = 1; | |
447 | hwif->drives[0].autodma = hwif->autodma; | |
448 | hwif->drives[1].autodma = hwif->autodma; | |
449 | } | |
450 | ||
451 | #define DECLARE_AMD_DEV(name_str) \ | |
452 | { \ | |
453 | .name = name_str, \ | |
454 | .init_chipset = init_chipset_amd74xx, \ | |
455 | .init_hwif = init_hwif_amd74xx, \ | |
456 | .channels = 2, \ | |
457 | .autodma = AUTODMA, \ | |
458 | .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \ | |
459 | .bootable = ON_BOARD, \ | |
460 | } | |
461 | ||
462 | #define DECLARE_NV_DEV(name_str) \ | |
463 | { \ | |
464 | .name = name_str, \ | |
465 | .init_chipset = init_chipset_amd74xx, \ | |
466 | .init_hwif = init_hwif_amd74xx, \ | |
467 | .channels = 2, \ | |
468 | .autodma = AUTODMA, \ | |
469 | .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \ | |
470 | .bootable = ON_BOARD, \ | |
471 | } | |
472 | ||
473 | static ide_pci_device_t amd74xx_chipsets[] __devinitdata = { | |
474 | /* 0 */ DECLARE_AMD_DEV("AMD7401"), | |
475 | /* 1 */ DECLARE_AMD_DEV("AMD7409"), | |
476 | /* 2 */ DECLARE_AMD_DEV("AMD7411"), | |
477 | /* 3 */ DECLARE_AMD_DEV("AMD7441"), | |
478 | /* 4 */ DECLARE_AMD_DEV("AMD8111"), | |
479 | ||
480 | /* 5 */ DECLARE_NV_DEV("NFORCE"), | |
481 | /* 6 */ DECLARE_NV_DEV("NFORCE2"), | |
482 | /* 7 */ DECLARE_NV_DEV("NFORCE2-U400R"), | |
483 | /* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA"), | |
484 | /* 9 */ DECLARE_NV_DEV("NFORCE3-150"), | |
485 | /* 10 */ DECLARE_NV_DEV("NFORCE3-250"), | |
486 | /* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA"), | |
487 | /* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2"), | |
488 | /* 13 */ DECLARE_NV_DEV("NFORCE-CK804"), | |
489 | /* 14 */ DECLARE_NV_DEV("NFORCE-MCP04"), | |
490 | }; | |
491 | ||
492 | static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
493 | { | |
494 | amd_chipset = amd74xx_chipsets + id->driver_data; | |
495 | amd_config = amd_ide_chips + id->driver_data; | |
496 | if (dev->device != amd_config->id) { | |
497 | printk(KERN_ERR "%s: assertion 0x%02x == 0x%02x failed !\n", | |
498 | pci_name(dev), dev->device, amd_config->id); | |
499 | return -ENODEV; | |
500 | } | |
501 | return ide_setup_pci_device(dev, amd_chipset); | |
502 | } | |
503 | ||
504 | static struct pci_device_id amd74xx_pci_tbl[] = { | |
505 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
506 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, | |
507 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 }, | |
508 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 }, | |
509 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, | |
510 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 }, | |
511 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 }, | |
512 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 }, | |
513 | #ifdef CONFIG_BLK_DEV_IDE_SATA | |
514 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 }, | |
515 | #endif | |
516 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 }, | |
517 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10 }, | |
518 | #ifdef CONFIG_BLK_DEV_IDE_SATA | |
519 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11 }, | |
520 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12 }, | |
521 | #endif | |
522 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13 }, | |
523 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14 }, | |
524 | { 0, }, | |
525 | }; | |
526 | MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl); | |
527 | ||
528 | static struct pci_driver driver = { | |
529 | .name = "AMD_IDE", | |
530 | .id_table = amd74xx_pci_tbl, | |
531 | .probe = amd74xx_probe, | |
532 | }; | |
533 | ||
534 | static int amd74xx_ide_init(void) | |
535 | { | |
536 | return ide_pci_register_driver(&driver); | |
537 | } | |
538 | ||
539 | module_init(amd74xx_ide_init); | |
540 | ||
541 | MODULE_AUTHOR("Vojtech Pavlik"); | |
542 | MODULE_DESCRIPTION("AMD PCI IDE driver"); | |
543 | MODULE_LICENSE("GPL"); |