[mirror_ubuntu-zesty-kernel.git] / drivers / ide / pci / amd74xx.c

/*
 * Version 2.23
 *
 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
 * IDE driver for Linux.
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
 *
 * Based on the work of:
 *      Andre Hedrick
 */

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <asm/io.h>

#include "ide-timing.h"

#define DISPLAY_AMD_TIMINGS

#define AMD_IDE_ENABLE		(0x00 + amd_config->base)
#define AMD_IDE_CONFIG		(0x01 + amd_config->base)
#define AMD_CABLE_DETECT	(0x02 + amd_config->base)
#define AMD_DRIVE_TIMING	(0x08 + amd_config->base)
#define AMD_8BIT_TIMING		(0x0e + amd_config->base)
#define AMD_ADDRESS_SETUP	(0x0c + amd_config->base)
#define AMD_UDMA_TIMING		(0x10 + amd_config->base)

#define AMD_CHECK_SWDMA		0x08
#define AMD_BAD_SWDMA		0x10
#define AMD_BAD_FIFO		0x20
#define AMD_CHECK_SERENADE	0x40

/*
 * AMD SouthBridge chips.
 */

static struct amd_ide_chip {
	unsigned short id;
	u8 base;
	u8 udma_mask;
	u8 flags;
} amd_ide_chips[] = {
	{ PCI_DEVICE_ID_AMD_COBRA_7401,		 0x40, ATA_UDMA2, AMD_BAD_SWDMA },
	{ PCI_DEVICE_ID_AMD_VIPER_7409,		 0x40, ATA_UDMA4, AMD_CHECK_SWDMA },
	{ PCI_DEVICE_ID_AMD_VIPER_7411,		 0x40, ATA_UDMA5, AMD_BAD_FIFO },
	{ PCI_DEVICE_ID_AMD_OPUS_7441,		 0x40, ATA_UDMA5, },
	{ PCI_DEVICE_ID_AMD_8111_IDE,		 0x40, ATA_UDMA6, AMD_CHECK_SERENADE },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE_IDE,	 0x50, ATA_UDMA5, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE,	 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE,	 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,	 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE,	 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE,	 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,	 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,	 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE, 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE, 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE, 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE, 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE, 0x50, ATA_UDMA6, },
	{ PCI_DEVICE_ID_AMD_CS5536_IDE,		 0x40, ATA_UDMA5, },
	{ 0 }
};

static struct amd_ide_chip *amd_config;
static ide_pci_device_t *amd_chipset;
static unsigned int amd_80w;
static unsigned int amd_clock;

static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };

/*
 * AMD /proc entry.
 */

#ifdef CONFIG_IDE_PROC_FS

#include <linux/stat.h>
#include <linux/proc_fs.h>

static u8 amd74xx_proc;

static unsigned char amd_udma2cyc[] = { 4, 6, 8, 10, 3, 2, 1, 15 };
static unsigned long amd_base;
static struct pci_dev *bmide_dev;
extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */

#define amd_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
#define amd_print_drive(name, format, arg...)\
	p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");

static int amd74xx_get_info(char *buffer, char **addr, off_t offset, int count)
{
	int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
		 uen[4], udma[4], active8b[4], recover8b[4];
	struct pci_dev *dev = bmide_dev;
	unsigned int v, u, i;
	unsigned short c, w;
	unsigned char t;
	int len;
	char *p = buffer;

	amd_print("----------AMD BusMastering IDE Configuration----------------");

	amd_print("Driver Version:                     2.13");
	amd_print("South Bridge:                       %s", pci_name(bmide_dev));

	amd_print("Revision:                           IDE %#x", dev->revision);
	amd_print("Highest DMA rate:                   UDMA%s", amd_dma[fls(amd_config->udma_mask) - 1]);

	amd_print("BM-DMA base:                        %#lx", amd_base);
	amd_print("PCI clock:                          %d.%dMHz", amd_clock / 1000, amd_clock / 100 % 10);
	
	amd_print("-----------------------Primary IDE-------Secondary IDE------");

	pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
	amd_print("Prefetch Buffer:       %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
	amd_print("Post Write Buffer:     %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");

	pci_read_config_byte(dev, AMD_IDE_ENABLE, &t);
	amd_print("Enabled:               %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");

	c = inb(amd_base + 0x02) | (inb(amd_base + 0x0a) << 8);
	amd_print("Simplex only:          %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");

	amd_print("Cable Type:            %10s%20s", (amd_80w & 1) ? "80w" : "40w", (amd_80w & 2) ? "80w" : "40w");

	if (!amd_clock)
                return p - buffer;

	amd_print("-------------------drive0----drive1----drive2----drive3-----");

	pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
	pci_read_config_dword(dev, AMD_DRIVE_TIMING, &v);
	pci_read_config_word(dev, AMD_8BIT_TIMING, &w);
	pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);

	for (i = 0; i < 4; i++) {
		setup[i]     = ((t >> ((3 - i) << 1)) & 0x3) + 1;
		recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
		active8b[i]  = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
		active[i]    = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
		recover[i]   = ((v >> ((3 - i) << 3)) & 0xf) + 1;

		udma[i] = amd_udma2cyc[((u >> ((3 - i) << 3)) & 0x7)];
		uen[i]  = ((u >> ((3 - i) << 3)) & 0x40) ? 1 : 0;
		den[i]  = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));

		if (den[i] && uen[i] && udma[i] == 1) {
			speed[i] = amd_clock * 3;
			cycle[i] = 666666 / amd_clock;
			continue;
		}

		if (den[i] && uen[i] && udma[i] == 15) {
			speed[i] = amd_clock * 4;
			cycle[i] = 500000 / amd_clock;
			continue;
		}

		speed[i] = 4 * amd_clock / ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2);
		cycle[i] = 1000000 * ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2) / amd_clock / 2;
	}

	amd_print_drive("Transfer Mode: ", "%10s", den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");

	amd_print_drive("Address Setup: ", "%8dns", 1000000 * setup[i] / amd_clock);
	amd_print_drive("Cmd Active:    ", "%8dns", 1000000 * active8b[i] / amd_clock);
	amd_print_drive("Cmd Recovery:  ", "%8dns", 1000000 * recover8b[i] / amd_clock);
	amd_print_drive("Data Active:   ", "%8dns", 1000000 * active[i] / amd_clock);
	amd_print_drive("Data Recovery: ", "%8dns", 1000000 * recover[i] / amd_clock);
	amd_print_drive("Cycle Time:    ", "%8dns", cycle[i]);
	amd_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10);

	/* hoping p - buffer is less than 4K... */
	len = (p - buffer) - offset;
	*addr = buffer + offset;
	
	return len > count ? count : len;
}

#endif

/*
 * amd_set_speed() writes timing values to the chipset registers
 */

static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing)
{
	unsigned char t;

	pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
	t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
	pci_write_config_byte(dev, AMD_ADDRESS_SETUP, t);

	pci_write_config_byte(dev, AMD_8BIT_TIMING + (1 - (dn >> 1)),
		((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn),
		((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));

	switch (amd_config->udma_mask) {
	case ATA_UDMA2: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
	case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
	case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
	default: return;
	}

	pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t);
}

/*
 * amd_set_drive() computes timing values and configures the chipset
 * to a desired transfer mode.  It also can be called by upper layers.
 */

static void amd_set_drive(ide_drive_t *drive, const u8 speed)
{
	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
	struct ide_timing t, p;
	int T, UT;

	T = 1000000000 / amd_clock;
	UT = (amd_config->udma_mask == ATA_UDMA2) ? T : (T / 2);

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer->present) {
		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
	if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;

	amd_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
}

/*
 * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
 */

static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	amd_set_drive(drive, XFER_PIO_0 + pio);
}

/*
 * The initialization callback. Here we determine the IDE chip type
 * and initialize its drive independent registers.
 */

static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const char *name)
{
	unsigned char t;
	unsigned int u;
	int i;

/*
 * Check for bad SWDMA.
 */

	if (amd_config->flags & AMD_CHECK_SWDMA) {
		if (dev->revision <= 7)
			amd_config->flags |= AMD_BAD_SWDMA;
	}

/*
 * Check 80-wire cable presence.
 */

	switch (amd_config->udma_mask) {

		case ATA_UDMA6:
		case ATA_UDMA5:
			pci_read_config_byte(dev, AMD_CABLE_DETECT, &t);
			pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
			amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
					printk(KERN_WARNING "%s: BIOS didn't set cable bits correctly. Enabling workaround.\n",
						amd_chipset->name);
					amd_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA4:
			/* no host side cable detection */
			amd_80w = 0x03;
			break;
	}

/*
 * Take care of prefetch & postwrite.
 */

	pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
	pci_write_config_byte(dev, AMD_IDE_CONFIG,
		(amd_config->flags & AMD_BAD_FIFO) ? (t & 0x0f) : (t | 0xf0));

/*
 * Take care of incorrectly wired Serenade mainboards.
 */

	if ((amd_config->flags & AMD_CHECK_SERENADE) &&
		dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
		dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
			amd_config->udma_mask = ATA_UDMA5;

/*
 * Determine the system bus clock.
 */

	amd_clock = system_bus_clock() * 1000;

	switch (amd_clock) {
		case 33000: amd_clock = 33333; break;
		case 37000: amd_clock = 37500; break;
		case 41000: amd_clock = 41666; break;
	}

	if (amd_clock < 20000 || amd_clock > 50000) {
		printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
			amd_chipset->name, amd_clock);
		amd_clock = 33333;
	}

/*
 * Print the boot message.
 */

	pci_read_config_byte(dev, PCI_REVISION_ID, &t);
	printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
		amd_chipset->name, pci_name(dev), dev->revision,
		amd_dma[fls(amd_config->udma_mask) - 1]);

/*
 * Register /proc/ide/amd74xx entry
 */

#if defined(DISPLAY_AMD_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
        if (!amd74xx_proc) {
                amd_base = pci_resource_start(dev, 4);
                bmide_dev = dev;
		ide_pci_create_host_proc("amd74xx", amd74xx_get_info);
                amd74xx_proc = 1;
        }
#endif /* DISPLAY_AMD_TIMINGS && CONFIG_IDE_PROC_FS */

	return dev->irq;
}

static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
{
	int i;

	if (hwif->irq == 0) /* 0 is bogus but will do for now */
		hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel);

	hwif->autodma = 0;

	hwif->set_pio_mode = &amd_set_pio_mode;
	hwif->set_dma_mode = &amd_set_drive;

	for (i = 0; i < 2; i++) {
		hwif->drives[i].io_32bit = 1;
		hwif->drives[i].unmask = 1;
		hwif->drives[i].autotune = 1;
		hwif->drives[i].dn = hwif->channel * 2 + i;
	}

	if (!hwif->dma_base)
		return;

        hwif->atapi_dma = 1;

	hwif->ultra_mask = amd_config->udma_mask;
	hwif->mwdma_mask = 0x07;
	if ((amd_config->flags & AMD_BAD_SWDMA) == 0)
		hwif->swdma_mask = 0x07;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
		if ((amd_80w >> hwif->channel) & 1)
			hwif->cbl = ATA_CBL_PATA80;
		else
			hwif->cbl = ATA_CBL_PATA40;
	}

        if (!noautodma)
                hwif->autodma = 1;
        hwif->drives[0].autodma = hwif->autodma;
        hwif->drives[1].autodma = hwif->autodma;
}

#define DECLARE_AMD_DEV(name_str)					\
	{								\
		.name		= name_str,				\
		.init_chipset	= init_chipset_amd74xx,			\
		.init_hwif	= init_hwif_amd74xx,			\
		.autodma	= AUTODMA,				\
		.enablebits	= {{0x40,0x02,0x02}, {0x40,0x01,0x01}},	\
		.bootable	= ON_BOARD,				\
		.host_flags	= IDE_HFLAG_PIO_NO_BLACKLIST		\
				| IDE_HFLAG_PIO_NO_DOWNGRADE		\
				| IDE_HFLAG_POST_SET_MODE,		\
		.pio_mask	= ATA_PIO5,				\
	}

#define DECLARE_NV_DEV(name_str)					\
	{								\
		.name		= name_str,				\
		.init_chipset	= init_chipset_amd74xx,			\
		.init_hwif	= init_hwif_amd74xx,			\
		.autodma	= AUTODMA,				\
		.enablebits	= {{0x50,0x02,0x02}, {0x50,0x01,0x01}},	\
		.bootable	= ON_BOARD,				\
		.host_flags	= IDE_HFLAG_PIO_NO_BLACKLIST		\
				| IDE_HFLAG_PIO_NO_DOWNGRADE		\
				| IDE_HFLAG_POST_SET_MODE,		\
		.pio_mask	= ATA_PIO5,				\
	}

static ide_pci_device_t amd74xx_chipsets[] __devinitdata = {
	/*  0 */ DECLARE_AMD_DEV("AMD7401"),
	/*  1 */ DECLARE_AMD_DEV("AMD7409"),
	/*  2 */ DECLARE_AMD_DEV("AMD7411"),
	/*  3 */ DECLARE_AMD_DEV("AMD7441"),
	/*  4 */ DECLARE_AMD_DEV("AMD8111"),

	/*  5 */ DECLARE_NV_DEV("NFORCE"),
	/*  6 */ DECLARE_NV_DEV("NFORCE2"),
	/*  7 */ DECLARE_NV_DEV("NFORCE2-U400R"),
	/*  8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA"),
	/*  9 */ DECLARE_NV_DEV("NFORCE3-150"),
	/* 10 */ DECLARE_NV_DEV("NFORCE3-250"),
	/* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA"),
	/* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2"),
	/* 13 */ DECLARE_NV_DEV("NFORCE-CK804"),
	/* 14 */ DECLARE_NV_DEV("NFORCE-MCP04"),
	/* 15 */ DECLARE_NV_DEV("NFORCE-MCP51"),
	/* 16 */ DECLARE_NV_DEV("NFORCE-MCP55"),
	/* 17 */ DECLARE_NV_DEV("NFORCE-MCP61"),
	/* 18 */ DECLARE_NV_DEV("NFORCE-MCP65"),
	/* 19 */ DECLARE_NV_DEV("NFORCE-MCP67"),
	/* 20 */ DECLARE_NV_DEV("NFORCE-MCP73"),
	/* 21 */ DECLARE_NV_DEV("NFORCE-MCP77"),
	/* 22 */ DECLARE_AMD_DEV("AMD5536"),
};

static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	amd_chipset = amd74xx_chipsets + id->driver_data;
	amd_config = amd_ide_chips + id->driver_data;
	if (dev->device != amd_config->id) {
		printk(KERN_ERR "%s: assertion 0x%02x == 0x%02x failed !\n",
		       pci_name(dev), dev->device, amd_config->id);
		return -ENODEV;
	}
	return ide_setup_pci_device(dev, amd_chipset);
}

static const struct pci_device_id amd74xx_pci_tbl[] = {
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_COBRA_7401),		 0 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7409),		 1 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7411),		 2 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_OPUS_7441),		 3 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_8111_IDE),		 4 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE),	 6 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE),	 7 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA),	 8 },
#endif
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE),	 9 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE),	10 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA),	11 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2),	12 },
#endif
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE),	13 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE),	14 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE),	15 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE),	16 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE),	17 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE),	18 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE),	19 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE),	20 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE),	21 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_CS5536_IDE),		22 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "AMD_IDE",
	.id_table	= amd74xx_pci_tbl,
	.probe		= amd74xx_probe,
};

static int __init amd74xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(amd74xx_ide_init);

MODULE_AUTHOR("Vojtech Pavlik");
MODULE_DESCRIPTION("AMD PCI IDE driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
3b4024d4	2	* Version 2.23
1da177e4 LT	3	*
	4	* AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
	5	* IDE driver for Linux.
	6	*
	7	* Copyright (c) 2000-2002 Vojtech Pavlik
75b1d975	8	* Copyright (c) 2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	9	*
	10	* Based on the work of:
	11	* Andre Hedrick
	12	*/
	13
	14	/*
	15	* This program is free software; you can redistribute it and/or modify it
	16	* under the terms of the GNU General Public License version 2 as published by
	17	* the Free Software Foundation.
	18	*/
	19
1da177e4 LT	20	#include <linux/module.h>
	21	#include <linux/kernel.h>
	22	#include <linux/ioport.h>
	23	#include <linux/blkdev.h>
	24	#include <linux/pci.h>
	25	#include <linux/init.h>
	26	#include <linux/ide.h>
	27	#include <asm/io.h>
	28
	29	#include "ide-timing.h"
	30
	31	#define DISPLAY_AMD_TIMINGS
	32
	33	#define AMD_IDE_ENABLE (0x00 + amd_config->base)
	34	#define AMD_IDE_CONFIG (0x01 + amd_config->base)
	35	#define AMD_CABLE_DETECT (0x02 + amd_config->base)
	36	#define AMD_DRIVE_TIMING (0x08 + amd_config->base)
	37	#define AMD_8BIT_TIMING (0x0e + amd_config->base)
	38	#define AMD_ADDRESS_SETUP (0x0c + amd_config->base)
	39	#define AMD_UDMA_TIMING (0x10 + amd_config->base)
	40
1da177e4 LT	41	#define AMD_CHECK_SWDMA 0x08
	42	#define AMD_BAD_SWDMA 0x10
	43	#define AMD_BAD_FIFO 0x20
	44	#define AMD_CHECK_SERENADE 0x40
	45
	46	/*
	47	* AMD SouthBridge chips.
	48	*/
	49
	50	static struct amd_ide_chip {
	51	unsigned short id;
75b1d975 BZ	52	u8 base;
	53	u8 udma_mask;
	54	u8 flags;
1da177e4	55	} amd_ide_chips[] = {
75b1d975 BZ	56	{ PCI_DEVICE_ID_AMD_COBRA_7401, 0x40, ATA_UDMA2, AMD_BAD_SWDMA },
	57	{ PCI_DEVICE_ID_AMD_VIPER_7409, 0x40, ATA_UDMA4, AMD_CHECK_SWDMA },
	58	{ PCI_DEVICE_ID_AMD_VIPER_7411, 0x40, ATA_UDMA5, AMD_BAD_FIFO },
	59	{ PCI_DEVICE_ID_AMD_OPUS_7441, 0x40, ATA_UDMA5, },
	60	{ PCI_DEVICE_ID_AMD_8111_IDE, 0x40, ATA_UDMA6, AMD_CHECK_SERENADE },
	61	{ PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x50, ATA_UDMA5, },
	62	{ PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x50, ATA_UDMA6, },
	63	{ PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, 0x50, ATA_UDMA6, },
	64	{ PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, 0x50, ATA_UDMA6, },
	65	{ PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, 0x50, ATA_UDMA6, },
	66	{ PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, 0x50, ATA_UDMA6, },
	67	{ PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, 0x50, ATA_UDMA6, },
	68	{ PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, 0x50, ATA_UDMA6, },
	69	{ PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, 0x50, ATA_UDMA6, },
	70	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, 0x50, ATA_UDMA6, },
	71	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, 0x50, ATA_UDMA6, },
	72	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, 0x50, ATA_UDMA6, },
	73	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE, 0x50, ATA_UDMA6, },
	74	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE, 0x50, ATA_UDMA6, },
	75	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE, 0x50, ATA_UDMA6, },
	76	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE, 0x50, ATA_UDMA6, },
	77	{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE, 0x50, ATA_UDMA6, },
	78	{ PCI_DEVICE_ID_AMD_CS5536_IDE, 0x40, ATA_UDMA5, },
1da177e4 LT	79	{ 0 }
	80	};
	81
	82	static struct amd_ide_chip *amd_config;
	83	static ide_pci_device_t *amd_chipset;
	84	static unsigned int amd_80w;
	85	static unsigned int amd_clock;
	86
75b1d975	87	static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
1da177e4 LT	88	static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
	89
	90	/*
	91	* AMD /proc entry.
	92	*/
	93
ecfd80e4	94	#ifdef CONFIG_IDE_PROC_FS
1da177e4 LT	95
	96	#include <linux/stat.h>
	97	#include <linux/proc_fs.h>
	98
	99	static u8 amd74xx_proc;
	100
	101	static unsigned char amd_udma2cyc[] = { 4, 6, 8, 10, 3, 2, 1, 15 };
	102	static unsigned long amd_base;
	103	static struct pci_dev *bmide_dev;
	104	extern int (amd74xx_display_info)(char , char *, off_t, int); / ide-proc.c */
	105
	106	#define amd_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
	107	#define amd_print_drive(name, format, arg...)\
	108	p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
	109
	110	static int amd74xx_get_info(char buffer, char *addr, off_t offset, int count)
	111	{
	112	int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
	113	uen[4], udma[4], active8b[4], recover8b[4];
	114	struct pci_dev *dev = bmide_dev;
	115	unsigned int v, u, i;
	116	unsigned short c, w;
	117	unsigned char t;
	118	int len;
	119	char *p = buffer;
	120
	121	amd_print("----------AMD BusMastering IDE Configuration----------------");
	122
	123	amd_print("Driver Version: 2.13");
	124	amd_print("South Bridge: %s", pci_name(bmide_dev));
	125
44c10138	126	amd_print("Revision: IDE %#x", dev->revision);
75b1d975	127	amd_print("Highest DMA rate: UDMA%s", amd_dma[fls(amd_config->udma_mask) - 1]);
1da177e4 LT	128
	129	amd_print("BM-DMA base: %#lx", amd_base);
	130	amd_print("PCI clock: %d.%dMHz", amd_clock / 1000, amd_clock / 100 % 10);
	131
	132	amd_print("-----------------------Primary IDE-------Secondary IDE------");
	133
	134	pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
	135	amd_print("Prefetch Buffer: %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
	136	amd_print("Post Write Buffer: %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
	137
	138	pci_read_config_byte(dev, AMD_IDE_ENABLE, &t);
	139	amd_print("Enabled: %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
	140
	141	c = inb(amd_base + 0x02) \| (inb(amd_base + 0x0a) << 8);
	142	amd_print("Simplex only: %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
	143
	144	amd_print("Cable Type: %10s%20s", (amd_80w & 1) ? "80w" : "40w", (amd_80w & 2) ? "80w" : "40w");
	145
	146	if (!amd_clock)
	147	return p - buffer;
	148
	149	amd_print("-------------------drive0----drive1----drive2----drive3-----");
	150
	151	pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
	152	pci_read_config_dword(dev, AMD_DRIVE_TIMING, &v);
	153	pci_read_config_word(dev, AMD_8BIT_TIMING, &w);
	154	pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
	155
	156	for (i = 0; i < 4; i++) {
	157	setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
	158	recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
	159	active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
	160	active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
	161	recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;
	162
	163	udma[i] = amd_udma2cyc[((u >> ((3 - i) << 3)) & 0x7)];
	164	uen[i] = ((u >> ((3 - i) << 3)) & 0x40) ? 1 : 0;
	165	den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
	166
	167	if (den[i] && uen[i] && udma[i] == 1) {
	168	speed[i] = amd_clock * 3;
	169	cycle[i] = 666666 / amd_clock;
	170	continue;
	171	}
	172
	173	if (den[i] && uen[i] && udma[i] == 15) {
	174	speed[i] = amd_clock * 4;
	175	cycle[i] = 500000 / amd_clock;
	176	continue;
	177	}
	178
	179	speed[i] = 4 * amd_clock / ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2);
	180	cycle[i] = 1000000 * ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2) / amd_clock / 2;
	181	}
	182
	183	amd_print_drive("Transfer Mode: ", "%10s", den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
	184
	185	amd_print_drive("Address Setup: ", "%8dns", 1000000 * setup[i] / amd_clock);
	186	amd_print_drive("Cmd Active: ", "%8dns", 1000000 * active8b[i] / amd_clock);
	187	amd_print_drive("Cmd Recovery: ", "%8dns", 1000000 * recover8b[i] / amd_clock);
	188	amd_print_drive("Data Active: ", "%8dns", 1000000 * active[i] / amd_clock);
	189	amd_print_drive("Data Recovery: ", "%8dns", 1000000 * recover[i] / amd_clock);
	190	amd_print_drive("Cycle Time: ", "%8dns", cycle[i]);
	191	amd_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10);
192
193	/* hoping p - buffer is less than 4K... */
194	len = (p - buffer) - offset;
195	*addr = buffer + offset;
196
197	return len > count ? count : len;
198	}
199
200	#endif
201
202	/*
203	* amd_set_speed() writes timing values to the chipset registers
204	*/
205
206	static void amd_set_speed(struct pci_dev dev, unsigned char dn, struct ide_timing timing)
207	{
208	unsigned char t;
209
210	pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
211	t = (t & ~(3 << ((3 - dn) << 1))) \| ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
212	pci_write_config_byte(dev, AMD_ADDRESS_SETUP, t);
213
214	pci_write_config_byte(dev, AMD_8BIT_TIMING + (1 - (dn >> 1)),
215	((FIT(timing->act8b, 1, 16) - 1) << 4) \| (FIT(timing->rec8b, 1, 16) - 1));
216
217	pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn),
218	((FIT(timing->active, 1, 16) - 1) << 4) \| (FIT(timing->recover, 1, 16) - 1));
219
75b1d975 BZ	220	switch (amd_config->udma_mask) {
	221	case ATA_UDMA2: t = timing->udma ? (0xc0 \| (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	222	case ATA_UDMA4: t = timing->udma ? (0xc0 \| amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
	223	case ATA_UDMA5: t = timing->udma ? (0xc0 \| amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
	224	case ATA_UDMA6: t = timing->udma ? (0xc0 \| amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
	225	default: return;
1da177e4 LT	226	}
	227
	228	pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t);
	229	}
	230
	231	/*
88b2b32b BZ	232	* amd_set_drive() computes timing values and configures the chipset
88b2b32b BZ	233	* to a desired transfer mode. It also can be called by upper layers.
1da177e4 LT	234	*/
1da177e4 LT	235
88b2b32b	236	static void amd_set_drive(ide_drive_t *drive, const u8 speed)
1da177e4 LT	237	{
	238	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
	239	struct ide_timing t, p;
	240	int T, UT;
	241
1da177e4	242	T = 1000000000 / amd_clock;
75b1d975	243	UT = (amd_config->udma_mask == ATA_UDMA2) ? T : (T / 2);
1da177e4 LT	244
	245	ide_timing_compute(drive, speed, &t, T, UT);
	246
	247	if (peer->present) {
	248	ide_timing_compute(peer, peer->current_speed, &p, T, UT);
	249	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	250	}
	251
	252	if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
	253	if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
	254
	255	amd_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
1da177e4 LT	256	}
	257
	258	/*
26bcb879	259	* amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
1da177e4 LT	260	*/
1da177e4 LT	261
26bcb879	262	static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	263	{
26bcb879	264	amd_set_drive(drive, XFER_PIO_0 + pio);
1da177e4 LT	265	}
1da177e4 LT	266
1da177e4 LT	267	/*
	268	* The initialization callback. Here we determine the IDE chip type
	269	* and initialize its drive independent registers.
	270	*/
	271
e895f926	272	static unsigned int __devinit init_chipset_amd74xx(struct pci_dev dev, const char name)
1da177e4 LT	273	{
	274	unsigned char t;
	275	unsigned int u;
	276	int i;
	277
	278	/*
	279	* Check for bad SWDMA.
	280	*/
	281
	282	if (amd_config->flags & AMD_CHECK_SWDMA) {
44c10138	283	if (dev->revision <= 7)
1da177e4 LT	284	amd_config->flags \|= AMD_BAD_SWDMA;
	285	}
	286
	287	/*
	288	* Check 80-wire cable presence.
	289	*/
	290
75b1d975	291	switch (amd_config->udma_mask) {
1da177e4	292
75b1d975 BZ	293	case ATA_UDMA6:
75b1d975 BZ	294	case ATA_UDMA5:
1da177e4 LT	295	pci_read_config_byte(dev, AMD_CABLE_DETECT, &t);
	296	pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
	297	amd_80w = ((t & 0x3) ? 1 : 0) \| ((t & 0xc) ? 2 : 0);
	298	for (i = 24; i >= 0; i -= 8)
	299	if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
	300	printk(KERN_WARNING "%s: BIOS didn't set cable bits correctly. Enabling workaround.\n",
	301	amd_chipset->name);
	302	amd_80w \|= (1 << (1 - (i >> 4)));
	303	}
	304	break;
	305
75b1d975	306	case ATA_UDMA4:
9edc91df RH	307	/* no host side cable detection */
9edc91df RH	308	amd_80w = 0x03;
1da177e4 LT	309	break;
	310	}
	311
	312	/*
	313	* Take care of prefetch & postwrite.
	314	*/
	315
	316	pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
	317	pci_write_config_byte(dev, AMD_IDE_CONFIG,
	318	(amd_config->flags & AMD_BAD_FIFO) ? (t & 0x0f) : (t \| 0xf0));
	319
	320	/*
	321	* Take care of incorrectly wired Serenade mainboards.
	322	*/
	323
	324	if ((amd_config->flags & AMD_CHECK_SERENADE) &&
	325	dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
	326	dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
75b1d975	327	amd_config->udma_mask = ATA_UDMA5;
1da177e4 LT	328
	329	/*
	330	* Determine the system bus clock.
	331	*/
	332
	333	amd_clock = system_bus_clock() * 1000;
	334
	335	switch (amd_clock) {
	336	case 33000: amd_clock = 33333; break;
	337	case 37000: amd_clock = 37500; break;
	338	case 41000: amd_clock = 41666; break;
	339	}
	340
	341	if (amd_clock < 20000 \|\| amd_clock > 50000) {
	342	printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
	343	amd_chipset->name, amd_clock);
1da177e4 LT	344	amd_clock = 33333;
	345	}
	346
	347	/*
	348	* Print the boot message.
	349	*/
	350
	351	pci_read_config_byte(dev, PCI_REVISION_ID, &t);
75b1d975	352	printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
44c10138	353	amd_chipset->name, pci_name(dev), dev->revision,
75b1d975	354	amd_dma[fls(amd_config->udma_mask) - 1]);
1da177e4 LT	355
	356	/*
	357	* Register /proc/ide/amd74xx entry
	358	*/
	359
ecfd80e4	360	#if defined(DISPLAY_AMD_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
1da177e4 LT	361	if (!amd74xx_proc) {
	362	amd_base = pci_resource_start(dev, 4);
	363	bmide_dev = dev;
	364	ide_pci_create_host_proc("amd74xx", amd74xx_get_info);
	365	amd74xx_proc = 1;
	366	}
ecfd80e4	367	#endif /* DISPLAY_AMD_TIMINGS && CONFIG_IDE_PROC_FS */
1da177e4 LT	368
	369	return dev->irq;
	370	}
	371
e895f926	372	static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
1da177e4 LT	373	{
	374	int i;
	375
	376	if (hwif->irq == 0) /* 0 is bogus but will do for now */
	377	hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel);
	378
	379	hwif->autodma = 0;
	380
26bcb879	381	hwif->set_pio_mode = &amd_set_pio_mode;
88b2b32b	382	hwif->set_dma_mode = &amd_set_drive;
1da177e4 LT	383
	384	for (i = 0; i < 2; i++) {
	385	hwif->drives[i].io_32bit = 1;
	386	hwif->drives[i].unmask = 1;
	387	hwif->drives[i].autotune = 1;
	388	hwif->drives[i].dn = hwif->channel * 2 + i;
	389	}
	390
	391	if (!hwif->dma_base)
	392	return;
	393
	394	hwif->atapi_dma = 1;
75b1d975 BZ	395
	396	hwif->ultra_mask = amd_config->udma_mask;
	397	hwif->mwdma_mask = 0x07;
	398	if ((amd_config->flags & AMD_BAD_SWDMA) == 0)
	399	hwif->swdma_mask = 0x07;
1da177e4	400
49521f97 BZ	401	if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
	402	if ((amd_80w >> hwif->channel) & 1)
	403	hwif->cbl = ATA_CBL_PATA80;
	404	else
	405	hwif->cbl = ATA_CBL_PATA40;
	406	}
	407
1da177e4 LT	408	if (!noautodma)
	409	hwif->autodma = 1;
	410	hwif->drives[0].autodma = hwif->autodma;
	411	hwif->drives[1].autodma = hwif->autodma;
	412	}
	413
	414	#define DECLARE_AMD_DEV(name_str) \
	415	{ \
	416	.name = name_str, \
	417	.init_chipset = init_chipset_amd74xx, \
	418	.init_hwif = init_hwif_amd74xx, \
1da177e4 LT	419	.autodma = AUTODMA, \
	420	.enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
	421	.bootable = ON_BOARD, \
6a824c92	422	.host_flags = IDE_HFLAG_PIO_NO_BLACKLIST \
88b2b32b BZ	423	\| IDE_HFLAG_PIO_NO_DOWNGRADE \
88b2b32b BZ	424	\| IDE_HFLAG_POST_SET_MODE, \
4099d143	425	.pio_mask = ATA_PIO5, \
1da177e4 LT	426	}
	427
	428	#define DECLARE_NV_DEV(name_str) \
	429	{ \
	430	.name = name_str, \
	431	.init_chipset = init_chipset_amd74xx, \
	432	.init_hwif = init_hwif_amd74xx, \
1da177e4 LT	433	.autodma = AUTODMA, \
	434	.enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
	435	.bootable = ON_BOARD, \
6a824c92	436	.host_flags = IDE_HFLAG_PIO_NO_BLACKLIST \
88b2b32b BZ	437	\| IDE_HFLAG_PIO_NO_DOWNGRADE \
88b2b32b BZ	438	\| IDE_HFLAG_POST_SET_MODE, \
4099d143	439	.pio_mask = ATA_PIO5, \
1da177e4 LT	440	}
	441
	442	static ide_pci_device_t amd74xx_chipsets[] __devinitdata = {
	443	/* 0 */ DECLARE_AMD_DEV("AMD7401"),
	444	/* 1 */ DECLARE_AMD_DEV("AMD7409"),
	445	/* 2 */ DECLARE_AMD_DEV("AMD7411"),
	446	/* 3 */ DECLARE_AMD_DEV("AMD7441"),
	447	/* 4 */ DECLARE_AMD_DEV("AMD8111"),
	448
	449	/* 5 */ DECLARE_NV_DEV("NFORCE"),
	450	/* 6 */ DECLARE_NV_DEV("NFORCE2"),
	451	/* 7 */ DECLARE_NV_DEV("NFORCE2-U400R"),
	452	/* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA"),
	453	/* 9 */ DECLARE_NV_DEV("NFORCE3-150"),
	454	/* 10 */ DECLARE_NV_DEV("NFORCE3-250"),
	455	/* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA"),
	456	/* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2"),
	457	/* 13 */ DECLARE_NV_DEV("NFORCE-CK804"),
	458	/* 14 */ DECLARE_NV_DEV("NFORCE-MCP04"),
af00f981	459	/* 15 */ DECLARE_NV_DEV("NFORCE-MCP51"),
21e2c01d	460	/* 16 */ DECLARE_NV_DEV("NFORCE-MCP55"),
4c5c8161	461	/* 17 */ DECLARE_NV_DEV("NFORCE-MCP61"),
353dcf7c	462	/* 18 */ DECLARE_NV_DEV("NFORCE-MCP65"),
cda5e61a	463	/* 19 */ DECLARE_NV_DEV("NFORCE-MCP67"),
c1183a33 PC	464	/* 20 */ DECLARE_NV_DEV("NFORCE-MCP73"),
	465	/* 21 */ DECLARE_NV_DEV("NFORCE-MCP77"),
	466	/* 22 */ DECLARE_AMD_DEV("AMD5536"),
1da177e4 LT	467	};
	468
	469	static int __devinit amd74xx_probe(struct pci_dev dev, const struct pci_device_id id)
	470	{
	471	amd_chipset = amd74xx_chipsets + id->driver_data;
	472	amd_config = amd_ide_chips + id->driver_data;
	473	if (dev->device != amd_config->id) {
	474	printk(KERN_ERR "%s: assertion 0x%02x == 0x%02x failed !\n",
	475	pci_name(dev), dev->device, amd_config->id);
	476	return -ENODEV;
	477	}
	478	return ide_setup_pci_device(dev, amd_chipset);
	479	}
	480
9cbcc5e3 BZ	481	static const struct pci_device_id amd74xx_pci_tbl[] = {
	482	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
	483	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
	484	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 },
	485	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 3 },
	486	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 4 },
	487	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 5 },
	488	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 6 },
	489	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 7 },
1da177e4	490	#ifdef CONFIG_BLK_DEV_IDE_SATA
9cbcc5e3	491	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 8 },
1da177e4	492	#endif
9cbcc5e3 BZ	493	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 9 },
9cbcc5e3 BZ	494	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 10 },
1da177e4	495	#ifdef CONFIG_BLK_DEV_IDE_SATA
9cbcc5e3 BZ	496	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 11 },
9cbcc5e3 BZ	497	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 12 },
1da177e4	498	#endif
9cbcc5e3 BZ	499	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 13 },
	500	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 14 },
	501	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 15 },
	502	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 16 },
	503	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 17 },
	504	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 18 },
	505	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 19 },
	506	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 20 },
	507	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 21 },
	508	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 22 },
1da177e4 LT	509	{ 0, },
	510	};
	511	MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
	512
	513	static struct pci_driver driver = {
	514	.name = "AMD_IDE",
	515	.id_table = amd74xx_pci_tbl,
	516	.probe = amd74xx_probe,
	517	};
	518
82ab1eec	519	static int __init amd74xx_ide_init(void)
1da177e4 LT	520	{
	521	return ide_pci_register_driver(&driver);
	522	}
	523
	524	module_init(amd74xx_ide_init);
	525
	526	MODULE_AUTHOR("Vojtech Pavlik");
	527	MODULE_DESCRIPTION("AMD PCI IDE driver");
	528	MODULE_LICENSE("GPL");