[mirror_ubuntu-bionic-kernel.git] / drivers / ide / pci / amd74xx.c

/*
 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
 * IDE driver for Linux.
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
 *
 * Based on the work of:
 *      Andre Hedrick
 */

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

enum {
	AMD_IDE_CONFIG		= 0x41,
	AMD_CABLE_DETECT	= 0x42,
	AMD_DRIVE_TIMING	= 0x48,
	AMD_8BIT_TIMING		= 0x4e,
	AMD_ADDRESS_SETUP	= 0x4c,
	AMD_UDMA_TIMING		= 0x50,
};

static unsigned int amd_80w;
static unsigned int amd_clock;

static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };

static inline u8 amd_offset(struct pci_dev *dev)
{
	return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0;
}

/*
 * amd_set_speed() writes timing values to the chipset registers
 */

static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
			  struct ide_timing *timing)
{
	u8 t = 0, offset = amd_offset(dev);

	pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t);
	t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
	pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t);

	pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)),
		((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn),
		((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));

	switch (udma_mask) {
	case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
	case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break;
	case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break;
	case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break;
	default: return;
	}

	pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t);
}

/*
 * amd_set_drive() computes timing values and configures the chipset
 * to a desired transfer mode.  It also can be called by upper layers.
 */

static void amd_set_drive(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	ide_drive_t *peer = hwif->drives + (~drive->dn & 1);
	struct ide_timing t, p;
	int T, UT;
	u8 udma_mask = hwif->ultra_mask;

	T = 1000000000 / amd_clock;
	UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer->present) {
		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
	if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;

	amd_set_speed(dev, drive->dn, udma_mask, &t);
}

/*
 * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
 */

static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	amd_set_drive(drive, XFER_PIO_0 + pio);
}

static void __devinit amd7409_cable_detect(struct pci_dev *dev,
					   const char *name)
{
	/* no host side cable detection */
	amd_80w = 0x03;
}

static void __devinit amd7411_cable_detect(struct pci_dev *dev,
					   const char *name)
{
	int i;
	u32 u = 0;
	u8 t = 0, offset = amd_offset(dev);

	pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t);
	pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u);
	amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
	for (i = 24; i >= 0; i -= 8)
		if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
			printk(KERN_WARNING "%s: BIOS didn't set cable bits "
					    "correctly. Enabling workaround.\n",
					    name);
			amd_80w |= (1 << (1 - (i >> 4)));
		}
}

/*
 * The initialization callback.  Initialize drive independent registers.
 */

static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev,
						   const char *name)
{
	u8 t = 0, offset = amd_offset(dev);

/*
 * Check 80-wire cable presence.
 */

	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	    dev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
		; /* no UDMA > 2 */
	else if (dev->vendor == PCI_VENDOR_ID_AMD &&
		 dev->device == PCI_DEVICE_ID_AMD_VIPER_7409)
		amd7409_cable_detect(dev, name);
	else
		amd7411_cable_detect(dev, name);

/*
 * Take care of prefetch & postwrite.
 */

	pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t);
	/*
	 * Check for broken FIFO support.
	 */
	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	    dev->vendor == PCI_DEVICE_ID_AMD_VIPER_7411)
		t &= 0x0f;
	else
		t |= 0xf0;
	pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t);

/*
 * Determine the system bus clock.
 */

	amd_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;

	switch (amd_clock) {
		case 33000: amd_clock = 33333; break;
		case 37000: amd_clock = 37500; break;
		case 41000: amd_clock = 41666; break;
	}

	if (amd_clock < 20000 || amd_clock > 50000) {
		printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
				    name, amd_clock);
		amd_clock = 33333;
	}

	return dev->irq;
}

static u8 __devinit amd_cable_detect(ide_hwif_t *hwif)
{
	if ((amd_80w >> hwif->channel) & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (hwif->irq == 0) /* 0 is bogus but will do for now */
		hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
}

static const struct ide_port_ops amd_port_ops = {
	.set_pio_mode		= amd_set_pio_mode,
	.set_dma_mode		= amd_set_drive,
	.cable_detect		= amd_cable_detect,
};

#define IDE_HFLAGS_AMD \
	(IDE_HFLAG_PIO_NO_BLACKLIST | \
	 IDE_HFLAG_POST_SET_MODE | \
	 IDE_HFLAG_IO_32BIT | \
	 IDE_HFLAG_UNMASK_IRQS)

#define DECLARE_AMD_DEV(name_str, swdma, udma)				\
	{								\
		.name		= name_str,				\
		.init_chipset	= init_chipset_amd74xx,			\
		.init_hwif	= init_hwif_amd74xx,			\
		.enablebits	= {{0x40,0x02,0x02}, {0x40,0x01,0x01}},	\
		.port_ops	= &amd_port_ops,			\
		.host_flags	= IDE_HFLAGS_AMD,			\
		.pio_mask	= ATA_PIO5,				\
		.swdma_mask	= swdma,				\
		.mwdma_mask	= ATA_MWDMA2,				\
		.udma_mask	= udma,					\
	}

#define DECLARE_NV_DEV(name_str, udma)					\
	{								\
		.name		= name_str,				\
		.init_chipset	= init_chipset_amd74xx,			\
		.init_hwif	= init_hwif_amd74xx,			\
		.enablebits	= {{0x50,0x02,0x02}, {0x50,0x01,0x01}},	\
		.port_ops	= &amd_port_ops,			\
		.host_flags	= IDE_HFLAGS_AMD,			\
		.pio_mask	= ATA_PIO5,				\
		.swdma_mask	= ATA_SWDMA2,				\
		.mwdma_mask	= ATA_MWDMA2,				\
		.udma_mask	= udma,					\
	}

static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
	/*  0 */ DECLARE_AMD_DEV("AMD7401",	  0x00, ATA_UDMA2),
	/*  1 */ DECLARE_AMD_DEV("AMD7409", ATA_SWDMA2, ATA_UDMA4),
	/*  2 */ DECLARE_AMD_DEV("AMD7411", ATA_SWDMA2, ATA_UDMA5),
	/*  3 */ DECLARE_AMD_DEV("AMD7441", ATA_SWDMA2, ATA_UDMA5),
	/*  4 */ DECLARE_AMD_DEV("AMD8111", ATA_SWDMA2, ATA_UDMA6),

	/*  5 */ DECLARE_NV_DEV("NFORCE",		ATA_UDMA5),
	/*  6 */ DECLARE_NV_DEV("NFORCE2",		ATA_UDMA6),
	/*  7 */ DECLARE_NV_DEV("NFORCE2-U400R",	ATA_UDMA6),
	/*  8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA",	ATA_UDMA6),
	/*  9 */ DECLARE_NV_DEV("NFORCE3-150",		ATA_UDMA6),
	/* 10 */ DECLARE_NV_DEV("NFORCE3-250",		ATA_UDMA6),
	/* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA",	ATA_UDMA6),
	/* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2",	ATA_UDMA6),
	/* 13 */ DECLARE_NV_DEV("NFORCE-CK804",		ATA_UDMA6),
	/* 14 */ DECLARE_NV_DEV("NFORCE-MCP04",		ATA_UDMA6),
	/* 15 */ DECLARE_NV_DEV("NFORCE-MCP51",		ATA_UDMA6),
	/* 16 */ DECLARE_NV_DEV("NFORCE-MCP55",		ATA_UDMA6),
	/* 17 */ DECLARE_NV_DEV("NFORCE-MCP61",		ATA_UDMA6),
	/* 18 */ DECLARE_NV_DEV("NFORCE-MCP65",		ATA_UDMA6),
	/* 19 */ DECLARE_NV_DEV("NFORCE-MCP67",		ATA_UDMA6),
	/* 20 */ DECLARE_NV_DEV("NFORCE-MCP73",		ATA_UDMA6),
	/* 21 */ DECLARE_NV_DEV("NFORCE-MCP77",		ATA_UDMA6),

	/* 22 */ DECLARE_AMD_DEV("AMD5536", ATA_SWDMA2, ATA_UDMA5),
};

static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = amd74xx_chipsets[idx];

	/*
	 * Check for bad SWDMA and incorrectly wired Serenade mainboards.
	 */
	if (idx == 1) {
		if (dev->revision <= 7)
			d.swdma_mask = 0;
		d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
	} else if (idx == 4) {
		if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
		    dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
			d.udma_mask = ATA_UDMA5;
	}

	printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
			 d.name, pci_name(dev), dev->revision,
			 amd_dma[fls(d.udma_mask) - 1]);

	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id amd74xx_pci_tbl[] = {
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_COBRA_7401),		 0 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7409),		 1 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7411),		 2 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_OPUS_7441),		 3 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_8111_IDE),		 4 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE),	 6 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE),	 7 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA),	 8 },
#endif
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE),	 9 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE),	10 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA),	11 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2),	12 },
#endif
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE),	13 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE),	14 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE),	15 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE),	16 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE),	17 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE),	18 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE),	19 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE),	20 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE),	21 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_CS5536_IDE),		22 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "AMD_IDE",
	.id_table	= amd74xx_pci_tbl,
	.probe		= amd74xx_probe,
};

static int __init amd74xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(amd74xx_ide_init);

MODULE_AUTHOR("Vojtech Pavlik");
MODULE_DESCRIPTION("AMD PCI IDE driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
	3	* IDE driver for Linux.
	4	*
	5	* Copyright (c) 2000-2002 Vojtech Pavlik
75b1d975	6	* Copyright (c) 2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	7	*
	8	* Based on the work of:
	9	* Andre Hedrick
	10	*/
	11
	12	/*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License version 2 as published by
	15	* the Free Software Foundation.
	16	*/
	17
1da177e4 LT	18	#include <linux/module.h>
1da177e4 LT	19	#include <linux/kernel.h>
1da177e4 LT	20	#include <linux/pci.h>
	21	#include <linux/init.h>
	22	#include <linux/ide.h>
1da177e4	23
993da8f9 BZ	24	enum {
	25	AMD_IDE_CONFIG = 0x41,
	26	AMD_CABLE_DETECT = 0x42,
	27	AMD_DRIVE_TIMING = 0x48,
	28	AMD_8BIT_TIMING = 0x4e,
	29	AMD_ADDRESS_SETUP = 0x4c,
	30	AMD_UDMA_TIMING = 0x50,
1da177e4 LT	31	};
1da177e4 LT	32
1da177e4 LT	33	static unsigned int amd_80w;
	34	static unsigned int amd_clock;
	35
75b1d975	36	static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
1da177e4 LT	37	static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
1da177e4 LT	38
993da8f9 BZ	39	static inline u8 amd_offset(struct pci_dev *dev)
	40	{
	41	return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0;
	42	}
	43
1da177e4 LT	44	/*
	45	* amd_set_speed() writes timing values to the chipset registers
	46	*/
	47
993da8f9 BZ	48	static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
993da8f9 BZ	49	struct ide_timing *timing)
1da177e4	50	{
993da8f9	51	u8 t = 0, offset = amd_offset(dev);
1da177e4	52
993da8f9	53	pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t);
d6cddd3c	54	t = (t & ~(3 << ((3 - dn) << 1))) \| ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
993da8f9	55	pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t);
1da177e4	56
993da8f9	57	pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)),
d6cddd3c	58	((clamp_val(timing->act8b, 1, 16) - 1) << 4) \| (clamp_val(timing->rec8b, 1, 16) - 1));
1da177e4	59
993da8f9	60	pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn),
d6cddd3c	61	((clamp_val(timing->active, 1, 16) - 1) << 4) \| (clamp_val(timing->recover, 1, 16) - 1));
1da177e4	62
993da8f9	63	switch (udma_mask) {
d6cddd3c HH	64	case ATA_UDMA2: t = timing->udma ? (0xc0 \| (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
	65	case ATA_UDMA4: t = timing->udma ? (0xc0 \| amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break;
	66	case ATA_UDMA5: t = timing->udma ? (0xc0 \| amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break;
	67	case ATA_UDMA6: t = timing->udma ? (0xc0 \| amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break;
75b1d975	68	default: return;
1da177e4 LT	69	}
1da177e4 LT	70
993da8f9	71	pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t);
1da177e4 LT	72	}
	73
	74	/*
88b2b32b BZ	75	* amd_set_drive() computes timing values and configures the chipset
88b2b32b BZ	76	* to a desired transfer mode. It also can be called by upper layers.
1da177e4 LT	77	*/
1da177e4 LT	78
88b2b32b	79	static void amd_set_drive(ide_drive_t *drive, const u8 speed)
1da177e4	80	{
993da8f9	81	ide_hwif_t *hwif = drive->hwif;
36501650	82	struct pci_dev *dev = to_pci_dev(hwif->dev);
993da8f9	83	ide_drive_t *peer = hwif->drives + (~drive->dn & 1);
1da177e4 LT	84	struct ide_timing t, p;
1da177e4 LT	85	int T, UT;
993da8f9	86	u8 udma_mask = hwif->ultra_mask;
1da177e4	87
1da177e4	88	T = 1000000000 / amd_clock;
993da8f9	89	UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);
1da177e4 LT	90
	91	ide_timing_compute(drive, speed, &t, T, UT);
	92
	93	if (peer->present) {
	94	ide_timing_compute(peer, peer->current_speed, &p, T, UT);
	95	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	96	}
	97
	98	if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
	99	if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
	100
36501650	101	amd_set_speed(dev, drive->dn, udma_mask, &t);
1da177e4 LT	102	}
	103
	104	/*
26bcb879	105	* amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
1da177e4 LT	106	*/
1da177e4 LT	107
26bcb879	108	static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	109	{
26bcb879	110	amd_set_drive(drive, XFER_PIO_0 + pio);
1da177e4 LT	111	}
1da177e4 LT	112
993da8f9 BZ	113	static void __devinit amd7409_cable_detect(struct pci_dev *dev,
	114	const char *name)
	115	{
	116	/* no host side cable detection */
	117	amd_80w = 0x03;
	118	}
1da177e4	119
993da8f9 BZ	120	static void __devinit amd7411_cable_detect(struct pci_dev *dev,
993da8f9 BZ	121	const char *name)
1da177e4	122	{
1da177e4	123	int i;
993da8f9 BZ	124	u32 u = 0;
	125	u8 t = 0, offset = amd_offset(dev);
	126
	127	pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t);
	128	pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u);
	129	amd_80w = ((t & 0x3) ? 1 : 0) \| ((t & 0xc) ? 2 : 0);
	130	for (i = 24; i >= 0; i -= 8)
	131	if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
	132	printk(KERN_WARNING "%s: BIOS didn't set cable bits "
	133	"correctly. Enabling workaround.\n",
	134	name);
	135	amd_80w \|= (1 << (1 - (i >> 4)));
	136	}
	137	}
1da177e4 LT	138
1da177e4 LT	139	/*
993da8f9	140	* The initialization callback. Initialize drive independent registers.
1da177e4 LT	141	*/
1da177e4 LT	142
993da8f9 BZ	143	static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev,
	144	const char *name)
	145	{
	146	u8 t = 0, offset = amd_offset(dev);
1da177e4 LT	147
	148	/*
	149	* Check 80-wire cable presence.
	150	*/
	151
993da8f9 BZ	152	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	153	dev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
	154	; /* no UDMA > 2 */
	155	else if (dev->vendor == PCI_VENDOR_ID_AMD &&
	156	dev->device == PCI_DEVICE_ID_AMD_VIPER_7409)
	157	amd7409_cable_detect(dev, name);
	158	else
	159	amd7411_cable_detect(dev, name);
1da177e4 LT	160
	161	/*
	162	* Take care of prefetch & postwrite.
	163	*/
	164
993da8f9 BZ	165	pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t);
	166	/*
	167	* Check for broken FIFO support.
	168	*/
	169	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	170	dev->vendor == PCI_DEVICE_ID_AMD_VIPER_7411)
	171	t &= 0x0f;
	172	else
	173	t \|= 0xf0;
	174	pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t);
1da177e4 LT	175
	176	/*
	177	* Determine the system bus clock.
	178	*/
	179
30e5ee4d	180	amd_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
1da177e4 LT	181
	182	switch (amd_clock) {
	183	case 33000: amd_clock = 33333; break;
	184	case 37000: amd_clock = 37500; break;
	185	case 41000: amd_clock = 41666; break;
	186	}
	187
	188	if (amd_clock < 20000 \|\| amd_clock > 50000) {
	189	printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
993da8f9	190	name, amd_clock);
1da177e4 LT	191	amd_clock = 33333;
	192	}
	193
1da177e4 LT	194	return dev->irq;
	195	}
	196
bfa14b42 BZ	197	static u8 __devinit amd_cable_detect(ide_hwif_t *hwif)
	198	{
	199	if ((amd_80w >> hwif->channel) & 1)
	200	return ATA_CBL_PATA80;
	201	else
	202	return ATA_CBL_PATA40;
	203	}
	204
e895f926	205	static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
1da177e4	206	{
36501650 BZ	207	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	208
1da177e4	209	if (hwif->irq == 0) /* 0 is bogus but will do for now */
36501650	210	hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
1da177e4 LT	211	}
1da177e4 LT	212
ac95beed BZ	213	static const struct ide_port_ops amd_port_ops = {
	214	.set_pio_mode = amd_set_pio_mode,
	215	.set_dma_mode = amd_set_drive,
	216	.cable_detect = amd_cable_detect,
	217	};
	218
caea7602 BZ	219	#define IDE_HFLAGS_AMD \
caea7602 BZ	220	(IDE_HFLAG_PIO_NO_BLACKLIST \| \
caea7602 BZ	221	IDE_HFLAG_POST_SET_MODE \| \
caea7602 BZ	222	IDE_HFLAG_IO_32BIT \| \
5e71d9c5	223	IDE_HFLAG_UNMASK_IRQS)
caea7602	224
993da8f9	225	#define DECLARE_AMD_DEV(name_str, swdma, udma) \
1da177e4 LT	226	{ \
	227	.name = name_str, \
	228	.init_chipset = init_chipset_amd74xx, \
	229	.init_hwif = init_hwif_amd74xx, \
1da177e4	230	.enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
ac95beed	231	.port_ops = &amd_port_ops, \
caea7602	232	.host_flags = IDE_HFLAGS_AMD, \
4099d143	233	.pio_mask = ATA_PIO5, \
993da8f9	234	.swdma_mask = swdma, \
5f8b6c34	235	.mwdma_mask = ATA_MWDMA2, \
993da8f9	236	.udma_mask = udma, \
1da177e4 LT	237	}
1da177e4 LT	238
993da8f9	239	#define DECLARE_NV_DEV(name_str, udma) \
1da177e4 LT	240	{ \
	241	.name = name_str, \
	242	.init_chipset = init_chipset_amd74xx, \
	243	.init_hwif = init_hwif_amd74xx, \
1da177e4	244	.enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
ac95beed	245	.port_ops = &amd_port_ops, \
caea7602	246	.host_flags = IDE_HFLAGS_AMD, \
4099d143	247	.pio_mask = ATA_PIO5, \
5f8b6c34 BZ	248	.swdma_mask = ATA_SWDMA2, \
5f8b6c34 BZ	249	.mwdma_mask = ATA_MWDMA2, \
993da8f9	250	.udma_mask = udma, \
1da177e4 LT	251	}
1da177e4 LT	252
85620436	253	static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
993da8f9 BZ	254	/* 0 */ DECLARE_AMD_DEV("AMD7401", 0x00, ATA_UDMA2),
	255	/* 1 */ DECLARE_AMD_DEV("AMD7409", ATA_SWDMA2, ATA_UDMA4),
	256	/* 2 */ DECLARE_AMD_DEV("AMD7411", ATA_SWDMA2, ATA_UDMA5),
	257	/* 3 */ DECLARE_AMD_DEV("AMD7441", ATA_SWDMA2, ATA_UDMA5),
	258	/* 4 */ DECLARE_AMD_DEV("AMD8111", ATA_SWDMA2, ATA_UDMA6),
	259
	260	/* 5 */ DECLARE_NV_DEV("NFORCE", ATA_UDMA5),
	261	/* 6 */ DECLARE_NV_DEV("NFORCE2", ATA_UDMA6),
	262	/* 7 */ DECLARE_NV_DEV("NFORCE2-U400R", ATA_UDMA6),
	263	/* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA", ATA_UDMA6),
	264	/* 9 */ DECLARE_NV_DEV("NFORCE3-150", ATA_UDMA6),
	265	/* 10 */ DECLARE_NV_DEV("NFORCE3-250", ATA_UDMA6),
	266	/* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA", ATA_UDMA6),
	267	/* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2", ATA_UDMA6),
	268	/* 13 */ DECLARE_NV_DEV("NFORCE-CK804", ATA_UDMA6),
	269	/* 14 */ DECLARE_NV_DEV("NFORCE-MCP04", ATA_UDMA6),
	270	/* 15 */ DECLARE_NV_DEV("NFORCE-MCP51", ATA_UDMA6),
	271	/* 16 */ DECLARE_NV_DEV("NFORCE-MCP55", ATA_UDMA6),
	272	/* 17 */ DECLARE_NV_DEV("NFORCE-MCP61", ATA_UDMA6),
	273	/* 18 */ DECLARE_NV_DEV("NFORCE-MCP65", ATA_UDMA6),
	274	/* 19 */ DECLARE_NV_DEV("NFORCE-MCP67", ATA_UDMA6),
	275	/* 20 */ DECLARE_NV_DEV("NFORCE-MCP73", ATA_UDMA6),
	276	/* 21 */ DECLARE_NV_DEV("NFORCE-MCP77", ATA_UDMA6),
	277
	278	/* 22 */ DECLARE_AMD_DEV("AMD5536", ATA_SWDMA2, ATA_UDMA5),
1da177e4 LT	279	};
	280
	281	static int __devinit amd74xx_probe(struct pci_dev dev, const struct pci_device_id id)
	282	{
993da8f9 BZ	283	struct ide_port_info d;
	284	u8 idx = id->driver_data;
	285
	286	d = amd74xx_chipsets[idx];
	287
	288	/*
	289	* Check for bad SWDMA and incorrectly wired Serenade mainboards.
	290	*/
	291	if (idx == 1) {
	292	if (dev->revision <= 7)
	293	d.swdma_mask = 0;
8ac2b42a	294	d.host_flags \|= IDE_HFLAG_CLEAR_SIMPLEX;
993da8f9 BZ	295	} else if (idx == 4) {
	296	if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
	297	dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
	298	d.udma_mask = ATA_UDMA5;
1da177e4	299	}
993da8f9 BZ	300
	301	printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
	302	d.name, pci_name(dev), dev->revision,
	303	amd_dma[fls(d.udma_mask) - 1]);
	304
6cdf6eb3	305	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	306	}
1da177e4 LT	307
9cbcc5e3 BZ	308	static const struct pci_device_id amd74xx_pci_tbl[] = {
	309	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
	310	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
	311	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 },
	312	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 3 },
	313	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 4 },
	314	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 5 },
	315	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 6 },
	316	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 7 },
1da177e4	317	#ifdef CONFIG_BLK_DEV_IDE_SATA
9cbcc5e3	318	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 8 },
1da177e4	319	#endif
9cbcc5e3 BZ	320	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 9 },
9cbcc5e3 BZ	321	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 10 },
1da177e4	322	#ifdef CONFIG_BLK_DEV_IDE_SATA
9cbcc5e3 BZ	323	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 11 },
9cbcc5e3 BZ	324	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 12 },
1da177e4	325	#endif
9cbcc5e3 BZ	326	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 13 },
	327	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 14 },
	328	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 15 },
	329	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 16 },
	330	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 17 },
	331	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 18 },
	332	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 19 },
	333	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 20 },
	334	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 21 },
	335	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 22 },
1da177e4 LT	336	{ 0, },
	337	};
	338	MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
	339
	340	static struct pci_driver driver = {
	341	.name = "AMD_IDE",
	342	.id_table = amd74xx_pci_tbl,
	343	.probe = amd74xx_probe,
	344	};
	345
82ab1eec	346	static int __init amd74xx_ide_init(void)
1da177e4 LT	347	{
	348	return ide_pci_register_driver(&driver);
	349	}
	350
	351	module_init(amd74xx_ide_init);
	352
	353	MODULE_AUTHOR("Vojtech Pavlik");
	354	MODULE_DESCRIPTION("AMD PCI IDE driver");
	355	MODULE_LICENSE("GPL");