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1da177e4 LT |
1 | /* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16 |
2 | * | |
3 | * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002 | |
4 | * | |
5 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. | |
6 | * Note, this driver is not used at all on other systems because | |
7 | * there the "BIOS" has done all of the following already. | |
8 | * Due to massive hardware bugs, UltraDMA is only supported | |
9 | * on the 646U2 and not on the 646U. | |
10 | * | |
11 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
12 | * Copyright (C) 1998 David S. Miller (davem@redhat.com) | |
13 | * | |
14 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/module.h> |
18 | #include <linux/types.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/hdreg.h> | |
22 | #include <linux/ide.h> | |
23 | #include <linux/init.h> | |
24 | ||
25 | #include <asm/io.h> | |
26 | ||
27 | #define DISPLAY_CMD64X_TIMINGS | |
28 | ||
29 | #define CMD_DEBUG 0 | |
30 | ||
31 | #if CMD_DEBUG | |
32 | #define cmdprintk(x...) printk(x) | |
33 | #else | |
34 | #define cmdprintk(x...) | |
35 | #endif | |
36 | ||
37 | /* | |
38 | * CMD64x specific registers definition. | |
39 | */ | |
40 | #define CFR 0x50 | |
41 | #define CFR_INTR_CH0 0x02 | |
42 | #define CNTRL 0x51 | |
43 | #define CNTRL_DIS_RA0 0x40 | |
44 | #define CNTRL_DIS_RA1 0x80 | |
45 | #define CNTRL_ENA_2ND 0x08 | |
46 | ||
47 | #define CMDTIM 0x52 | |
48 | #define ARTTIM0 0x53 | |
49 | #define DRWTIM0 0x54 | |
50 | #define ARTTIM1 0x55 | |
51 | #define DRWTIM1 0x56 | |
52 | #define ARTTIM23 0x57 | |
53 | #define ARTTIM23_DIS_RA2 0x04 | |
54 | #define ARTTIM23_DIS_RA3 0x08 | |
55 | #define ARTTIM23_INTR_CH1 0x10 | |
56 | #define ARTTIM2 0x57 | |
57 | #define ARTTIM3 0x57 | |
58 | #define DRWTIM23 0x58 | |
59 | #define DRWTIM2 0x58 | |
60 | #define BRST 0x59 | |
61 | #define DRWTIM3 0x5b | |
62 | ||
63 | #define BMIDECR0 0x70 | |
64 | #define MRDMODE 0x71 | |
65 | #define MRDMODE_INTR_CH0 0x04 | |
66 | #define MRDMODE_INTR_CH1 0x08 | |
67 | #define MRDMODE_BLK_CH0 0x10 | |
68 | #define MRDMODE_BLK_CH1 0x20 | |
69 | #define BMIDESR0 0x72 | |
70 | #define UDIDETCR0 0x73 | |
71 | #define DTPR0 0x74 | |
72 | #define BMIDECR1 0x78 | |
73 | #define BMIDECSR 0x79 | |
74 | #define BMIDESR1 0x7A | |
75 | #define UDIDETCR1 0x7B | |
76 | #define DTPR1 0x7C | |
77 | ||
78 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) | |
79 | #include <linux/stat.h> | |
80 | #include <linux/proc_fs.h> | |
81 | ||
82 | static u8 cmd64x_proc = 0; | |
83 | ||
84 | #define CMD_MAX_DEVS 5 | |
85 | ||
86 | static struct pci_dev *cmd_devs[CMD_MAX_DEVS]; | |
87 | static int n_cmd_devs; | |
88 | ||
89 | static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index) | |
90 | { | |
91 | char *p = buf; | |
92 | ||
93 | u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0; /* primary */ | |
94 | u8 reg57 = 0, reg58 = 0, reg5b; /* secondary */ | |
95 | u8 reg72 = 0, reg73 = 0; /* primary */ | |
96 | u8 reg7a = 0, reg7b = 0; /* secondary */ | |
97 | u8 reg50 = 0, reg71 = 0; /* extra */ | |
98 | ||
99 | p += sprintf(p, "\nController: %d\n", index); | |
100 | p += sprintf(p, "CMD%x Chipset.\n", dev->device); | |
101 | (void) pci_read_config_byte(dev, CFR, ®50); | |
102 | (void) pci_read_config_byte(dev, ARTTIM0, ®53); | |
103 | (void) pci_read_config_byte(dev, DRWTIM0, ®54); | |
104 | (void) pci_read_config_byte(dev, ARTTIM1, ®55); | |
105 | (void) pci_read_config_byte(dev, DRWTIM1, ®56); | |
106 | (void) pci_read_config_byte(dev, ARTTIM2, ®57); | |
107 | (void) pci_read_config_byte(dev, DRWTIM2, ®58); | |
108 | (void) pci_read_config_byte(dev, DRWTIM3, ®5b); | |
109 | (void) pci_read_config_byte(dev, MRDMODE, ®71); | |
110 | (void) pci_read_config_byte(dev, BMIDESR0, ®72); | |
111 | (void) pci_read_config_byte(dev, UDIDETCR0, ®73); | |
112 | (void) pci_read_config_byte(dev, BMIDESR1, ®7a); | |
113 | (void) pci_read_config_byte(dev, UDIDETCR1, ®7b); | |
114 | ||
115 | p += sprintf(p, "--------------- Primary Channel " | |
116 | "---------------- Secondary Channel " | |
117 | "-------------\n"); | |
118 | p += sprintf(p, " %sabled " | |
119 | " %sabled\n", | |
120 | (reg72&0x80)?"dis":" en", | |
121 | (reg7a&0x80)?"dis":" en"); | |
122 | p += sprintf(p, "--------------- drive0 " | |
123 | "--------- drive1 -------- drive0 " | |
124 | "---------- drive1 ------\n"); | |
125 | p += sprintf(p, "DMA enabled: %s %s" | |
126 | " %s %s\n", | |
127 | (reg72&0x20)?"yes":"no ", (reg72&0x40)?"yes":"no ", | |
128 | (reg7a&0x20)?"yes":"no ", (reg7a&0x40)?"yes":"no "); | |
129 | ||
130 | p += sprintf(p, "DMA Mode: %s(%s) %s(%s)", | |
131 | (reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO", | |
132 | (reg72&0x20)?( | |
133 | ((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"): | |
134 | ((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"): | |
135 | ((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"): | |
136 | ((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"): | |
137 | "X"):"?", | |
138 | (reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO", | |
139 | (reg72&0x40)?( | |
140 | ((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"): | |
141 | ((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"): | |
142 | ((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"): | |
143 | ((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"): | |
144 | "X"):"?"); | |
145 | p += sprintf(p, " %s(%s) %s(%s)\n", | |
146 | (reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO", | |
147 | (reg7a&0x20)?( | |
148 | ((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"): | |
149 | ((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"): | |
150 | ((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"): | |
151 | ((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"): | |
152 | "X"):"?", | |
153 | (reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO", | |
154 | (reg7a&0x40)?( | |
155 | ((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"): | |
156 | ((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"): | |
157 | ((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"): | |
158 | ((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"): | |
159 | "X"):"?" ); | |
160 | p += sprintf(p, "PIO Mode: %s %s" | |
161 | " %s %s\n", | |
162 | "?", "?", "?", "?"); | |
163 | p += sprintf(p, " %s %s\n", | |
164 | (reg50 & CFR_INTR_CH0) ? "interrupting" : "polling ", | |
165 | (reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling"); | |
166 | p += sprintf(p, " %s %s\n", | |
167 | (reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear ", | |
168 | (reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear"); | |
169 | p += sprintf(p, " %s %s\n", | |
170 | (reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled", | |
171 | (reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled"); | |
172 | ||
173 | return (char *)p; | |
174 | } | |
175 | ||
176 | static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count) | |
177 | { | |
178 | char *p = buffer; | |
179 | int i; | |
180 | ||
181 | p += sprintf(p, "\n"); | |
182 | for (i = 0; i < n_cmd_devs; i++) { | |
183 | struct pci_dev *dev = cmd_devs[i]; | |
184 | p = print_cmd64x_get_info(p, dev, i); | |
185 | } | |
186 | return p-buffer; /* => must be less than 4k! */ | |
187 | } | |
188 | ||
189 | #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */ | |
190 | ||
1da177e4 LT |
191 | /* |
192 | * This routine writes the prepared setup/active/recovery counts | |
193 | * for a drive into the cmd646 chipset registers to active them. | |
194 | */ | |
195 | static void program_drive_counts (ide_drive_t *drive, int setup_count, int active_count, int recovery_count) | |
196 | { | |
197 | unsigned long flags; | |
198 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
199 | ide_drive_t *drives = HWIF(drive)->drives; | |
200 | u8 temp_b; | |
201 | static const u8 setup_counts[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0}; | |
202 | static const u8 recovery_counts[] = | |
203 | {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; | |
204 | static const u8 arttim_regs[2][2] = { | |
205 | { ARTTIM0, ARTTIM1 }, | |
206 | { ARTTIM23, ARTTIM23 } | |
207 | }; | |
208 | static const u8 drwtim_regs[2][2] = { | |
209 | { DRWTIM0, DRWTIM1 }, | |
210 | { DRWTIM2, DRWTIM3 } | |
211 | }; | |
212 | int channel = (int) HWIF(drive)->channel; | |
213 | int slave = (drives != drive); /* Is this really the best way to determine this?? */ | |
214 | ||
215 | cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n", | |
216 | setup_count, active_count, recovery_count, drive->present); | |
217 | /* | |
218 | * Set up address setup count registers. | |
219 | * Primary interface has individual count/timing registers for | |
220 | * each drive. Secondary interface has one common set of registers, | |
221 | * for address setup so we merge these timings, using the slowest | |
222 | * value. | |
223 | */ | |
224 | if (channel) { | |
225 | drive->drive_data = setup_count; | |
226 | setup_count = max(drives[0].drive_data, | |
227 | drives[1].drive_data); | |
228 | cmdprintk("Secondary interface, setup_count = %d\n", | |
229 | setup_count); | |
230 | } | |
231 | ||
232 | /* | |
233 | * Convert values to internal chipset representation | |
234 | */ | |
235 | setup_count = (setup_count > 5) ? 0xc0 : (int) setup_counts[setup_count]; | |
236 | active_count &= 0xf; /* Remember, max value is 16 */ | |
237 | recovery_count = (int) recovery_counts[recovery_count]; | |
238 | ||
239 | cmdprintk("Final values = %d,%d,%d\n", | |
240 | setup_count, active_count, recovery_count); | |
241 | ||
242 | /* | |
243 | * Now that everything is ready, program the new timings | |
244 | */ | |
245 | local_irq_save(flags); | |
246 | /* | |
247 | * Program the address_setup clocks into ARTTIM reg, | |
248 | * and then the active/recovery counts into the DRWTIM reg | |
249 | */ | |
250 | (void) pci_read_config_byte(dev, arttim_regs[channel][slave], &temp_b); | |
251 | (void) pci_write_config_byte(dev, arttim_regs[channel][slave], | |
252 | ((u8) setup_count) | (temp_b & 0x3f)); | |
253 | (void) pci_write_config_byte(dev, drwtim_regs[channel][slave], | |
254 | (u8) ((active_count << 4) | recovery_count)); | |
255 | cmdprintk ("Write %x to %x\n", | |
256 | ((u8) setup_count) | (temp_b & 0x3f), | |
257 | arttim_regs[channel][slave]); | |
258 | cmdprintk ("Write %x to %x\n", | |
259 | (u8) ((active_count << 4) | recovery_count), | |
260 | drwtim_regs[channel][slave]); | |
261 | local_irq_restore(flags); | |
262 | } | |
263 | ||
264 | /* | |
265 | * Attempts to set the interface PIO mode. | |
266 | * The preferred method of selecting PIO modes (e.g. mode 4) is | |
267 | * "echo 'piomode:4' > /proc/ide/hdx/settings". Special cases are | |
268 | * 8: prefetch off, 9: prefetch on, 255: auto-select best mode. | |
269 | * Called with 255 at boot time. | |
270 | */ | |
271 | ||
272 | static void cmd64x_tuneproc (ide_drive_t *drive, u8 mode_wanted) | |
273 | { | |
274 | int setup_time, active_time, recovery_time; | |
275 | int clock_time, pio_mode, cycle_time; | |
276 | u8 recovery_count2, cycle_count; | |
277 | int setup_count, active_count, recovery_count; | |
278 | int bus_speed = system_bus_clock(); | |
279 | /*byte b;*/ | |
280 | ide_pio_data_t d; | |
281 | ||
282 | switch (mode_wanted) { | |
283 | case 8: /* set prefetch off */ | |
284 | case 9: /* set prefetch on */ | |
285 | mode_wanted &= 1; | |
286 | /*set_prefetch_mode(index, mode_wanted);*/ | |
287 | cmdprintk("%s: %sabled cmd640 prefetch\n", | |
288 | drive->name, mode_wanted ? "en" : "dis"); | |
289 | return; | |
290 | } | |
291 | ||
292 | mode_wanted = ide_get_best_pio_mode (drive, mode_wanted, 5, &d); | |
293 | pio_mode = d.pio_mode; | |
294 | cycle_time = d.cycle_time; | |
295 | ||
296 | /* | |
297 | * I copied all this complicated stuff from cmd640.c and made a few | |
298 | * minor changes. For now I am just going to pray that it is correct. | |
299 | */ | |
300 | if (pio_mode > 5) | |
301 | pio_mode = 5; | |
302 | setup_time = ide_pio_timings[pio_mode].setup_time; | |
303 | active_time = ide_pio_timings[pio_mode].active_time; | |
304 | recovery_time = cycle_time - (setup_time + active_time); | |
305 | clock_time = 1000 / bus_speed; | |
306 | cycle_count = (cycle_time + clock_time - 1) / clock_time; | |
307 | ||
308 | setup_count = (setup_time + clock_time - 1) / clock_time; | |
309 | ||
310 | active_count = (active_time + clock_time - 1) / clock_time; | |
311 | ||
312 | recovery_count = (recovery_time + clock_time - 1) / clock_time; | |
313 | recovery_count2 = cycle_count - (setup_count + active_count); | |
314 | if (recovery_count2 > recovery_count) | |
315 | recovery_count = recovery_count2; | |
316 | if (recovery_count > 16) { | |
317 | active_count += recovery_count - 16; | |
318 | recovery_count = 16; | |
319 | } | |
320 | if (active_count > 16) | |
321 | active_count = 16; /* maximum allowed by cmd646 */ | |
322 | ||
323 | /* | |
324 | * In a perfect world, we might set the drive pio mode here | |
325 | * (using WIN_SETFEATURE) before continuing. | |
326 | * | |
327 | * But we do not, because: | |
328 | * 1) this is the wrong place to do it | |
329 | * (proper is do_special() in ide.c) | |
330 | * 2) in practice this is rarely, if ever, necessary | |
331 | */ | |
332 | program_drive_counts (drive, setup_count, active_count, recovery_count); | |
333 | ||
334 | cmdprintk("%s: selected cmd646 PIO mode%d : %d (%dns)%s, " | |
335 | "clocks=%d/%d/%d\n", | |
336 | drive->name, pio_mode, mode_wanted, cycle_time, | |
337 | d.overridden ? " (overriding vendor mode)" : "", | |
338 | setup_count, active_count, recovery_count); | |
339 | } | |
340 | ||
341 | static u8 cmd64x_ratemask (ide_drive_t *drive) | |
342 | { | |
343 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
344 | u8 mode = 0; | |
345 | ||
346 | switch(dev->device) { | |
347 | case PCI_DEVICE_ID_CMD_649: | |
348 | mode = 3; | |
349 | break; | |
350 | case PCI_DEVICE_ID_CMD_648: | |
351 | mode = 2; | |
352 | break; | |
353 | case PCI_DEVICE_ID_CMD_643: | |
354 | return 0; | |
355 | ||
356 | case PCI_DEVICE_ID_CMD_646: | |
357 | { | |
358 | unsigned int class_rev = 0; | |
359 | pci_read_config_dword(dev, | |
360 | PCI_CLASS_REVISION, &class_rev); | |
361 | class_rev &= 0xff; | |
362 | /* | |
363 | * UltraDMA only supported on PCI646U and PCI646U2, which | |
364 | * correspond to revisions 0x03, 0x05 and 0x07 respectively. | |
365 | * Actually, although the CMD tech support people won't | |
366 | * tell me the details, the 0x03 revision cannot support | |
367 | * UDMA correctly without hardware modifications, and even | |
368 | * then it only works with Quantum disks due to some | |
369 | * hold time assumptions in the 646U part which are fixed | |
370 | * in the 646U2. | |
371 | * | |
372 | * So we only do UltraDMA on revision 0x05 and 0x07 chipsets. | |
373 | */ | |
374 | switch(class_rev) { | |
375 | case 0x07: | |
376 | case 0x05: | |
377 | return 1; | |
378 | case 0x03: | |
379 | case 0x01: | |
380 | default: | |
381 | return 0; | |
382 | } | |
383 | } | |
384 | } | |
385 | if (!eighty_ninty_three(drive)) | |
386 | mode = min(mode, (u8)1); | |
387 | return mode; | |
388 | } | |
389 | ||
390 | static void config_cmd64x_chipset_for_pio (ide_drive_t *drive, u8 set_speed) | |
391 | { | |
392 | u8 speed = 0x00; | |
393 | u8 set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL); | |
394 | ||
395 | cmd64x_tuneproc(drive, set_pio); | |
396 | speed = XFER_PIO_0 + set_pio; | |
397 | if (set_speed) | |
398 | (void) ide_config_drive_speed(drive, speed); | |
399 | } | |
400 | ||
401 | static void config_chipset_for_pio (ide_drive_t *drive, u8 set_speed) | |
402 | { | |
403 | config_cmd64x_chipset_for_pio(drive, set_speed); | |
404 | } | |
405 | ||
406 | static int cmd64x_tune_chipset (ide_drive_t *drive, u8 xferspeed) | |
407 | { | |
408 | ide_hwif_t *hwif = HWIF(drive); | |
409 | struct pci_dev *dev = hwif->pci_dev; | |
410 | ||
411 | u8 unit = (drive->select.b.unit & 0x01); | |
412 | u8 regU = 0, pciU = (hwif->channel) ? UDIDETCR1 : UDIDETCR0; | |
413 | u8 regD = 0, pciD = (hwif->channel) ? BMIDESR1 : BMIDESR0; | |
414 | ||
415 | u8 speed = ide_rate_filter(cmd64x_ratemask(drive), xferspeed); | |
416 | ||
417 | if (speed > XFER_PIO_4) { | |
418 | (void) pci_read_config_byte(dev, pciD, ®D); | |
419 | (void) pci_read_config_byte(dev, pciU, ®U); | |
420 | regD &= ~(unit ? 0x40 : 0x20); | |
421 | regU &= ~(unit ? 0xCA : 0x35); | |
422 | (void) pci_write_config_byte(dev, pciD, regD); | |
423 | (void) pci_write_config_byte(dev, pciU, regU); | |
424 | (void) pci_read_config_byte(dev, pciD, ®D); | |
425 | (void) pci_read_config_byte(dev, pciU, ®U); | |
426 | } | |
427 | ||
428 | switch(speed) { | |
429 | case XFER_UDMA_5: regU |= (unit ? 0x0A : 0x05); break; | |
430 | case XFER_UDMA_4: regU |= (unit ? 0x4A : 0x15); break; | |
431 | case XFER_UDMA_3: regU |= (unit ? 0x8A : 0x25); break; | |
432 | case XFER_UDMA_2: regU |= (unit ? 0x42 : 0x11); break; | |
433 | case XFER_UDMA_1: regU |= (unit ? 0x82 : 0x21); break; | |
434 | case XFER_UDMA_0: regU |= (unit ? 0xC2 : 0x31); break; | |
435 | case XFER_MW_DMA_2: regD |= (unit ? 0x40 : 0x10); break; | |
436 | case XFER_MW_DMA_1: regD |= (unit ? 0x80 : 0x20); break; | |
437 | case XFER_MW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break; | |
438 | case XFER_SW_DMA_2: regD |= (unit ? 0x40 : 0x10); break; | |
439 | case XFER_SW_DMA_1: regD |= (unit ? 0x80 : 0x20); break; | |
440 | case XFER_SW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break; | |
441 | case XFER_PIO_4: cmd64x_tuneproc(drive, 4); break; | |
442 | case XFER_PIO_3: cmd64x_tuneproc(drive, 3); break; | |
443 | case XFER_PIO_2: cmd64x_tuneproc(drive, 2); break; | |
444 | case XFER_PIO_1: cmd64x_tuneproc(drive, 1); break; | |
445 | case XFER_PIO_0: cmd64x_tuneproc(drive, 0); break; | |
446 | ||
447 | default: | |
448 | return 1; | |
449 | } | |
450 | ||
451 | if (speed > XFER_PIO_4) { | |
452 | (void) pci_write_config_byte(dev, pciU, regU); | |
453 | regD |= (unit ? 0x40 : 0x20); | |
454 | (void) pci_write_config_byte(dev, pciD, regD); | |
455 | } | |
456 | ||
457 | return (ide_config_drive_speed(drive, speed)); | |
458 | } | |
459 | ||
460 | static int config_chipset_for_dma (ide_drive_t *drive) | |
461 | { | |
462 | u8 speed = ide_dma_speed(drive, cmd64x_ratemask(drive)); | |
463 | ||
464 | config_chipset_for_pio(drive, !speed); | |
465 | ||
466 | if (!speed) | |
467 | return 0; | |
468 | ||
056a697b BZ |
469 | if (cmd64x_tune_chipset(drive, speed)) |
470 | return 0; | |
1da177e4 LT |
471 | |
472 | return ide_dma_enable(drive); | |
473 | } | |
474 | ||
475 | static int cmd64x_config_drive_for_dma (ide_drive_t *drive) | |
476 | { | |
7569e8dc | 477 | if (ide_use_dma(drive) && config_chipset_for_dma(drive)) |
3608b5d7 | 478 | return 0; |
1da177e4 | 479 | |
d8f4469d | 480 | if (ide_use_fast_pio(drive)) |
1da177e4 | 481 | config_chipset_for_pio(drive, 1); |
d8f4469d | 482 | |
3608b5d7 | 483 | return -1; |
1da177e4 LT |
484 | } |
485 | ||
486 | static int cmd64x_alt_dma_status (struct pci_dev *dev) | |
487 | { | |
488 | switch(dev->device) { | |
489 | case PCI_DEVICE_ID_CMD_648: | |
490 | case PCI_DEVICE_ID_CMD_649: | |
491 | return 1; | |
492 | default: | |
493 | break; | |
494 | } | |
495 | return 0; | |
496 | } | |
497 | ||
498 | static int cmd64x_ide_dma_end (ide_drive_t *drive) | |
499 | { | |
500 | u8 dma_stat = 0, dma_cmd = 0; | |
501 | ide_hwif_t *hwif = HWIF(drive); | |
502 | struct pci_dev *dev = hwif->pci_dev; | |
503 | ||
504 | drive->waiting_for_dma = 0; | |
505 | /* read DMA command state */ | |
0ecdca26 | 506 | dma_cmd = inb(hwif->dma_command); |
1da177e4 | 507 | /* stop DMA */ |
0ecdca26 | 508 | outb(dma_cmd & ~1, hwif->dma_command); |
1da177e4 | 509 | /* get DMA status */ |
0ecdca26 | 510 | dma_stat = inb(hwif->dma_status); |
1da177e4 | 511 | /* clear the INTR & ERROR bits */ |
0ecdca26 | 512 | outb(dma_stat | 6, hwif->dma_status); |
1da177e4 LT |
513 | if (cmd64x_alt_dma_status(dev)) { |
514 | u8 dma_intr = 0; | |
515 | u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 : | |
516 | CFR_INTR_CH0; | |
517 | u8 dma_reg = (hwif->channel) ? ARTTIM2 : CFR; | |
518 | (void) pci_read_config_byte(dev, dma_reg, &dma_intr); | |
519 | /* clear the INTR bit */ | |
520 | (void) pci_write_config_byte(dev, dma_reg, dma_intr|dma_mask); | |
521 | } | |
522 | /* purge DMA mappings */ | |
523 | ide_destroy_dmatable(drive); | |
524 | /* verify good DMA status */ | |
525 | return (dma_stat & 7) != 4; | |
526 | } | |
527 | ||
528 | static int cmd64x_ide_dma_test_irq (ide_drive_t *drive) | |
529 | { | |
530 | ide_hwif_t *hwif = HWIF(drive); | |
531 | struct pci_dev *dev = hwif->pci_dev; | |
532 | u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 : | |
533 | MRDMODE_INTR_CH0; | |
0ecdca26 | 534 | u8 dma_stat = inb(hwif->dma_status); |
1da177e4 LT |
535 | |
536 | (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat); | |
537 | #ifdef DEBUG | |
538 | printk("%s: dma_stat: 0x%02x dma_alt_stat: " | |
539 | "0x%02x mask: 0x%02x\n", drive->name, | |
540 | dma_stat, dma_alt_stat, mask); | |
541 | #endif | |
542 | if (!(dma_alt_stat & mask)) | |
543 | return 0; | |
544 | ||
545 | /* return 1 if INTR asserted */ | |
546 | if ((dma_stat & 4) == 4) | |
547 | return 1; | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | /* | |
553 | * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old | |
554 | * event order for DMA transfers. | |
555 | */ | |
556 | ||
557 | static int cmd646_1_ide_dma_end (ide_drive_t *drive) | |
558 | { | |
559 | ide_hwif_t *hwif = HWIF(drive); | |
560 | u8 dma_stat = 0, dma_cmd = 0; | |
561 | ||
562 | drive->waiting_for_dma = 0; | |
563 | /* get DMA status */ | |
0ecdca26 | 564 | dma_stat = inb(hwif->dma_status); |
1da177e4 | 565 | /* read DMA command state */ |
0ecdca26 | 566 | dma_cmd = inb(hwif->dma_command); |
1da177e4 | 567 | /* stop DMA */ |
0ecdca26 | 568 | outb(dma_cmd & ~1, hwif->dma_command); |
1da177e4 | 569 | /* clear the INTR & ERROR bits */ |
0ecdca26 | 570 | outb(dma_stat | 6, hwif->dma_status); |
1da177e4 LT |
571 | /* and free any DMA resources */ |
572 | ide_destroy_dmatable(drive); | |
573 | /* verify good DMA status */ | |
574 | return (dma_stat & 7) != 4; | |
575 | } | |
576 | ||
577 | static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name) | |
578 | { | |
579 | u32 class_rev = 0; | |
580 | u8 mrdmode = 0; | |
581 | ||
582 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
583 | class_rev &= 0xff; | |
584 | ||
1da177e4 LT |
585 | switch(dev->device) { |
586 | case PCI_DEVICE_ID_CMD_643: | |
587 | break; | |
588 | case PCI_DEVICE_ID_CMD_646: | |
589 | printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev); | |
590 | switch(class_rev) { | |
591 | case 0x07: | |
592 | case 0x05: | |
593 | printk("UltraDMA Capable"); | |
594 | break; | |
595 | case 0x03: | |
596 | printk("MultiWord DMA Force Limited"); | |
597 | break; | |
598 | case 0x01: | |
599 | default: | |
600 | printk("MultiWord DMA Limited, IRQ workaround enabled"); | |
601 | break; | |
602 | } | |
603 | printk("\n"); | |
604 | break; | |
605 | case PCI_DEVICE_ID_CMD_648: | |
606 | case PCI_DEVICE_ID_CMD_649: | |
607 | break; | |
608 | default: | |
609 | break; | |
610 | } | |
611 | ||
612 | /* Set a good latency timer and cache line size value. */ | |
613 | (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); | |
614 | /* FIXME: pci_set_master() to ensure a good latency timer value */ | |
615 | ||
616 | /* Setup interrupts. */ | |
617 | (void) pci_read_config_byte(dev, MRDMODE, &mrdmode); | |
618 | mrdmode &= ~(0x30); | |
619 | (void) pci_write_config_byte(dev, MRDMODE, mrdmode); | |
620 | ||
621 | /* Use MEMORY READ LINE for reads. | |
622 | * NOTE: Although not mentioned in the PCI0646U specs, | |
623 | * these bits are write only and won't be read | |
624 | * back as set or not. The PCI0646U2 specs clarify | |
625 | * this point. | |
626 | */ | |
627 | (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02); | |
628 | ||
629 | /* Set reasonable active/recovery/address-setup values. */ | |
630 | (void) pci_write_config_byte(dev, ARTTIM0, 0x40); | |
631 | (void) pci_write_config_byte(dev, DRWTIM0, 0x3f); | |
632 | (void) pci_write_config_byte(dev, ARTTIM1, 0x40); | |
633 | (void) pci_write_config_byte(dev, DRWTIM1, 0x3f); | |
634 | #ifdef __i386__ | |
635 | (void) pci_write_config_byte(dev, ARTTIM23, 0x1c); | |
636 | #else | |
637 | (void) pci_write_config_byte(dev, ARTTIM23, 0x5c); | |
638 | #endif | |
639 | (void) pci_write_config_byte(dev, DRWTIM23, 0x3f); | |
640 | (void) pci_write_config_byte(dev, DRWTIM3, 0x3f); | |
641 | #ifdef CONFIG_PPC | |
642 | (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0); | |
643 | #endif /* CONFIG_PPC */ | |
644 | ||
645 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) | |
646 | ||
647 | cmd_devs[n_cmd_devs++] = dev; | |
648 | ||
649 | if (!cmd64x_proc) { | |
650 | cmd64x_proc = 1; | |
651 | ide_pci_create_host_proc("cmd64x", cmd64x_get_info); | |
652 | } | |
653 | #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */ | |
654 | ||
655 | return 0; | |
656 | } | |
657 | ||
658 | static unsigned int __devinit ata66_cmd64x(ide_hwif_t *hwif) | |
659 | { | |
660 | u8 ata66 = 0, mask = (hwif->channel) ? 0x02 : 0x01; | |
661 | ||
662 | switch(hwif->pci_dev->device) { | |
663 | case PCI_DEVICE_ID_CMD_643: | |
664 | case PCI_DEVICE_ID_CMD_646: | |
665 | return ata66; | |
666 | default: | |
667 | break; | |
668 | } | |
669 | pci_read_config_byte(hwif->pci_dev, BMIDECSR, &ata66); | |
670 | return (ata66 & mask) ? 1 : 0; | |
671 | } | |
672 | ||
673 | static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif) | |
674 | { | |
675 | struct pci_dev *dev = hwif->pci_dev; | |
676 | unsigned int class_rev; | |
677 | ||
678 | hwif->autodma = 0; | |
679 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
680 | class_rev &= 0xff; | |
681 | ||
682 | hwif->tuneproc = &cmd64x_tuneproc; | |
683 | hwif->speedproc = &cmd64x_tune_chipset; | |
684 | ||
685 | if (!hwif->dma_base) { | |
686 | hwif->drives[0].autotune = 1; | |
687 | hwif->drives[1].autotune = 1; | |
688 | return; | |
689 | } | |
690 | ||
691 | hwif->atapi_dma = 1; | |
692 | ||
693 | hwif->ultra_mask = 0x3f; | |
694 | hwif->mwdma_mask = 0x07; | |
695 | hwif->swdma_mask = 0x07; | |
696 | ||
697 | if (dev->device == PCI_DEVICE_ID_CMD_643) | |
698 | hwif->ultra_mask = 0x80; | |
699 | if (dev->device == PCI_DEVICE_ID_CMD_646) | |
700 | hwif->ultra_mask = (class_rev > 0x04) ? 0x07 : 0x80; | |
701 | if (dev->device == PCI_DEVICE_ID_CMD_648) | |
702 | hwif->ultra_mask = 0x1f; | |
703 | ||
704 | hwif->ide_dma_check = &cmd64x_config_drive_for_dma; | |
705 | if (!(hwif->udma_four)) | |
706 | hwif->udma_four = ata66_cmd64x(hwif); | |
707 | ||
708 | if (dev->device == PCI_DEVICE_ID_CMD_646) { | |
709 | hwif->chipset = ide_cmd646; | |
710 | if (class_rev == 0x01) { | |
711 | hwif->ide_dma_end = &cmd646_1_ide_dma_end; | |
712 | } else { | |
713 | hwif->ide_dma_end = &cmd64x_ide_dma_end; | |
714 | hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq; | |
715 | } | |
716 | } else { | |
717 | hwif->ide_dma_end = &cmd64x_ide_dma_end; | |
718 | hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq; | |
719 | } | |
720 | ||
721 | ||
722 | if (!noautodma) | |
723 | hwif->autodma = 1; | |
724 | hwif->drives[0].autodma = hwif->autodma; | |
725 | hwif->drives[1].autodma = hwif->autodma; | |
726 | } | |
727 | ||
728 | static ide_pci_device_t cmd64x_chipsets[] __devinitdata = { | |
729 | { /* 0 */ | |
730 | .name = "CMD643", | |
731 | .init_chipset = init_chipset_cmd64x, | |
732 | .init_hwif = init_hwif_cmd64x, | |
733 | .channels = 2, | |
734 | .autodma = AUTODMA, | |
735 | .bootable = ON_BOARD, | |
736 | },{ /* 1 */ | |
737 | .name = "CMD646", | |
738 | .init_chipset = init_chipset_cmd64x, | |
739 | .init_hwif = init_hwif_cmd64x, | |
740 | .channels = 2, | |
741 | .autodma = AUTODMA, | |
742 | .enablebits = {{0x00,0x00,0x00}, {0x51,0x80,0x80}}, | |
743 | .bootable = ON_BOARD, | |
744 | },{ /* 2 */ | |
745 | .name = "CMD648", | |
746 | .init_chipset = init_chipset_cmd64x, | |
747 | .init_hwif = init_hwif_cmd64x, | |
748 | .channels = 2, | |
749 | .autodma = AUTODMA, | |
750 | .bootable = ON_BOARD, | |
751 | },{ /* 3 */ | |
752 | .name = "CMD649", | |
753 | .init_chipset = init_chipset_cmd64x, | |
754 | .init_hwif = init_hwif_cmd64x, | |
755 | .channels = 2, | |
756 | .autodma = AUTODMA, | |
757 | .bootable = ON_BOARD, | |
758 | } | |
759 | }; | |
760 | ||
761 | static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
762 | { | |
763 | return ide_setup_pci_device(dev, &cmd64x_chipsets[id->driver_data]); | |
764 | } | |
765 | ||
766 | static struct pci_device_id cmd64x_pci_tbl[] = { | |
767 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
768 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, | |
769 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
770 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, | |
771 | { 0, }, | |
772 | }; | |
773 | MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl); | |
774 | ||
775 | static struct pci_driver driver = { | |
776 | .name = "CMD64x_IDE", | |
777 | .id_table = cmd64x_pci_tbl, | |
778 | .probe = cmd64x_init_one, | |
779 | }; | |
780 | ||
82ab1eec | 781 | static int __init cmd64x_ide_init(void) |
1da177e4 LT |
782 | { |
783 | return ide_pci_register_driver(&driver); | |
784 | } | |
785 | ||
786 | module_init(cmd64x_ide_init); | |
787 | ||
788 | MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick"); | |
789 | MODULE_DESCRIPTION("PCI driver module for CMD64x IDE"); | |
790 | MODULE_LICENSE("GPL"); |