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60e7a82f | 1 | /* |
66602c83 | 2 | * linux/drivers/ide/pci/cmd64x.c Version 1.47 Mar 19, 2007 |
1da177e4 LT |
3 | * |
4 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. | |
1da177e4 LT |
5 | * Due to massive hardware bugs, UltraDMA is only supported |
6 | * on the 646U2 and not on the 646U. | |
7 | * | |
8 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
9 | * Copyright (C) 1998 David S. Miller (davem@redhat.com) | |
10 | * | |
11 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> | |
f92d50e6 | 12 | * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 LT |
13 | */ |
14 | ||
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/types.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/hdreg.h> | |
20 | #include <linux/ide.h> | |
21 | #include <linux/init.h> | |
22 | ||
23 | #include <asm/io.h> | |
24 | ||
25 | #define DISPLAY_CMD64X_TIMINGS | |
26 | ||
27 | #define CMD_DEBUG 0 | |
28 | ||
29 | #if CMD_DEBUG | |
30 | #define cmdprintk(x...) printk(x) | |
31 | #else | |
32 | #define cmdprintk(x...) | |
33 | #endif | |
34 | ||
35 | /* | |
36 | * CMD64x specific registers definition. | |
37 | */ | |
38 | #define CFR 0x50 | |
e51e2528 | 39 | #define CFR_INTR_CH0 0x04 |
1da177e4 | 40 | #define CNTRL 0x51 |
5826b318 SS |
41 | #define CNTRL_ENA_1ST 0x04 |
42 | #define CNTRL_ENA_2ND 0x08 | |
43 | #define CNTRL_DIS_RA0 0x40 | |
44 | #define CNTRL_DIS_RA1 0x80 | |
1da177e4 LT |
45 | |
46 | #define CMDTIM 0x52 | |
47 | #define ARTTIM0 0x53 | |
48 | #define DRWTIM0 0x54 | |
49 | #define ARTTIM1 0x55 | |
50 | #define DRWTIM1 0x56 | |
51 | #define ARTTIM23 0x57 | |
52 | #define ARTTIM23_DIS_RA2 0x04 | |
53 | #define ARTTIM23_DIS_RA3 0x08 | |
54 | #define ARTTIM23_INTR_CH1 0x10 | |
55 | #define ARTTIM2 0x57 | |
56 | #define ARTTIM3 0x57 | |
57 | #define DRWTIM23 0x58 | |
58 | #define DRWTIM2 0x58 | |
59 | #define BRST 0x59 | |
60 | #define DRWTIM3 0x5b | |
61 | ||
62 | #define BMIDECR0 0x70 | |
63 | #define MRDMODE 0x71 | |
64 | #define MRDMODE_INTR_CH0 0x04 | |
65 | #define MRDMODE_INTR_CH1 0x08 | |
66 | #define MRDMODE_BLK_CH0 0x10 | |
67 | #define MRDMODE_BLK_CH1 0x20 | |
68 | #define BMIDESR0 0x72 | |
69 | #define UDIDETCR0 0x73 | |
70 | #define DTPR0 0x74 | |
71 | #define BMIDECR1 0x78 | |
72 | #define BMIDECSR 0x79 | |
73 | #define BMIDESR1 0x7A | |
74 | #define UDIDETCR1 0x7B | |
75 | #define DTPR1 0x7C | |
76 | ||
ecfd80e4 | 77 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) |
1da177e4 LT |
78 | #include <linux/stat.h> |
79 | #include <linux/proc_fs.h> | |
80 | ||
81 | static u8 cmd64x_proc = 0; | |
82 | ||
83 | #define CMD_MAX_DEVS 5 | |
84 | ||
85 | static struct pci_dev *cmd_devs[CMD_MAX_DEVS]; | |
86 | static int n_cmd_devs; | |
87 | ||
88 | static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index) | |
89 | { | |
90 | char *p = buf; | |
1da177e4 LT |
91 | u8 reg72 = 0, reg73 = 0; /* primary */ |
92 | u8 reg7a = 0, reg7b = 0; /* secondary */ | |
5826b318 SS |
93 | u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */ |
94 | u8 rev = 0; | |
1da177e4 LT |
95 | |
96 | p += sprintf(p, "\nController: %d\n", index); | |
5826b318 SS |
97 | p += sprintf(p, "PCI-%x Chipset.\n", dev->device); |
98 | ||
1da177e4 | 99 | (void) pci_read_config_byte(dev, CFR, ®50); |
5826b318 SS |
100 | (void) pci_read_config_byte(dev, CNTRL, ®51); |
101 | (void) pci_read_config_byte(dev, ARTTIM23, ®57); | |
1da177e4 LT |
102 | (void) pci_read_config_byte(dev, MRDMODE, ®71); |
103 | (void) pci_read_config_byte(dev, BMIDESR0, ®72); | |
104 | (void) pci_read_config_byte(dev, UDIDETCR0, ®73); | |
105 | (void) pci_read_config_byte(dev, BMIDESR1, ®7a); | |
106 | (void) pci_read_config_byte(dev, UDIDETCR1, ®7b); | |
107 | ||
5826b318 SS |
108 | /* PCI0643/6 originally didn't have the primary channel enable bit */ |
109 | (void) pci_read_config_byte(dev, PCI_REVISION_ID, &rev); | |
110 | if ((dev->device == PCI_DEVICE_ID_CMD_643) || | |
111 | (dev->device == PCI_DEVICE_ID_CMD_646 && rev < 3)) | |
112 | reg51 |= CNTRL_ENA_1ST; | |
113 | ||
114 | p += sprintf(p, "---------------- Primary Channel " | |
115 | "---------------- Secondary Channel ------------\n"); | |
116 | p += sprintf(p, " %s %s\n", | |
117 | (reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled", | |
118 | (reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled"); | |
119 | p += sprintf(p, "---------------- drive0 --------- drive1 " | |
120 | "-------- drive0 --------- drive1 ------\n"); | |
121 | p += sprintf(p, "DMA enabled: %s %s" | |
122 | " %s %s\n", | |
123 | (reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ", | |
124 | (reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no "); | |
125 | p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)", | |
126 | ( reg73 & 0x01) ? " on" : "off", | |
127 | ((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') : | |
128 | ((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') : | |
129 | ((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') : | |
130 | ((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?', | |
131 | ( reg73 & 0x02) ? " on" : "off", | |
132 | ((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') : | |
133 | ((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') : | |
134 | ((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') : | |
135 | ((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?'); | |
136 | p += sprintf(p, " %s (%c) %s (%c)\n", | |
137 | ( reg7b & 0x01) ? " on" : "off", | |
138 | ((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') : | |
139 | ((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') : | |
140 | ((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') : | |
141 | ((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?', | |
142 | ( reg7b & 0x02) ? " on" : "off", | |
143 | ((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') : | |
144 | ((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') : | |
145 | ((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') : | |
146 | ((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?'); | |
147 | p += sprintf(p, "Interrupt: %s, %s %s, %s\n", | |
148 | (reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled", | |
149 | (reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ", | |
150 | (reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled", | |
151 | (reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear "); | |
1da177e4 LT |
152 | |
153 | return (char *)p; | |
154 | } | |
155 | ||
156 | static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count) | |
157 | { | |
158 | char *p = buffer; | |
159 | int i; | |
160 | ||
1da177e4 LT |
161 | for (i = 0; i < n_cmd_devs; i++) { |
162 | struct pci_dev *dev = cmd_devs[i]; | |
163 | p = print_cmd64x_get_info(p, dev, i); | |
164 | } | |
165 | return p-buffer; /* => must be less than 4k! */ | |
166 | } | |
167 | ||
ecfd80e4 | 168 | #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */ |
1da177e4 | 169 | |
e277a1aa SS |
170 | static u8 quantize_timing(int timing, int quant) |
171 | { | |
172 | return (timing + quant - 1) / quant; | |
173 | } | |
174 | ||
1da177e4 | 175 | /* |
60e7a82f SS |
176 | * This routine calculates active/recovery counts and then writes them into |
177 | * the chipset registers. | |
1da177e4 | 178 | */ |
60e7a82f | 179 | static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time) |
1da177e4 | 180 | { |
60e7a82f SS |
181 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
182 | int clock_time = 1000 / system_bus_clock(); | |
183 | u8 cycle_count, active_count, recovery_count, drwtim; | |
184 | static const u8 recovery_values[] = | |
1da177e4 | 185 | {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; |
60e7a82f SS |
186 | static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3}; |
187 | ||
188 | cmdprintk("program_cycle_times parameters: total=%d, active=%d\n", | |
189 | cycle_time, active_time); | |
190 | ||
191 | cycle_count = quantize_timing( cycle_time, clock_time); | |
192 | active_count = quantize_timing(active_time, clock_time); | |
193 | recovery_count = cycle_count - active_count; | |
194 | ||
1da177e4 | 195 | /* |
60e7a82f SS |
196 | * In case we've got too long recovery phase, try to lengthen |
197 | * the active phase | |
1da177e4 | 198 | */ |
60e7a82f SS |
199 | if (recovery_count > 16) { |
200 | active_count += recovery_count - 16; | |
201 | recovery_count = 16; | |
1da177e4 | 202 | } |
60e7a82f SS |
203 | if (active_count > 16) /* shouldn't actually happen... */ |
204 | active_count = 16; | |
205 | ||
206 | cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n", | |
207 | cycle_count, active_count, recovery_count); | |
1da177e4 LT |
208 | |
209 | /* | |
210 | * Convert values to internal chipset representation | |
211 | */ | |
60e7a82f SS |
212 | recovery_count = recovery_values[recovery_count]; |
213 | active_count &= 0x0f; | |
1da177e4 | 214 | |
60e7a82f SS |
215 | /* Program the active/recovery counts into the DRWTIM register */ |
216 | drwtim = (active_count << 4) | recovery_count; | |
217 | (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim); | |
218 | cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]); | |
1da177e4 LT |
219 | } |
220 | ||
221 | /* | |
60e7a82f SS |
222 | * This routine selects drive's best PIO mode and writes into the chipset |
223 | * registers setup/active/recovery timings. | |
1da177e4 | 224 | */ |
f92d50e6 | 225 | static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted) |
1da177e4 | 226 | { |
60e7a82f SS |
227 | ide_hwif_t *hwif = HWIF(drive); |
228 | struct pci_dev *dev = hwif->pci_dev; | |
e277a1aa | 229 | ide_pio_data_t pio; |
60e7a82f SS |
230 | u8 pio_mode, setup_count, arttim = 0; |
231 | static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0}; | |
232 | static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23}; | |
e277a1aa | 233 | pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio); |
1da177e4 | 234 | |
60e7a82f SS |
235 | cmdprintk("%s: PIO mode wanted %d, selected %d (%d ns)%s\n", |
236 | drive->name, mode_wanted, pio_mode, pio.cycle_time, | |
237 | pio.overridden ? " (overriding vendor mode)" : ""); | |
1da177e4 | 238 | |
60e7a82f SS |
239 | program_cycle_times(drive, pio.cycle_time, |
240 | ide_pio_timings[pio_mode].active_time); | |
1da177e4 | 241 | |
60e7a82f SS |
242 | setup_count = quantize_timing(ide_pio_timings[pio_mode].setup_time, |
243 | 1000 / system_bus_clock()); | |
244 | ||
245 | /* | |
246 | * The primary channel has individual address setup timing registers | |
247 | * for each drive and the hardware selects the slowest timing itself. | |
248 | * The secondary channel has one common register and we have to select | |
249 | * the slowest address setup timing ourselves. | |
250 | */ | |
251 | if (hwif->channel) { | |
252 | ide_drive_t *drives = hwif->drives; | |
253 | ||
254 | drive->drive_data = setup_count; | |
255 | setup_count = max(drives[0].drive_data, drives[1].drive_data); | |
1da177e4 | 256 | } |
1da177e4 | 257 | |
60e7a82f SS |
258 | if (setup_count > 5) /* shouldn't actually happen... */ |
259 | setup_count = 5; | |
260 | cmdprintk("Final address setup count: %d\n", setup_count); | |
1da177e4 | 261 | |
60e7a82f SS |
262 | /* |
263 | * Program the address setup clocks into the ARTTIM registers. | |
264 | * Avoid clearing the secondary channel's interrupt bit. | |
265 | */ | |
266 | (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim); | |
267 | if (hwif->channel) | |
268 | arttim &= ~ARTTIM23_INTR_CH1; | |
269 | arttim &= ~0xc0; | |
270 | arttim |= setup_values[setup_count]; | |
271 | (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim); | |
272 | cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]); | |
f92d50e6 SS |
273 | |
274 | return pio_mode; | |
275 | } | |
276 | ||
277 | /* | |
278 | * Attempts to set drive's PIO mode. | |
279 | * Special cases are 8: prefetch off, 9: prefetch on (both never worked), | |
280 | * and 255: auto-select best mode (used at boot time). | |
281 | */ | |
282 | static void cmd64x_tune_drive (ide_drive_t *drive, u8 pio) | |
283 | { | |
284 | /* | |
285 | * Filter out the prefetch control values | |
286 | * to prevent PIO5 from being programmed | |
287 | */ | |
288 | if (pio == 8 || pio == 9) | |
289 | return; | |
290 | ||
291 | pio = cmd64x_tune_pio(drive, pio); | |
292 | (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio); | |
1da177e4 LT |
293 | } |
294 | ||
60e7a82f | 295 | static int cmd64x_tune_chipset (ide_drive_t *drive, u8 speed) |
1da177e4 LT |
296 | { |
297 | ide_hwif_t *hwif = HWIF(drive); | |
298 | struct pci_dev *dev = hwif->pci_dev; | |
60e7a82f SS |
299 | u8 unit = drive->dn & 0x01; |
300 | u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0; | |
1da177e4 | 301 | |
2d5eaa6d | 302 | speed = ide_rate_filter(drive, speed); |
1da177e4 | 303 | |
f92d50e6 | 304 | if (speed >= XFER_SW_DMA_0) { |
1da177e4 | 305 | (void) pci_read_config_byte(dev, pciU, ®U); |
1da177e4 | 306 | regU &= ~(unit ? 0xCA : 0x35); |
1da177e4 LT |
307 | } |
308 | ||
309 | switch(speed) { | |
60e7a82f SS |
310 | case XFER_UDMA_5: |
311 | regU |= unit ? 0x0A : 0x05; | |
312 | break; | |
313 | case XFER_UDMA_4: | |
314 | regU |= unit ? 0x4A : 0x15; | |
315 | break; | |
316 | case XFER_UDMA_3: | |
317 | regU |= unit ? 0x8A : 0x25; | |
318 | break; | |
319 | case XFER_UDMA_2: | |
320 | regU |= unit ? 0x42 : 0x11; | |
321 | break; | |
322 | case XFER_UDMA_1: | |
323 | regU |= unit ? 0x82 : 0x21; | |
324 | break; | |
325 | case XFER_UDMA_0: | |
326 | regU |= unit ? 0xC2 : 0x31; | |
327 | break; | |
328 | case XFER_MW_DMA_2: | |
329 | program_cycle_times(drive, 120, 70); | |
330 | break; | |
331 | case XFER_MW_DMA_1: | |
332 | program_cycle_times(drive, 150, 80); | |
333 | break; | |
334 | case XFER_MW_DMA_0: | |
335 | program_cycle_times(drive, 480, 215); | |
336 | break; | |
337 | case XFER_PIO_5: | |
338 | case XFER_PIO_4: | |
339 | case XFER_PIO_3: | |
340 | case XFER_PIO_2: | |
341 | case XFER_PIO_1: | |
342 | case XFER_PIO_0: | |
343 | (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0); | |
344 | break; | |
345 | default: | |
346 | return 1; | |
1da177e4 LT |
347 | } |
348 | ||
60e7a82f | 349 | if (speed >= XFER_SW_DMA_0) |
1da177e4 | 350 | (void) pci_write_config_byte(dev, pciU, regU); |
1da177e4 | 351 | |
60e7a82f | 352 | return ide_config_drive_speed(drive, speed); |
1da177e4 LT |
353 | } |
354 | ||
1da177e4 LT |
355 | static int cmd64x_config_drive_for_dma (ide_drive_t *drive) |
356 | { | |
4728d546 | 357 | if (ide_tune_dma(drive)) |
3608b5d7 | 358 | return 0; |
1da177e4 | 359 | |
d8f4469d | 360 | if (ide_use_fast_pio(drive)) |
f92d50e6 | 361 | cmd64x_tune_drive(drive, 255); |
d8f4469d | 362 | |
3608b5d7 | 363 | return -1; |
1da177e4 LT |
364 | } |
365 | ||
66602c83 | 366 | static int cmd648_ide_dma_end (ide_drive_t *drive) |
1da177e4 | 367 | { |
66602c83 SS |
368 | ide_hwif_t *hwif = HWIF(drive); |
369 | int err = __ide_dma_end(drive); | |
370 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : | |
371 | MRDMODE_INTR_CH0; | |
372 | u8 mrdmode = inb(hwif->dma_master + 0x01); | |
373 | ||
374 | /* clear the interrupt bit */ | |
375 | outb(mrdmode | irq_mask, hwif->dma_master + 0x01); | |
376 | ||
377 | return err; | |
1da177e4 LT |
378 | } |
379 | ||
380 | static int cmd64x_ide_dma_end (ide_drive_t *drive) | |
381 | { | |
1da177e4 LT |
382 | ide_hwif_t *hwif = HWIF(drive); |
383 | struct pci_dev *dev = hwif->pci_dev; | |
66602c83 SS |
384 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
385 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : | |
386 | CFR_INTR_CH0; | |
387 | u8 irq_stat = 0; | |
388 | int err = __ide_dma_end(drive); | |
1da177e4 | 389 | |
66602c83 SS |
390 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); |
391 | /* clear the interrupt bit */ | |
392 | (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask); | |
393 | ||
394 | return err; | |
395 | } | |
396 | ||
397 | static int cmd648_ide_dma_test_irq (ide_drive_t *drive) | |
398 | { | |
399 | ide_hwif_t *hwif = HWIF(drive); | |
400 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : | |
401 | MRDMODE_INTR_CH0; | |
402 | u8 dma_stat = inb(hwif->dma_status); | |
403 | u8 mrdmode = inb(hwif->dma_master + 0x01); | |
404 | ||
405 | #ifdef DEBUG | |
406 | printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n", | |
407 | drive->name, dma_stat, mrdmode, irq_mask); | |
408 | #endif | |
409 | if (!(mrdmode & irq_mask)) | |
410 | return 0; | |
411 | ||
412 | /* return 1 if INTR asserted */ | |
413 | if (dma_stat & 4) | |
414 | return 1; | |
415 | ||
416 | return 0; | |
1da177e4 LT |
417 | } |
418 | ||
419 | static int cmd64x_ide_dma_test_irq (ide_drive_t *drive) | |
420 | { | |
e51e2528 SS |
421 | ide_hwif_t *hwif = HWIF(drive); |
422 | struct pci_dev *dev = hwif->pci_dev; | |
66602c83 SS |
423 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
424 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : | |
425 | CFR_INTR_CH0; | |
426 | u8 dma_stat = inb(hwif->dma_status); | |
427 | u8 irq_stat = 0; | |
e51e2528 SS |
428 | |
429 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); | |
1da177e4 | 430 | |
1da177e4 | 431 | #ifdef DEBUG |
66602c83 SS |
432 | printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n", |
433 | drive->name, dma_stat, irq_stat, irq_mask); | |
1da177e4 | 434 | #endif |
66602c83 | 435 | if (!(irq_stat & irq_mask)) |
1da177e4 LT |
436 | return 0; |
437 | ||
438 | /* return 1 if INTR asserted */ | |
66602c83 | 439 | if (dma_stat & 4) |
1da177e4 LT |
440 | return 1; |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | /* | |
446 | * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old | |
447 | * event order for DMA transfers. | |
448 | */ | |
449 | ||
450 | static int cmd646_1_ide_dma_end (ide_drive_t *drive) | |
451 | { | |
452 | ide_hwif_t *hwif = HWIF(drive); | |
453 | u8 dma_stat = 0, dma_cmd = 0; | |
454 | ||
455 | drive->waiting_for_dma = 0; | |
456 | /* get DMA status */ | |
0ecdca26 | 457 | dma_stat = inb(hwif->dma_status); |
1da177e4 | 458 | /* read DMA command state */ |
0ecdca26 | 459 | dma_cmd = inb(hwif->dma_command); |
1da177e4 | 460 | /* stop DMA */ |
0ecdca26 | 461 | outb(dma_cmd & ~1, hwif->dma_command); |
1da177e4 | 462 | /* clear the INTR & ERROR bits */ |
0ecdca26 | 463 | outb(dma_stat | 6, hwif->dma_status); |
1da177e4 LT |
464 | /* and free any DMA resources */ |
465 | ide_destroy_dmatable(drive); | |
466 | /* verify good DMA status */ | |
467 | return (dma_stat & 7) != 4; | |
468 | } | |
469 | ||
470 | static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name) | |
471 | { | |
472 | u32 class_rev = 0; | |
473 | u8 mrdmode = 0; | |
474 | ||
475 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
476 | class_rev &= 0xff; | |
477 | ||
1da177e4 LT |
478 | switch(dev->device) { |
479 | case PCI_DEVICE_ID_CMD_643: | |
480 | break; | |
481 | case PCI_DEVICE_ID_CMD_646: | |
482 | printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev); | |
483 | switch(class_rev) { | |
484 | case 0x07: | |
485 | case 0x05: | |
486 | printk("UltraDMA Capable"); | |
487 | break; | |
488 | case 0x03: | |
489 | printk("MultiWord DMA Force Limited"); | |
490 | break; | |
491 | case 0x01: | |
492 | default: | |
493 | printk("MultiWord DMA Limited, IRQ workaround enabled"); | |
494 | break; | |
495 | } | |
496 | printk("\n"); | |
497 | break; | |
498 | case PCI_DEVICE_ID_CMD_648: | |
499 | case PCI_DEVICE_ID_CMD_649: | |
500 | break; | |
501 | default: | |
502 | break; | |
503 | } | |
504 | ||
505 | /* Set a good latency timer and cache line size value. */ | |
506 | (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); | |
507 | /* FIXME: pci_set_master() to ensure a good latency timer value */ | |
508 | ||
509 | /* Setup interrupts. */ | |
510 | (void) pci_read_config_byte(dev, MRDMODE, &mrdmode); | |
511 | mrdmode &= ~(0x30); | |
512 | (void) pci_write_config_byte(dev, MRDMODE, mrdmode); | |
513 | ||
514 | /* Use MEMORY READ LINE for reads. | |
515 | * NOTE: Although not mentioned in the PCI0646U specs, | |
516 | * these bits are write only and won't be read | |
517 | * back as set or not. The PCI0646U2 specs clarify | |
518 | * this point. | |
519 | */ | |
520 | (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02); | |
521 | ||
522 | /* Set reasonable active/recovery/address-setup values. */ | |
523 | (void) pci_write_config_byte(dev, ARTTIM0, 0x40); | |
524 | (void) pci_write_config_byte(dev, DRWTIM0, 0x3f); | |
525 | (void) pci_write_config_byte(dev, ARTTIM1, 0x40); | |
526 | (void) pci_write_config_byte(dev, DRWTIM1, 0x3f); | |
527 | #ifdef __i386__ | |
528 | (void) pci_write_config_byte(dev, ARTTIM23, 0x1c); | |
529 | #else | |
530 | (void) pci_write_config_byte(dev, ARTTIM23, 0x5c); | |
531 | #endif | |
532 | (void) pci_write_config_byte(dev, DRWTIM23, 0x3f); | |
533 | (void) pci_write_config_byte(dev, DRWTIM3, 0x3f); | |
534 | #ifdef CONFIG_PPC | |
535 | (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0); | |
536 | #endif /* CONFIG_PPC */ | |
537 | ||
ecfd80e4 | 538 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) |
1da177e4 LT |
539 | |
540 | cmd_devs[n_cmd_devs++] = dev; | |
541 | ||
542 | if (!cmd64x_proc) { | |
543 | cmd64x_proc = 1; | |
544 | ide_pci_create_host_proc("cmd64x", cmd64x_get_info); | |
545 | } | |
ecfd80e4 | 546 | #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_IDE_PROC_FS */ |
1da177e4 LT |
547 | |
548 | return 0; | |
549 | } | |
550 | ||
551 | static unsigned int __devinit ata66_cmd64x(ide_hwif_t *hwif) | |
552 | { | |
553 | u8 ata66 = 0, mask = (hwif->channel) ? 0x02 : 0x01; | |
554 | ||
555 | switch(hwif->pci_dev->device) { | |
556 | case PCI_DEVICE_ID_CMD_643: | |
557 | case PCI_DEVICE_ID_CMD_646: | |
558 | return ata66; | |
559 | default: | |
560 | break; | |
561 | } | |
562 | pci_read_config_byte(hwif->pci_dev, BMIDECSR, &ata66); | |
563 | return (ata66 & mask) ? 1 : 0; | |
564 | } | |
565 | ||
566 | static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif) | |
567 | { | |
568 | struct pci_dev *dev = hwif->pci_dev; | |
569 | unsigned int class_rev; | |
570 | ||
571 | hwif->autodma = 0; | |
572 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
573 | class_rev &= 0xff; | |
574 | ||
f92d50e6 | 575 | hwif->tuneproc = &cmd64x_tune_drive; |
1da177e4 LT |
576 | hwif->speedproc = &cmd64x_tune_chipset; |
577 | ||
f92d50e6 SS |
578 | hwif->drives[0].autotune = hwif->drives[1].autotune = 1; |
579 | ||
580 | if (!hwif->dma_base) | |
1da177e4 | 581 | return; |
1da177e4 LT |
582 | |
583 | hwif->atapi_dma = 1; | |
584 | ||
18137207 BZ |
585 | hwif->ultra_mask = hwif->cds->udma_mask; |
586 | ||
2d5eaa6d BZ |
587 | /* |
588 | * UltraDMA only supported on PCI646U and PCI646U2, which | |
589 | * correspond to revisions 0x03, 0x05 and 0x07 respectively. | |
590 | * Actually, although the CMD tech support people won't | |
591 | * tell me the details, the 0x03 revision cannot support | |
592 | * UDMA correctly without hardware modifications, and even | |
593 | * then it only works with Quantum disks due to some | |
594 | * hold time assumptions in the 646U part which are fixed | |
595 | * in the 646U2. | |
596 | * | |
597 | * So we only do UltraDMA on revision 0x05 and 0x07 chipsets. | |
598 | */ | |
18137207 BZ |
599 | if (dev->device == PCI_DEVICE_ID_CMD_646 && class_rev < 5) |
600 | hwif->ultra_mask = 0x00; | |
1da177e4 | 601 | |
18137207 | 602 | hwif->mwdma_mask = 0x07; |
1da177e4 LT |
603 | |
604 | hwif->ide_dma_check = &cmd64x_config_drive_for_dma; | |
605 | if (!(hwif->udma_four)) | |
606 | hwif->udma_four = ata66_cmd64x(hwif); | |
607 | ||
66602c83 SS |
608 | switch(dev->device) { |
609 | case PCI_DEVICE_ID_CMD_648: | |
610 | case PCI_DEVICE_ID_CMD_649: | |
611 | alt_irq_bits: | |
612 | hwif->ide_dma_end = &cmd648_ide_dma_end; | |
613 | hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq; | |
614 | break; | |
615 | case PCI_DEVICE_ID_CMD_646: | |
1da177e4 LT |
616 | hwif->chipset = ide_cmd646; |
617 | if (class_rev == 0x01) { | |
618 | hwif->ide_dma_end = &cmd646_1_ide_dma_end; | |
66602c83 SS |
619 | break; |
620 | } else if (class_rev >= 0x03) | |
621 | goto alt_irq_bits; | |
622 | /* fall thru */ | |
623 | default: | |
624 | hwif->ide_dma_end = &cmd64x_ide_dma_end; | |
625 | hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq; | |
626 | break; | |
1da177e4 LT |
627 | } |
628 | ||
629 | ||
630 | if (!noautodma) | |
631 | hwif->autodma = 1; | |
632 | hwif->drives[0].autodma = hwif->autodma; | |
633 | hwif->drives[1].autodma = hwif->autodma; | |
634 | } | |
635 | ||
7accbffd SS |
636 | static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d) |
637 | { | |
638 | return ide_setup_pci_device(dev, d); | |
639 | } | |
640 | ||
641 | static int __devinit init_setup_cmd646(struct pci_dev *dev, ide_pci_device_t *d) | |
642 | { | |
643 | u8 rev = 0; | |
644 | ||
645 | /* | |
646 | * The original PCI0646 didn't have the primary channel enable bit, | |
647 | * it appeared starting with PCI0646U (i.e. revision ID 3). | |
648 | */ | |
649 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); | |
650 | if (rev < 3) | |
651 | d->enablebits[0].reg = 0; | |
652 | ||
653 | return ide_setup_pci_device(dev, d); | |
654 | } | |
655 | ||
1da177e4 LT |
656 | static ide_pci_device_t cmd64x_chipsets[] __devinitdata = { |
657 | { /* 0 */ | |
658 | .name = "CMD643", | |
7accbffd | 659 | .init_setup = init_setup_cmd64x, |
1da177e4 LT |
660 | .init_chipset = init_chipset_cmd64x, |
661 | .init_hwif = init_hwif_cmd64x, | |
662 | .channels = 2, | |
663 | .autodma = AUTODMA, | |
7accbffd | 664 | .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}}, |
1da177e4 | 665 | .bootable = ON_BOARD, |
18137207 | 666 | .udma_mask = 0x00, /* no udma */ |
1da177e4 LT |
667 | },{ /* 1 */ |
668 | .name = "CMD646", | |
7accbffd | 669 | .init_setup = init_setup_cmd646, |
1da177e4 LT |
670 | .init_chipset = init_chipset_cmd64x, |
671 | .init_hwif = init_hwif_cmd64x, | |
672 | .channels = 2, | |
673 | .autodma = AUTODMA, | |
7accbffd | 674 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
1da177e4 | 675 | .bootable = ON_BOARD, |
18137207 | 676 | .udma_mask = 0x07, /* udma0-2 */ |
1da177e4 LT |
677 | },{ /* 2 */ |
678 | .name = "CMD648", | |
7accbffd | 679 | .init_setup = init_setup_cmd64x, |
1da177e4 LT |
680 | .init_chipset = init_chipset_cmd64x, |
681 | .init_hwif = init_hwif_cmd64x, | |
682 | .channels = 2, | |
683 | .autodma = AUTODMA, | |
7accbffd | 684 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
1da177e4 | 685 | .bootable = ON_BOARD, |
18137207 | 686 | .udma_mask = 0x1f, /* udma0-4 */ |
1da177e4 LT |
687 | },{ /* 3 */ |
688 | .name = "CMD649", | |
7accbffd | 689 | .init_setup = init_setup_cmd64x, |
1da177e4 LT |
690 | .init_chipset = init_chipset_cmd64x, |
691 | .init_hwif = init_hwif_cmd64x, | |
692 | .channels = 2, | |
693 | .autodma = AUTODMA, | |
7accbffd | 694 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
1da177e4 | 695 | .bootable = ON_BOARD, |
18137207 | 696 | .udma_mask = 0x3f, /* udma0-5 */ |
1da177e4 LT |
697 | } |
698 | }; | |
699 | ||
7accbffd SS |
700 | /* |
701 | * We may have to modify enablebits for PCI0646, so we'd better pass | |
702 | * a local copy of the ide_pci_device_t structure down the call chain... | |
703 | */ | |
1da177e4 LT |
704 | static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
705 | { | |
7accbffd SS |
706 | ide_pci_device_t d = cmd64x_chipsets[id->driver_data]; |
707 | ||
708 | return d.init_setup(dev, &d); | |
1da177e4 LT |
709 | } |
710 | ||
711 | static struct pci_device_id cmd64x_pci_tbl[] = { | |
712 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
713 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, | |
714 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
715 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, | |
716 | { 0, }, | |
717 | }; | |
718 | MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl); | |
719 | ||
720 | static struct pci_driver driver = { | |
721 | .name = "CMD64x_IDE", | |
722 | .id_table = cmd64x_pci_tbl, | |
723 | .probe = cmd64x_init_one, | |
724 | }; | |
725 | ||
82ab1eec | 726 | static int __init cmd64x_ide_init(void) |
1da177e4 LT |
727 | { |
728 | return ide_pci_register_driver(&driver); | |
729 | } | |
730 | ||
731 | module_init(cmd64x_ide_init); | |
732 | ||
733 | MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick"); | |
734 | MODULE_DESCRIPTION("PCI driver module for CMD64x IDE"); | |
735 | MODULE_LICENSE("GPL"); |