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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org> |
1da177e4 | 3 | * Copyright (C) 2000 Mark Lord <mlord@pobox.com> |
5fd216bb BZ |
4 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
5 | * | |
1da177e4 LT |
6 | * May be copied or modified under the terms of the GNU General Public License |
7 | * | |
8 | * Development of this chipset driver was funded | |
9 | * by the nice folks at National Semiconductor. | |
10 | * | |
11 | * Documentation: | |
12 | * CS5530 documentation available from National Semiconductor. | |
13 | */ | |
14 | ||
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/types.h> | |
17 | #include <linux/kernel.h> | |
1da177e4 | 18 | #include <linux/hdreg.h> |
1da177e4 LT |
19 | #include <linux/pci.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/ide.h> | |
78829dd9 | 22 | |
1da177e4 | 23 | #include <asm/io.h> |
1da177e4 | 24 | |
1da177e4 LT |
25 | /* |
26 | * Here are the standard PIO mode 0-4 timings for each "format". | |
27 | * Format-0 uses fast data reg timings, with slower command reg timings. | |
28 | * Format-1 uses fast timings for all registers, but won't work with all drives. | |
29 | */ | |
30 | static unsigned int cs5530_pio_timings[2][5] = { | |
31 | {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, | |
32 | {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010} | |
33 | }; | |
34 | ||
35 | /* | |
36 | * After chip reset, the PIO timings are set to 0x0000e132, which is not valid. | |
37 | */ | |
38 | #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132) | |
39 | #define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20)) | |
40 | ||
41 | /** | |
88b2b32b | 42 | * cs5530_set_pio_mode - set host controller for PIO mode |
26bcb879 BZ |
43 | * @drive: drive |
44 | * @pio: PIO mode number | |
1da177e4 | 45 | * |
88b2b32b | 46 | * Handles setting of PIO mode for the chipset. |
1da177e4 | 47 | * |
26bcb879 | 48 | * The init_hwif_cs5530() routine guarantees that all drives |
1da177e4 LT |
49 | * will have valid default PIO timings set up before we get here. |
50 | */ | |
51 | ||
26bcb879 | 52 | static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 53 | { |
88b2b32b BZ |
54 | unsigned long basereg = CS5530_BASEREG(drive->hwif); |
55 | unsigned int format = (inl(basereg + 4) >> 31) & 1; | |
56 | ||
57 | outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3)); | |
1da177e4 LT |
58 | } |
59 | ||
60 | /** | |
5fd216bb BZ |
61 | * cs5530_udma_filter - UDMA filter |
62 | * @drive: drive | |
63 | * | |
64 | * cs5530_udma_filter() does UDMA mask filtering for the given drive | |
65 | * taking into the consideration capabilities of the mate device. | |
66 | * | |
67 | * The CS5530 specifies that two drives sharing a cable cannot mix | |
68 | * UDMA/MDMA. It has to be one or the other, for the pair, though | |
69 | * different timings can still be chosen for each drive. We could | |
70 | * set the appropriate timing bits on the fly, but that might be | |
71 | * a bit confusing. So, for now we statically handle this requirement | |
72 | * by looking at our mate drive to see what it is capable of, before | |
73 | * choosing a mode for our own drive. | |
74 | * | |
75 | * Note: This relies on the fact we never fail from UDMA to MWDMA2 | |
76 | * but instead drop to PIO. | |
77 | */ | |
78 | ||
79 | static u8 cs5530_udma_filter(ide_drive_t *drive) | |
80 | { | |
81 | ide_hwif_t *hwif = drive->hwif; | |
82 | ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1]; | |
83 | struct hd_driveid *mateid = mate->id; | |
84 | u8 mask = hwif->ultra_mask; | |
85 | ||
86 | if (mate->present == 0) | |
87 | goto out; | |
88 | ||
89 | if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) { | |
90 | if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7)) | |
91 | goto out; | |
92 | if ((mateid->field_valid & 2) && (mateid->dma_mword & 7)) | |
93 | mask = 0; | |
94 | } | |
95 | out: | |
96 | return mask; | |
97 | } | |
98 | ||
88b2b32b | 99 | static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode) |
3c3f5d2c | 100 | { |
5fd216bb | 101 | unsigned long basereg; |
3c3f5d2c | 102 | unsigned int reg, timings = 0; |
1da177e4 | 103 | |
1da177e4 LT |
104 | switch (mode) { |
105 | case XFER_UDMA_0: timings = 0x00921250; break; | |
106 | case XFER_UDMA_1: timings = 0x00911140; break; | |
107 | case XFER_UDMA_2: timings = 0x00911030; break; | |
108 | case XFER_MW_DMA_0: timings = 0x00077771; break; | |
109 | case XFER_MW_DMA_1: timings = 0x00012121; break; | |
110 | case XFER_MW_DMA_2: timings = 0x00002020; break; | |
1da177e4 | 111 | } |
3c3f5d2c | 112 | basereg = CS5530_BASEREG(drive->hwif); |
0ecdca26 | 113 | reg = inl(basereg + 4); /* get drive0 config register */ |
1da177e4 | 114 | timings |= reg & 0x80000000; /* preserve PIO format bit */ |
3c3f5d2c | 115 | if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */ |
0ecdca26 | 116 | outl(timings, basereg + 4); /* write drive0 config register */ |
1da177e4 LT |
117 | } else { |
118 | if (timings & 0x00100000) | |
119 | reg |= 0x00100000; /* enable UDMA timings for both drives */ | |
120 | else | |
121 | reg &= ~0x00100000; /* disable UDMA timings for both drives */ | |
0ecdca26 BZ |
122 | outl(reg, basereg + 4); /* write drive0 config register */ |
123 | outl(timings, basereg + 12); /* write drive1 config register */ | |
1da177e4 | 124 | } |
1da177e4 LT |
125 | } |
126 | ||
127 | /** | |
128 | * init_chipset_5530 - set up 5530 bridge | |
129 | * @dev: PCI device | |
130 | * @name: device name | |
131 | * | |
132 | * Initialize the cs5530 bridge for reliable IDE DMA operation. | |
133 | */ | |
134 | ||
88de8e99 | 135 | static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const char *name) |
1da177e4 LT |
136 | { |
137 | struct pci_dev *master_0 = NULL, *cs5530_0 = NULL; | |
1da177e4 | 138 | |
f7b0d2df BZ |
139 | if (pci_resource_start(dev, 4) == 0) |
140 | return -EFAULT; | |
141 | ||
1da177e4 | 142 | dev = NULL; |
652aa162 | 143 | while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) { |
1da177e4 LT |
144 | switch (dev->device) { |
145 | case PCI_DEVICE_ID_CYRIX_PCI_MASTER: | |
652aa162 | 146 | master_0 = pci_dev_get(dev); |
1da177e4 LT |
147 | break; |
148 | case PCI_DEVICE_ID_CYRIX_5530_LEGACY: | |
652aa162 | 149 | cs5530_0 = pci_dev_get(dev); |
1da177e4 LT |
150 | break; |
151 | } | |
152 | } | |
153 | if (!master_0) { | |
154 | printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name); | |
652aa162 | 155 | goto out; |
1da177e4 LT |
156 | } |
157 | if (!cs5530_0) { | |
158 | printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name); | |
652aa162 | 159 | goto out; |
1da177e4 LT |
160 | } |
161 | ||
1da177e4 LT |
162 | /* |
163 | * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530: | |
164 | * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530 | |
165 | */ | |
166 | ||
167 | pci_set_master(cs5530_0); | |
694625c0 | 168 | pci_try_set_mwi(cs5530_0); |
1da177e4 LT |
169 | |
170 | /* | |
171 | * Set PCI CacheLineSize to 16-bytes: | |
172 | * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530 | |
173 | */ | |
174 | ||
175 | pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04); | |
176 | ||
177 | /* | |
178 | * Disable trapping of UDMA register accesses (Win98 hack): | |
179 | * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530 | |
180 | */ | |
181 | ||
182 | pci_write_config_word(cs5530_0, 0xd0, 0x5006); | |
183 | ||
184 | /* | |
185 | * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus: | |
186 | * The other settings are what is necessary to get the register | |
187 | * into a sane state for IDE DMA operation. | |
188 | */ | |
189 | ||
190 | pci_write_config_byte(master_0, 0x40, 0x1e); | |
191 | ||
192 | /* | |
193 | * Set max PCI burst size (16-bytes seems to work best): | |
194 | * 16bytes: set bit-1 at 0x41 (reg value of 0x16) | |
195 | * all others: clear bit-1 at 0x41, and do: | |
196 | * 128bytes: OR 0x00 at 0x41 | |
197 | * 256bytes: OR 0x04 at 0x41 | |
198 | * 512bytes: OR 0x08 at 0x41 | |
199 | * 1024bytes: OR 0x0c at 0x41 | |
200 | */ | |
201 | ||
202 | pci_write_config_byte(master_0, 0x41, 0x14); | |
203 | ||
204 | /* | |
205 | * These settings are necessary to get the chip | |
206 | * into a sane state for IDE DMA operation. | |
207 | */ | |
208 | ||
209 | pci_write_config_byte(master_0, 0x42, 0x00); | |
210 | pci_write_config_byte(master_0, 0x43, 0xc1); | |
211 | ||
652aa162 AC |
212 | out: |
213 | pci_dev_put(master_0); | |
214 | pci_dev_put(cs5530_0); | |
1da177e4 LT |
215 | return 0; |
216 | } | |
217 | ||
218 | /** | |
219 | * init_hwif_cs5530 - initialise an IDE channel | |
220 | * @hwif: IDE to initialize | |
221 | * | |
222 | * This gets invoked by the IDE driver once for each channel. It | |
223 | * performs channel-specific pre-initialization before drive probing. | |
224 | */ | |
225 | ||
88de8e99 | 226 | static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif) |
1da177e4 LT |
227 | { |
228 | unsigned long basereg; | |
229 | u32 d0_timings; | |
1da177e4 | 230 | |
1da177e4 | 231 | basereg = CS5530_BASEREG(hwif); |
0ecdca26 | 232 | d0_timings = inl(basereg + 0); |
93104654 | 233 | if (CS5530_BAD_PIO(d0_timings)) |
0ecdca26 | 234 | outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0); |
93104654 | 235 | if (CS5530_BAD_PIO(inl(basereg + 8))) |
0ecdca26 | 236 | outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8); |
1da177e4 LT |
237 | } |
238 | ||
ac95beed BZ |
239 | static const struct ide_port_ops cs5530_port_ops = { |
240 | .set_pio_mode = cs5530_set_pio_mode, | |
241 | .set_dma_mode = cs5530_set_dma_mode, | |
242 | .udma_filter = cs5530_udma_filter, | |
243 | }; | |
244 | ||
85620436 | 245 | static const struct ide_port_info cs5530_chipset __devinitdata = { |
1da177e4 LT |
246 | .name = "CS5530", |
247 | .init_chipset = init_chipset_cs5530, | |
248 | .init_hwif = init_hwif_cs5530, | |
ac95beed | 249 | .port_ops = &cs5530_port_ops, |
1c51361a | 250 | .host_flags = IDE_HFLAG_SERIALIZE | |
5e71d9c5 | 251 | IDE_HFLAG_POST_SET_MODE, |
4099d143 | 252 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
253 | .mwdma_mask = ATA_MWDMA2, |
254 | .udma_mask = ATA_UDMA2, | |
1da177e4 LT |
255 | }; |
256 | ||
257 | static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
258 | { | |
259 | return ide_setup_pci_device(dev, &cs5530_chipset); | |
260 | } | |
261 | ||
9cbcc5e3 BZ |
262 | static const struct pci_device_id cs5530_pci_tbl[] = { |
263 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), 0 }, | |
1da177e4 LT |
264 | { 0, }, |
265 | }; | |
266 | MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl); | |
267 | ||
268 | static struct pci_driver driver = { | |
269 | .name = "CS5530 IDE", | |
270 | .id_table = cs5530_pci_tbl, | |
271 | .probe = cs5530_init_one, | |
272 | }; | |
273 | ||
82ab1eec | 274 | static int __init cs5530_ide_init(void) |
1da177e4 LT |
275 | { |
276 | return ide_pci_register_driver(&driver); | |
277 | } | |
278 | ||
279 | module_init(cs5530_ide_init); | |
280 | ||
281 | MODULE_AUTHOR("Mark Lord"); | |
282 | MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE"); | |
283 | MODULE_LICENSE("GPL"); |