[mirror_ubuntu-artful-kernel.git] / drivers / ide / pci / cs5535.c

/*
 * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
 * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
 *
 * History:
 * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
 * - Reworked tuneproc, set_drive, misc mods to prep for mainline
 * - Work was sponsored by CIS (M) Sdn Bhd.
 * Ported to Kernel 2.6.11 on June 26, 2005 by
 *   Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
 *   Alexander Kiausch <alex.kiausch@t-online.de>
 * Originally developed by AMD for 2.4/2.6
 *
 * Development of this chipset driver was funded
 * by the nice folks at National Semiconductor/AMD.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * Documentation:
 *  CS5535 documentation available from AMD
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/ide.h>

#include "ide-timing.h"

#define MSR_ATAC_BASE		0x51300000
#define ATAC_GLD_MSR_CAP	(MSR_ATAC_BASE+0)
#define ATAC_GLD_MSR_CONFIG	(MSR_ATAC_BASE+0x01)
#define ATAC_GLD_MSR_SMI	(MSR_ATAC_BASE+0x02)
#define ATAC_GLD_MSR_ERROR	(MSR_ATAC_BASE+0x03)
#define ATAC_GLD_MSR_PM		(MSR_ATAC_BASE+0x04)
#define ATAC_GLD_MSR_DIAG	(MSR_ATAC_BASE+0x05)
#define ATAC_IO_BAR		(MSR_ATAC_BASE+0x08)
#define ATAC_RESET		(MSR_ATAC_BASE+0x10)
#define ATAC_CH0D0_PIO		(MSR_ATAC_BASE+0x20)
#define ATAC_CH0D0_DMA		(MSR_ATAC_BASE+0x21)
#define ATAC_CH0D1_PIO		(MSR_ATAC_BASE+0x22)
#define ATAC_CH0D1_DMA		(MSR_ATAC_BASE+0x23)
#define ATAC_PCI_ABRTERR	(MSR_ATAC_BASE+0x24)
#define ATAC_BM0_CMD_PRIM	0x00
#define ATAC_BM0_STS_PRIM	0x02
#define ATAC_BM0_PRD		0x04
#define CS5535_CABLE_DETECT	0x48

/* Format I PIO settings. We separate out cmd and data for safer timings */

static unsigned int cs5535_pio_cmd_timings[5] =
{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
static unsigned int cs5535_pio_dta_timings[5] =
{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };

static unsigned int cs5535_mwdma_timings[3] =
{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };

static unsigned int cs5535_udma_timings[5] =
{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };

/* Macros to check if the register is the reset value -  reset value is an
   invalid timing and indicates the register has not been set previously */

#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )

/****
 *	cs5535_set_speed         -     Configure the chipset to the new speed
 *	@drive: Drive to set up
 *	@speed: desired speed
 *
 *	cs5535_set_speed() configures the chipset to a new speed.
 */
static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
{

	u32 reg = 0, dummy;
	int unit = drive->select.b.unit;


	/* Set the PIO timings */
	if ((speed & XFER_MODE) == XFER_PIO) {
		ide_drive_t *pair = ide_get_paired_drive(drive);
		u8 cmd, pioa;

		cmd = pioa = speed - XFER_PIO_0;

		if (pair->present) {
			u8 piob = ide_get_best_pio_mode(pair, 255, 4);

			if (piob < cmd)
				cmd = piob;
		}

		/* Write the speed of the current drive */
		reg = (cs5535_pio_cmd_timings[cmd] << 16) |
			cs5535_pio_dta_timings[pioa];
		wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);

		/* And if nessesary - change the speed of the other drive */
		rdmsr(unit ?  ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);

		if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
			cs5535_pio_cmd_timings[cmd]) {
			reg &= 0x0000FFFF;
			reg |= cs5535_pio_cmd_timings[cmd] << 16;
			wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
		}

		/* Set bit 31 of the DMA register for PIO format 1 timings */
		rdmsr(unit ?  ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
		wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
					reg | 0x80000000UL, 0);
	} else {
		rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);

		reg &= 0x80000000UL;  /* Preserve the PIO format bit */

		if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
			reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
		else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
			reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
		else
			return;

		wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
	}
}

/**
 *	cs5535_set_dma_mode	-	set host controller for DMA mode
 *	@drive: drive
 *	@speed: DMA mode
 *
 *	Programs the chipset for DMA mode.
 */

static void cs5535_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	cs5535_set_speed(drive, speed);
}

/**
 *	cs5535_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void cs5535_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	cs5535_set_speed(drive, XFER_PIO_0 + pio);
}

static u8 __devinit cs5535_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u8 bit;

	/* if a 80 wire cable was detected */
	pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);

	return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
}

/****
 *	init_hwif_cs5535        -       Initialize one ide cannel
 *	@hwif: Channel descriptor
 *
 *	This gets invoked by the IDE driver once for each channel. It
 *	performs channel-specific pre-initialization before drive probing.
 *
 */
static void __devinit init_hwif_cs5535(ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &cs5535_set_pio_mode;
	hwif->set_dma_mode = &cs5535_set_dma_mode;

	hwif->cable_detect = cs5535_cable_detect;
}

static const struct ide_port_info cs5535_chipset __devinitdata = {
	.name		= "CS5535",
	.init_hwif	= init_hwif_cs5535,
	.host_flags	= IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE |
			  IDE_HFLAG_ABUSE_SET_DMA_MODE,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
	.udma_mask	= ATA_UDMA4,
};

static int __devinit cs5535_init_one(struct pci_dev *dev,
					const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &cs5535_chipset);
}

static const struct pci_device_id cs5535_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 },
	{ 0, },
};

MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);

static struct pci_driver driver = {
	.name       = "CS5535_IDE",
	.id_table   = cs5535_pci_tbl,
	.probe      = cs5535_init_one,
};

static int __init cs5535_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(cs5535_ide_init);

MODULE_AUTHOR("AMD");
MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
f5b2d8b4	1	/*
f5b2d8b4	2	* Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
bc0b0b5c	3	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
f5b2d8b4 JK	4	*
	5	* History:
	6	* 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
	7	* - Reworked tuneproc, set_drive, misc mods to prep for mainline
	8	* - Work was sponsored by CIS (M) Sdn Bhd.
	9	* Ported to Kernel 2.6.11 on June 26, 2005 by
	10	* Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
	11	* Alexander Kiausch <alex.kiausch@t-online.de>
	12	* Originally developed by AMD for 2.4/2.6
	13	*
	14	* Development of this chipset driver was funded
	15	* by the nice folks at National Semiconductor/AMD.
	16	*
	17	* This program is free software; you can redistribute it and/or modify it
	18	* under the terms of the GNU General Public License version 2 as published by
	19	* the Free Software Foundation.
	20	*
	21	* Documentation:
	22	* CS5535 documentation available from AMD
	23	*/
	24
f5b2d8b4 JK	25	#include <linux/module.h>
	26	#include <linux/pci.h>
	27	#include <linux/ide.h>
	28
	29	#include "ide-timing.h"
	30
	31	#define MSR_ATAC_BASE 0x51300000
	32	#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
	33	#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
	34	#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
	35	#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
	36	#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
	37	#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
	38	#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
	39	#define ATAC_RESET (MSR_ATAC_BASE+0x10)
	40	#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
	41	#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
	42	#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
	43	#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
	44	#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
	45	#define ATAC_BM0_CMD_PRIM 0x00
	46	#define ATAC_BM0_STS_PRIM 0x02
	47	#define ATAC_BM0_PRD 0x04
	48	#define CS5535_CABLE_DETECT 0x48
	49
a1c6d28c	50	/* Format I PIO settings. We separate out cmd and data for safer timings */
f5b2d8b4 JK	51
	52	static unsigned int cs5535_pio_cmd_timings[5] =
	53	{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
	54	static unsigned int cs5535_pio_dta_timings[5] =
	55	{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
	56
	57	static unsigned int cs5535_mwdma_timings[3] =
	58	{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
	59
	60	static unsigned int cs5535_udma_timings[5] =
	61	{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
	62
	63	/* Macros to check if the register is the reset value - reset value is an
	64	invalid timing and indicates the register has not been set previously */
	65
	66	#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
	67	#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
	68
	69	/****
	70	* cs5535_set_speed - Configure the chipset to the new speed
	71	* @drive: Drive to set up
	72	* @speed: desired speed
	73	*
	74	* cs5535_set_speed() configures the chipset to a new speed.
	75	*/
f212ff28	76	static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
f5b2d8b4 JK	77	{
	78
	79	u32 reg = 0, dummy;
	80	int unit = drive->select.b.unit;
	81
	82
	83	/* Set the PIO timings */
	84	if ((speed & XFER_MODE) == XFER_PIO) {
15d8061b	85	ide_drive_t *pair = ide_get_paired_drive(drive);
bc0b0b5c	86	u8 cmd, pioa;
f5b2d8b4	87
bc0b0b5c BZ	88	cmd = pioa = speed - XFER_PIO_0;
	89
	90	if (pair->present) {
	91	u8 piob = ide_get_best_pio_mode(pair, 255, 4);
	92
	93	if (piob < cmd)
	94	cmd = piob;
	95	}
f5b2d8b4 JK	96
	97	/* Write the speed of the current drive */
	98	reg = (cs5535_pio_cmd_timings[cmd] << 16) \|
	99	cs5535_pio_dta_timings[pioa];
	100	wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
	101
	102	/* And if nessesary - change the speed of the other drive */
	103	rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
	104
	105	if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
	106	cs5535_pio_cmd_timings[cmd]) {
	107	reg &= 0x0000FFFF;
	108	reg \|= cs5535_pio_cmd_timings[cmd] << 16;
	109	wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
	110	}
	111
	112	/* Set bit 31 of the DMA register for PIO format 1 timings */
	113	rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
	114	wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
	115	reg \| 0x80000000UL, 0);
	116	} else {
	117	rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
	118
	119	reg &= 0x80000000UL; /* Preserve the PIO format bit */
	120
32a70a81	121	if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
f5b2d8b4 JK	122	reg \|= cs5535_udma_timings[speed - XFER_UDMA_0];
	123	else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
	124	reg \|= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
	125	else
	126	return;
	127
	128	wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
	129	}
	130	}
	131
88b2b32b BZ	132	/**
	133	* cs5535_set_dma_mode - set host controller for DMA mode
	134	* @drive: drive
	135	* @speed: DMA mode
f5b2d8b4	136	*
88b2b32b	137	* Programs the chipset for DMA mode.
f5b2d8b4	138	*/
249aa4ff	139
88b2b32b BZ	140	static void cs5535_set_dma_mode(ide_drive_t *drive, const u8 speed)
88b2b32b BZ	141	{
f5b2d8b4	142	cs5535_set_speed(drive, speed);
f5b2d8b4 JK	143	}
f5b2d8b4 JK	144
26bcb879	145	/**
88b2b32b	146	* cs5535_set_pio_mode - set host controller for PIO mode
26bcb879 BZ	147	* @drive: drive
26bcb879 BZ	148	* @pio: PIO mode number
f5b2d8b4 JK	149	*
	150	* A callback from the upper layers for PIO-only tuning.
	151	*/
26bcb879 BZ	152
26bcb879 BZ	153	static void cs5535_set_pio_mode(ide_drive_t *drive, const u8 pio)
f5b2d8b4	154	{
bc0b0b5c	155	cs5535_set_speed(drive, XFER_PIO_0 + pio);
f5b2d8b4 JK	156	}
f5b2d8b4 JK	157
b4d1c73d	158	static u8 __devinit cs5535_cable_detect(ide_hwif_t *hwif)
f5b2d8b4	159	{
b4d1c73d	160	struct pci_dev *dev = to_pci_dev(hwif->dev);
f5b2d8b4 JK	161	u8 bit;
	162
	163	/* if a 80 wire cable was detected */
	164	pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
49521f97 BZ	165
49521f97 BZ	166	return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
f5b2d8b4 JK	167	}
	168
	169	/****
	170	* init_hwif_cs5535 - Initialize one ide cannel
	171	* @hwif: Channel descriptor
	172	*
	173	* This gets invoked by the IDE driver once for each channel. It
	174	* performs channel-specific pre-initialization before drive probing.
	175	*
	176	*/
	177	static void __devinit init_hwif_cs5535(ide_hwif_t *hwif)
	178	{
26bcb879	179	hwif->set_pio_mode = &cs5535_set_pio_mode;
88b2b32b	180	hwif->set_dma_mode = &cs5535_set_dma_mode;
7bda292d	181
bfa14b42	182	hwif->cable_detect = cs5535_cable_detect;
f5b2d8b4 JK	183	}
f5b2d8b4 JK	184
85620436	185	static const struct ide_port_info cs5535_chipset __devinitdata = {
f5b2d8b4 JK	186	.name = "CS5535",
f5b2d8b4 JK	187	.init_hwif = init_hwif_cs5535,
7cab14a7	188	.host_flags = IDE_HFLAG_SINGLE \| IDE_HFLAG_POST_SET_MODE \|
5e71d9c5	189	IDE_HFLAG_ABUSE_SET_DMA_MODE,
4099d143	190	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	191	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	192	.udma_mask = ATA_UDMA4,
f5b2d8b4 JK	193	};
	194
	195	static int __devinit cs5535_init_one(struct pci_dev *dev,
	196	const struct pci_device_id *id)
	197	{
	198	return ide_setup_pci_device(dev, &cs5535_chipset);
	199	}
	200
9cbcc5e3 BZ	201	static const struct pci_device_id cs5535_pci_tbl[] = {
9cbcc5e3 BZ	202	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 },
f5b2d8b4 JK	203	{ 0, },
	204	};
	205
	206	MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
	207
	208	static struct pci_driver driver = {
	209	.name = "CS5535_IDE",
	210	.id_table = cs5535_pci_tbl,
	211	.probe = cs5535_init_one,
	212	};
	213
	214	static int __init cs5535_ide_init(void)
	215	{
	216	return ide_pci_register_driver(&driver);
	217	}
	218
	219	module_init(cs5535_ide_init);
	220
	221	MODULE_AUTHOR("AMD");
	222	MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
	223	MODULE_LICENSE("GPL");