[mirror_ubuntu-artful-kernel.git] / drivers / ide / pci / cs5535.c

/*
 * linux/drivers/ide/pci/cs5535.c
 *
 * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
 * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
 *
 * History:
 * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
 * - Reworked tuneproc, set_drive, misc mods to prep for mainline
 * - Work was sponsored by CIS (M) Sdn Bhd.
 * Ported to Kernel 2.6.11 on June 26, 2005 by
 *   Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
 *   Alexander Kiausch <alex.kiausch@t-online.de>
 * Originally developed by AMD for 2.4/2.6
 *
 * Development of this chipset driver was funded
 * by the nice folks at National Semiconductor/AMD.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * Documentation:
 *  CS5535 documentation available from AMD
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/ide.h>

#include "ide-timing.h"

#define MSR_ATAC_BASE		0x51300000
#define ATAC_GLD_MSR_CAP	(MSR_ATAC_BASE+0)
#define ATAC_GLD_MSR_CONFIG	(MSR_ATAC_BASE+0x01)
#define ATAC_GLD_MSR_SMI	(MSR_ATAC_BASE+0x02)
#define ATAC_GLD_MSR_ERROR	(MSR_ATAC_BASE+0x03)
#define ATAC_GLD_MSR_PM		(MSR_ATAC_BASE+0x04)
#define ATAC_GLD_MSR_DIAG	(MSR_ATAC_BASE+0x05)
#define ATAC_IO_BAR		(MSR_ATAC_BASE+0x08)
#define ATAC_RESET		(MSR_ATAC_BASE+0x10)
#define ATAC_CH0D0_PIO		(MSR_ATAC_BASE+0x20)
#define ATAC_CH0D0_DMA		(MSR_ATAC_BASE+0x21)
#define ATAC_CH0D1_PIO		(MSR_ATAC_BASE+0x22)
#define ATAC_CH0D1_DMA		(MSR_ATAC_BASE+0x23)
#define ATAC_PCI_ABRTERR	(MSR_ATAC_BASE+0x24)
#define ATAC_BM0_CMD_PRIM	0x00
#define ATAC_BM0_STS_PRIM	0x02
#define ATAC_BM0_PRD		0x04
#define CS5535_CABLE_DETECT	0x48

/* Format I PIO settings. We seperate out cmd and data for safer timings */

static unsigned int cs5535_pio_cmd_timings[5] =
{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
static unsigned int cs5535_pio_dta_timings[5] =
{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };

static unsigned int cs5535_mwdma_timings[3] =
{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };

static unsigned int cs5535_udma_timings[5] =
{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };

/* Macros to check if the register is the reset value -  reset value is an
   invalid timing and indicates the register has not been set previously */

#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )

/****
 *	cs5535_set_speed         -     Configure the chipset to the new speed
 *	@drive: Drive to set up
 *	@speed: desired speed
 *
 *	cs5535_set_speed() configures the chipset to a new speed.
 */
static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
{

	u32 reg = 0, dummy;
	int unit = drive->select.b.unit;


	/* Set the PIO timings */
	if ((speed & XFER_MODE) == XFER_PIO) {
		ide_drive_t *pair = &drive->hwif->drives[drive->dn ^ 1];
		u8 cmd, pioa;

		cmd = pioa = speed - XFER_PIO_0;

		if (pair->present) {
			u8 piob = ide_get_best_pio_mode(pair, 255, 4);

			if (piob < cmd)
				cmd = piob;
		}

		/* Write the speed of the current drive */
		reg = (cs5535_pio_cmd_timings[cmd] << 16) |
			cs5535_pio_dta_timings[pioa];
		wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);

		/* And if nessesary - change the speed of the other drive */
		rdmsr(unit ?  ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);

		if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
			cs5535_pio_cmd_timings[cmd]) {
			reg &= 0x0000FFFF;
			reg |= cs5535_pio_cmd_timings[cmd] << 16;
			wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
		}

		/* Set bit 31 of the DMA register for PIO format 1 timings */
		rdmsr(unit ?  ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
		wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
					reg | 0x80000000UL, 0);
	} else {
		rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);

		reg &= 0x80000000UL;  /* Preserve the PIO format bit */

		if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
			reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
		else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
			reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
		else
			return;

		wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
	}
}

/**
 *	cs5535_set_dma_mode	-	set host controller for DMA mode
 *	@drive: drive
 *	@speed: DMA mode
 *
 *	Programs the chipset for DMA mode.
 */

static void cs5535_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	cs5535_set_speed(drive, speed);
}

/**
 *	cs5535_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void cs5535_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	cs5535_set_speed(drive, XFER_PIO_0 + pio);
}

static u8 __devinit cs5535_cable_detect(struct pci_dev *dev)
{
	u8 bit;

	/* if a 80 wire cable was detected */
	pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);

	return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
}

/****
 *	init_hwif_cs5535        -       Initialize one ide cannel
 *	@hwif: Channel descriptor
 *
 *	This gets invoked by the IDE driver once for each channel. It
 *	performs channel-specific pre-initialization before drive probing.
 *
 */
static void __devinit init_hwif_cs5535(ide_hwif_t *hwif)
{
	hwif->autodma = 0;

	hwif->set_pio_mode = &cs5535_set_pio_mode;
	hwif->set_dma_mode = &cs5535_set_dma_mode;

	hwif->drives[1].autotune = hwif->drives[0].autotune = 1;

	if (hwif->dma_base == 0)
		return;

	hwif->atapi_dma = 1;
	hwif->ultra_mask = 0x1F;
	hwif->mwdma_mask = 0x07;

	hwif->cbl = cs5535_cable_detect(hwif->pci_dev);

	if (!noautodma)
		hwif->autodma = 1;

	hwif->drives[1].autodma = hwif->drives[0].autodma = hwif->autodma;
}

static ide_pci_device_t cs5535_chipset __devinitdata = {
	.name		= "CS5535",
	.init_hwif	= init_hwif_cs5535,
	.autodma	= AUTODMA,
	.bootable	= ON_BOARD,
	.host_flags	= IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE,
	.pio_mask	= ATA_PIO4,
};

static int __devinit cs5535_init_one(struct pci_dev *dev,
					const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &cs5535_chipset);
}

static struct pci_device_id cs5535_pci_tbl[] =
{
	{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_IDE, PCI_ANY_ID,
		PCI_ANY_ID, 0, 0, 0},
	{ 0, },
};

MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);

static struct pci_driver driver = {
	.name       = "CS5535_IDE",
	.id_table   = cs5535_pci_tbl,
	.probe      = cs5535_init_one,
};

static int __init cs5535_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(cs5535_ide_init);

MODULE_AUTHOR("AMD");
MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
f5b2d8b4 JK	1	/*
	2	* linux/drivers/ide/pci/cs5535.c
	3	*
	4	* Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
bc0b0b5c	5	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
f5b2d8b4 JK	6	*
	7	* History:
	8	* 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
	9	* - Reworked tuneproc, set_drive, misc mods to prep for mainline
	10	* - Work was sponsored by CIS (M) Sdn Bhd.
	11	* Ported to Kernel 2.6.11 on June 26, 2005 by
	12	* Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
	13	* Alexander Kiausch <alex.kiausch@t-online.de>
	14	* Originally developed by AMD for 2.4/2.6
	15	*
	16	* Development of this chipset driver was funded
	17	* by the nice folks at National Semiconductor/AMD.
	18	*
	19	* This program is free software; you can redistribute it and/or modify it
	20	* under the terms of the GNU General Public License version 2 as published by
	21	* the Free Software Foundation.
	22	*
	23	* Documentation:
	24	* CS5535 documentation available from AMD
	25	*/
	26
f5b2d8b4 JK	27	#include <linux/module.h>
	28	#include <linux/pci.h>
	29	#include <linux/ide.h>
	30
	31	#include "ide-timing.h"
	32
	33	#define MSR_ATAC_BASE 0x51300000
	34	#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
	35	#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
	36	#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
	37	#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
	38	#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
	39	#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
	40	#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
	41	#define ATAC_RESET (MSR_ATAC_BASE+0x10)
	42	#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
	43	#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
	44	#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
	45	#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
	46	#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
	47	#define ATAC_BM0_CMD_PRIM 0x00
	48	#define ATAC_BM0_STS_PRIM 0x02
	49	#define ATAC_BM0_PRD 0x04
	50	#define CS5535_CABLE_DETECT 0x48
	51
	52	/* Format I PIO settings. We seperate out cmd and data for safer timings */
	53
	54	static unsigned int cs5535_pio_cmd_timings[5] =
	55	{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
	56	static unsigned int cs5535_pio_dta_timings[5] =
	57	{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
	58
	59	static unsigned int cs5535_mwdma_timings[3] =
	60	{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
	61
	62	static unsigned int cs5535_udma_timings[5] =
	63	{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
	64
	65	/* Macros to check if the register is the reset value - reset value is an
	66	invalid timing and indicates the register has not been set previously */
	67
	68	#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
	69	#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
	70
	71	/****
	72	* cs5535_set_speed - Configure the chipset to the new speed
	73	* @drive: Drive to set up
	74	* @speed: desired speed
	75	*
	76	* cs5535_set_speed() configures the chipset to a new speed.
	77	*/
f212ff28	78	static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
f5b2d8b4 JK	79	{
	80
	81	u32 reg = 0, dummy;
	82	int unit = drive->select.b.unit;
	83
	84
	85	/* Set the PIO timings */
	86	if ((speed & XFER_MODE) == XFER_PIO) {
bc0b0b5c BZ	87	ide_drive_t *pair = &drive->hwif->drives[drive->dn ^ 1];
bc0b0b5c BZ	88	u8 cmd, pioa;
f5b2d8b4	89
bc0b0b5c BZ	90	cmd = pioa = speed - XFER_PIO_0;
	91
	92	if (pair->present) {
	93	u8 piob = ide_get_best_pio_mode(pair, 255, 4);
	94
	95	if (piob < cmd)
	96	cmd = piob;
	97	}
f5b2d8b4 JK	98
	99	/* Write the speed of the current drive */
	100	reg = (cs5535_pio_cmd_timings[cmd] << 16) \|
	101	cs5535_pio_dta_timings[pioa];
	102	wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
	103
	104	/* And if nessesary - change the speed of the other drive */
	105	rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
	106
	107	if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
	108	cs5535_pio_cmd_timings[cmd]) {
	109	reg &= 0x0000FFFF;
	110	reg \|= cs5535_pio_cmd_timings[cmd] << 16;
	111	wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
	112	}
	113
	114	/* Set bit 31 of the DMA register for PIO format 1 timings */
	115	rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
	116	wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
	117	reg \| 0x80000000UL, 0);
	118	} else {
	119	rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
	120
	121	reg &= 0x80000000UL; /* Preserve the PIO format bit */
	122
32a70a81	123	if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
f5b2d8b4 JK	124	reg \|= cs5535_udma_timings[speed - XFER_UDMA_0];
	125	else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
	126	reg \|= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
	127	else
	128	return;
	129
	130	wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
	131	}
	132	}
	133
88b2b32b BZ	134	/**
	135	* cs5535_set_dma_mode - set host controller for DMA mode
	136	* @drive: drive
	137	* @speed: DMA mode
f5b2d8b4	138	*
88b2b32b	139	* Programs the chipset for DMA mode.
f5b2d8b4	140	*/
249aa4ff	141
88b2b32b BZ	142	static void cs5535_set_dma_mode(ide_drive_t *drive, const u8 speed)
88b2b32b BZ	143	{
f5b2d8b4	144	cs5535_set_speed(drive, speed);
f5b2d8b4 JK	145	}
f5b2d8b4 JK	146
26bcb879	147	/**
88b2b32b	148	* cs5535_set_pio_mode - set host controller for PIO mode
26bcb879 BZ	149	* @drive: drive
26bcb879 BZ	150	* @pio: PIO mode number
f5b2d8b4 JK	151	*
	152	* A callback from the upper layers for PIO-only tuning.
	153	*/
26bcb879 BZ	154
26bcb879 BZ	155	static void cs5535_set_pio_mode(ide_drive_t *drive, const u8 pio)
f5b2d8b4	156	{
bc0b0b5c	157	cs5535_set_speed(drive, XFER_PIO_0 + pio);
f5b2d8b4 JK	158	}
f5b2d8b4 JK	159
f5b2d8b4 JK	160	static u8 __devinit cs5535_cable_detect(struct pci_dev *dev)
	161	{
	162	u8 bit;
	163
	164	/* if a 80 wire cable was detected */
	165	pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
49521f97 BZ	166
49521f97 BZ	167	return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
f5b2d8b4 JK	168	}
	169
	170	/****
	171	* init_hwif_cs5535 - Initialize one ide cannel
	172	* @hwif: Channel descriptor
	173	*
	174	* This gets invoked by the IDE driver once for each channel. It
	175	* performs channel-specific pre-initialization before drive probing.
	176	*
	177	*/
	178	static void __devinit init_hwif_cs5535(ide_hwif_t *hwif)
	179	{
f5b2d8b4 JK	180	hwif->autodma = 0;
f5b2d8b4 JK	181
26bcb879	182	hwif->set_pio_mode = &cs5535_set_pio_mode;
88b2b32b	183	hwif->set_dma_mode = &cs5535_set_dma_mode;
7bda292d BZ	184
	185	hwif->drives[1].autotune = hwif->drives[0].autotune = 1;
	186
	187	if (hwif->dma_base == 0)
	188	return;
	189
f5b2d8b4 JK	190	hwif->atapi_dma = 1;
	191	hwif->ultra_mask = 0x1F;
	192	hwif->mwdma_mask = 0x07;
	193
49521f97	194	hwif->cbl = cs5535_cable_detect(hwif->pci_dev);
f5b2d8b4 JK	195
	196	if (!noautodma)
	197	hwif->autodma = 1;
	198
7bda292d	199	hwif->drives[1].autodma = hwif->drives[0].autodma = hwif->autodma;
f5b2d8b4 JK	200	}
	201
	202	static ide_pci_device_t cs5535_chipset __devinitdata = {
	203	.name = "CS5535",
	204	.init_hwif = init_hwif_cs5535,
f5b2d8b4 JK	205	.autodma = AUTODMA,
f5b2d8b4 JK	206	.bootable = ON_BOARD,
88b2b32b	207	.host_flags = IDE_HFLAG_SINGLE \| IDE_HFLAG_POST_SET_MODE,
4099d143	208	.pio_mask = ATA_PIO4,
f5b2d8b4 JK	209	};
	210
	211	static int __devinit cs5535_init_one(struct pci_dev *dev,
	212	const struct pci_device_id *id)
	213	{
	214	return ide_setup_pci_device(dev, &cs5535_chipset);
	215	}
	216
	217	static struct pci_device_id cs5535_pci_tbl[] =
	218	{
	219	{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_IDE, PCI_ANY_ID,
	220	PCI_ANY_ID, 0, 0, 0},
	221	{ 0, },
	222	};
	223
	224	MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
	225
	226	static struct pci_driver driver = {
	227	.name = "CS5535_IDE",
	228	.id_table = cs5535_pci_tbl,
	229	.probe = cs5535_init_one,
	230	};
	231
	232	static int __init cs5535_ide_init(void)
	233	{
	234	return ide_pci_register_driver(&driver);
	235	}
	236
	237	module_init(cs5535_ide_init);
	238
	239	MODULE_AUTHOR("AMD");
	240	MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
	241	MODULE_LICENSE("GPL");