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1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002 | |
3 | * | |
4 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * May be copied or modified under the terms of the GNU General Public License | |
6 | * | |
7 | * | |
8 | * 00:12.0 Unknown mass storage controller: | |
9 | * Triones Technologies, Inc. | |
10 | * Unknown device 0003 (rev 01) | |
11 | * | |
12 | * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010) | |
13 | * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030) | |
14 | * hde: DMA 2 (0x0000 0x0002) (0x0000 0x0010) | |
15 | * hdf: DMA 2 (0x0002 0x0012) (0x0010 0x0030) | |
16 | * hdg: DMA 1 (0x0012 0x0052) (0x0030 0x0070) | |
17 | * hdh: DMA 1 (0x0052 0x0252) (0x0070 0x00f0) | |
18 | * | |
19 | * ide-pci.c reference | |
20 | * | |
21 | * Since there are two cards that report almost identically, | |
22 | * the only discernable difference is the values reported in pcicmd. | |
23 | * Booting-BIOS card or HPT363 :: pcicmd == 0x07 | |
24 | * Non-bootable card or HPT343 :: pcicmd == 0x05 | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | #include <linux/module.h> |
28 | #include <linux/types.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/timer.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/blkdev.h> | |
35 | #include <linux/hdreg.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/ide.h> | |
40 | ||
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> | |
43 | ||
44 | #define HPT343_DEBUG_DRIVE_INFO 0 | |
45 | ||
88b2b32b | 46 | static void hpt34x_set_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
47 | { |
48 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
1da177e4 LT |
49 | u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0; |
50 | u8 hi_speed, lo_speed; | |
51 | ||
52 | hi_speed = speed >> 4; | |
53 | lo_speed = speed & 0x0f; | |
54 | ||
55 | if (hi_speed & 7) { | |
56 | hi_speed = (hi_speed & 4) ? 0x01 : 0x10; | |
57 | } else { | |
58 | lo_speed <<= 5; | |
59 | lo_speed >>= 5; | |
60 | } | |
61 | ||
62 | pci_read_config_dword(dev, 0x44, ®1); | |
63 | pci_read_config_dword(dev, 0x48, ®2); | |
64 | tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn)))); | |
296d9bcc | 65 | tmp2 = ((hi_speed << drive->dn) | (reg2 & ~(0x11 << drive->dn))); |
1da177e4 LT |
66 | pci_write_config_dword(dev, 0x44, tmp1); |
67 | pci_write_config_dword(dev, 0x48, tmp2); | |
68 | ||
69 | #if HPT343_DEBUG_DRIVE_INFO | |
70 | printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \ | |
71 | " (0x%02x 0x%02x)\n", | |
72 | drive->name, ide_xfer_verbose(speed), | |
73 | drive->dn, reg1, tmp1, reg2, tmp2, | |
74 | hi_speed, lo_speed); | |
75 | #endif /* HPT343_DEBUG_DRIVE_INFO */ | |
1da177e4 LT |
76 | } |
77 | ||
26bcb879 | 78 | static void hpt34x_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 79 | { |
88b2b32b | 80 | hpt34x_set_mode(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
81 | } |
82 | ||
1da177e4 LT |
83 | /* |
84 | * If the BIOS does not set the IO base addaress to XX00, 343 will fail. | |
85 | */ | |
86 | #define HPT34X_PCI_INIT_REG 0x80 | |
87 | ||
88 | static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name) | |
89 | { | |
90 | int i = 0; | |
91 | unsigned long hpt34xIoBase = pci_resource_start(dev, 4); | |
92 | unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c }; | |
93 | unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 }; | |
94 | u16 cmd; | |
95 | unsigned long flags; | |
96 | ||
97 | local_irq_save(flags); | |
98 | ||
99 | pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00); | |
100 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
101 | ||
9702b5d5 | 102 | if (cmd & PCI_COMMAND_MEMORY) |
1da177e4 | 103 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0); |
9702b5d5 | 104 | else |
1da177e4 | 105 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); |
1da177e4 LT |
106 | |
107 | /* | |
108 | * Since 20-23 can be assigned and are R/W, we correct them. | |
109 | */ | |
110 | pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO); | |
111 | for(i=0; i<4; i++) { | |
112 | dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]); | |
113 | dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i]; | |
114 | dev->resource[i].flags = IORESOURCE_IO; | |
115 | pci_write_config_dword(dev, | |
116 | (PCI_BASE_ADDRESS_0 + (i * 4)), | |
117 | dev->resource[i].start); | |
118 | } | |
119 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
120 | ||
121 | local_irq_restore(flags); | |
122 | ||
123 | return dev->irq; | |
124 | } | |
125 | ||
126 | static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif) | |
127 | { | |
128 | u16 pcicmd = 0; | |
129 | ||
130 | hwif->autodma = 0; | |
131 | ||
26bcb879 | 132 | hwif->set_pio_mode = &hpt34x_set_pio_mode; |
88b2b32b BZ |
133 | hwif->set_dma_mode = &hpt34x_set_mode; |
134 | ||
1da177e4 LT |
135 | hwif->drives[0].autotune = 1; |
136 | hwif->drives[1].autotune = 1; | |
137 | ||
138 | pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd); | |
139 | ||
140 | if (!hwif->dma_base) | |
141 | return; | |
142 | ||
76e1faa7 | 143 | #ifdef CONFIG_HPT34X_AUTODMA |
1da177e4 LT |
144 | hwif->ultra_mask = 0x07; |
145 | hwif->mwdma_mask = 0x07; | |
146 | hwif->swdma_mask = 0x07; | |
76e1faa7 | 147 | #endif |
1da177e4 | 148 | |
1da177e4 LT |
149 | if (!noautodma) |
150 | hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0; | |
151 | hwif->drives[0].autodma = hwif->autodma; | |
152 | hwif->drives[1].autodma = hwif->autodma; | |
153 | } | |
154 | ||
155 | static ide_pci_device_t hpt34x_chipset __devinitdata = { | |
156 | .name = "HPT34X", | |
157 | .init_chipset = init_chipset_hpt34x, | |
158 | .init_hwif = init_hwif_hpt34x, | |
1da177e4 LT |
159 | .autodma = NOAUTODMA, |
160 | .bootable = NEVER_BOARD, | |
4099d143 BZ |
161 | .extra = 16, |
162 | .pio_mask = ATA_PIO5, | |
1da177e4 LT |
163 | }; |
164 | ||
165 | static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
166 | { | |
167 | ide_pci_device_t *d = &hpt34x_chipset; | |
168 | static char *chipset_names[] = {"HPT343", "HPT345"}; | |
169 | u16 pcicmd = 0; | |
170 | ||
171 | pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
172 | ||
173 | d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0]; | |
174 | d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD; | |
175 | ||
176 | return ide_setup_pci_device(dev, d); | |
177 | } | |
178 | ||
179 | static struct pci_device_id hpt34x_pci_tbl[] = { | |
180 | { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
181 | { 0, }, | |
182 | }; | |
183 | MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl); | |
184 | ||
185 | static struct pci_driver driver = { | |
186 | .name = "HPT34x_IDE", | |
187 | .id_table = hpt34x_pci_tbl, | |
188 | .probe = hpt34x_init_one, | |
189 | }; | |
190 | ||
82ab1eec | 191 | static int __init hpt34x_ide_init(void) |
1da177e4 LT |
192 | { |
193 | return ide_pci_register_driver(&driver); | |
194 | } | |
195 | ||
196 | module_init(hpt34x_ide_init); | |
197 | ||
198 | MODULE_AUTHOR("Andre Hedrick"); | |
199 | MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE"); | |
200 | MODULE_LICENSE("GPL"); |