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1da177e4 | 1 | /* |
26ccb802 | 2 | * linux/drivers/ide/pci/hpt366.c Version 0.51 Jun 04, 2006 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
5 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
6 | * Portions Copyright (C) 2003 Red Hat Inc | |
836c0063 | 7 | * Portions Copyright (C) 2005-2006 MontaVista Software, Inc. |
1da177e4 LT |
8 | * |
9 | * Thanks to HighPoint Technologies for their assistance, and hardware. | |
10 | * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his | |
11 | * donation of an ABit BP6 mainboard, processor, and memory acellerated | |
12 | * development and support. | |
13 | * | |
b39b01ff | 14 | * |
836c0063 SS |
15 | * HighPoint has its own drivers (open source except for the RAID part) |
16 | * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/. | |
17 | * This may be useful to anyone wanting to work on this driver, however do not | |
18 | * trust them too much since the code tends to become less and less meaningful | |
19 | * as the time passes... :-/ | |
b39b01ff | 20 | * |
1da177e4 LT |
21 | * Note that final HPT370 support was done by force extraction of GPL. |
22 | * | |
23 | * - add function for getting/setting power status of drive | |
24 | * - the HPT370's state machine can get confused. reset it before each dma | |
25 | * xfer to prevent that from happening. | |
26 | * - reset state engine whenever we get an error. | |
27 | * - check for busmaster state at end of dma. | |
28 | * - use new highpoint timings. | |
29 | * - detect bus speed using highpoint register. | |
30 | * - use pll if we don't have a clock table. added a 66MHz table that's | |
31 | * just 2x the 33MHz table. | |
32 | * - removed turnaround. NOTE: we never want to switch between pll and | |
33 | * pci clocks as the chip can glitch in those cases. the highpoint | |
34 | * approved workaround slows everything down too much to be useful. in | |
35 | * addition, we would have to serialize access to each chip. | |
36 | * Adrian Sun <a.sun@sun.com> | |
37 | * | |
38 | * add drive timings for 66MHz PCI bus, | |
39 | * fix ATA Cable signal detection, fix incorrect /proc info | |
40 | * add /proc display for per-drive PIO/DMA/UDMA mode and | |
41 | * per-channel ATA-33/66 Cable detect. | |
42 | * Duncan Laurie <void@sun.com> | |
43 | * | |
44 | * fixup /proc output for multiple controllers | |
45 | * Tim Hockin <thockin@sun.com> | |
46 | * | |
47 | * On hpt366: | |
48 | * Reset the hpt366 on error, reset on dma | |
49 | * Fix disabling Fast Interrupt hpt366. | |
50 | * Mike Waychison <crlf@sun.com> | |
51 | * | |
52 | * Added support for 372N clocking and clock switching. The 372N needs | |
53 | * different clocks on read/write. This requires overloading rw_disk and | |
54 | * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for | |
55 | * keeping me sane. | |
56 | * Alan Cox <alan@redhat.com> | |
57 | * | |
836c0063 SS |
58 | * - fix the clock turnaround code: it was writing to the wrong ports when |
59 | * called for the secondary channel, caching the current clock mode per- | |
60 | * channel caused the cached register value to get out of sync with the | |
61 | * actual one, the channels weren't serialized, the turnaround shouldn't | |
62 | * be done on 66 MHz PCI bus | |
63 | * - avoid calibrating PLL twice as the second time results in a wrong PCI | |
64 | * frequency and thus in the wrong timings for the secondary channel | |
e139b0b0 SS |
65 | * - disable UltraATA/133 for HPT372 and UltraATA/100 for HPT370 by default |
66 | * as the ATA clock being used does not allow for this speed anyway | |
836c0063 SS |
67 | * - add support for HPT302N and HPT371N clocking (the same as for HPT372N) |
68 | * - HPT371/N are single channel chips, so avoid touching the primary channel | |
69 | * which exists only virtually (there's no pins for it) | |
471a0bda SS |
70 | * - fix/remove bad/unused timing tables and use one set of tables for the whole |
71 | * HPT37x chip family; save space by introducing the separate transfer mode | |
72 | * table in which the mode lookup is done | |
26c068da SS |
73 | * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives |
74 | * the wrong PCI frequency since DPLL has already been calibrated by BIOS | |
33b18a60 SS |
75 | * - fix the hotswap code: it caused RESET- to glitch when tristating the bus, |
76 | * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead | |
73d1dd93 SS |
77 | * - pass to init_chipset() handlers a copy of the IDE PCI device structure as |
78 | * they tamper with its fields | |
90778574 SS |
79 | * - prefix the driver startup messages with the real chip name |
80 | * - claim the extra 240 bytes of I/O space for all chips | |
e139b0b0 | 81 | * - optimize the rate masking/filtering and the drive list lookup code |
b4586715 | 82 | * - use pci_get_slot() to get to the function 1 of HPT36x/374 |
abc4ad4c SS |
83 | * - cache the channel's MCRs' offset; only touch the relevant MCR when detecting |
84 | * the cable type on HPT374's function 1 | |
85 | * - rename all the register related variables consistently | |
26ccb802 SS |
86 | * - move the interrupt twiddling code from the speedproc handlers into the |
87 | * init_hwif handler, also grouping all the DMA related code together there; | |
88 | * simplify the init_chipset handler | |
89 | * - merge two HPT37x speedproc handlers and fix the PIO timing register mask | |
90 | * there; make HPT36x speedproc handler look the same way as the HPT37x one | |
91 | * - fix the tuneproc handler to always set the PIO mode requested, not the | |
92 | * best possible one | |
836c0063 | 93 | * <source@mvista.com> |
1da177e4 LT |
94 | */ |
95 | ||
1da177e4 LT |
96 | #include <linux/types.h> |
97 | #include <linux/module.h> | |
98 | #include <linux/kernel.h> | |
99 | #include <linux/delay.h> | |
100 | #include <linux/timer.h> | |
101 | #include <linux/mm.h> | |
102 | #include <linux/ioport.h> | |
103 | #include <linux/blkdev.h> | |
104 | #include <linux/hdreg.h> | |
105 | ||
106 | #include <linux/interrupt.h> | |
107 | #include <linux/pci.h> | |
108 | #include <linux/init.h> | |
109 | #include <linux/ide.h> | |
110 | ||
111 | #include <asm/uaccess.h> | |
112 | #include <asm/io.h> | |
113 | #include <asm/irq.h> | |
114 | ||
115 | /* various tuning parameters */ | |
116 | #define HPT_RESET_STATE_ENGINE | |
836c0063 SS |
117 | #undef HPT_DELAY_INTERRUPT |
118 | #define HPT_SERIALIZE_IO 0 | |
1da177e4 LT |
119 | |
120 | static const char *quirk_drives[] = { | |
121 | "QUANTUM FIREBALLlct08 08", | |
122 | "QUANTUM FIREBALLP KA6.4", | |
123 | "QUANTUM FIREBALLP LM20.4", | |
124 | "QUANTUM FIREBALLP LM20.5", | |
125 | NULL | |
126 | }; | |
127 | ||
128 | static const char *bad_ata100_5[] = { | |
129 | "IBM-DTLA-307075", | |
130 | "IBM-DTLA-307060", | |
131 | "IBM-DTLA-307045", | |
132 | "IBM-DTLA-307030", | |
133 | "IBM-DTLA-307020", | |
134 | "IBM-DTLA-307015", | |
135 | "IBM-DTLA-305040", | |
136 | "IBM-DTLA-305030", | |
137 | "IBM-DTLA-305020", | |
138 | "IC35L010AVER07-0", | |
139 | "IC35L020AVER07-0", | |
140 | "IC35L030AVER07-0", | |
141 | "IC35L040AVER07-0", | |
142 | "IC35L060AVER07-0", | |
143 | "WDC AC310200R", | |
144 | NULL | |
145 | }; | |
146 | ||
147 | static const char *bad_ata66_4[] = { | |
148 | "IBM-DTLA-307075", | |
149 | "IBM-DTLA-307060", | |
150 | "IBM-DTLA-307045", | |
151 | "IBM-DTLA-307030", | |
152 | "IBM-DTLA-307020", | |
153 | "IBM-DTLA-307015", | |
154 | "IBM-DTLA-305040", | |
155 | "IBM-DTLA-305030", | |
156 | "IBM-DTLA-305020", | |
157 | "IC35L010AVER07-0", | |
158 | "IC35L020AVER07-0", | |
159 | "IC35L030AVER07-0", | |
160 | "IC35L040AVER07-0", | |
161 | "IC35L060AVER07-0", | |
162 | "WDC AC310200R", | |
163 | NULL | |
164 | }; | |
165 | ||
166 | static const char *bad_ata66_3[] = { | |
167 | "WDC AC310200R", | |
168 | NULL | |
169 | }; | |
170 | ||
171 | static const char *bad_ata33[] = { | |
172 | "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", | |
173 | "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", | |
174 | "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", | |
175 | "Maxtor 90510D4", | |
176 | "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", | |
177 | "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", | |
178 | "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", | |
179 | NULL | |
180 | }; | |
181 | ||
471a0bda SS |
182 | static u8 xfer_speeds[] = { |
183 | XFER_UDMA_6, | |
184 | XFER_UDMA_5, | |
185 | XFER_UDMA_4, | |
186 | XFER_UDMA_3, | |
187 | XFER_UDMA_2, | |
188 | XFER_UDMA_1, | |
189 | XFER_UDMA_0, | |
190 | ||
191 | XFER_MW_DMA_2, | |
192 | XFER_MW_DMA_1, | |
193 | XFER_MW_DMA_0, | |
194 | ||
195 | XFER_PIO_4, | |
196 | XFER_PIO_3, | |
197 | XFER_PIO_2, | |
198 | XFER_PIO_1, | |
199 | XFER_PIO_0 | |
1da177e4 LT |
200 | }; |
201 | ||
471a0bda SS |
202 | /* Key for bus clock timings |
203 | * 36x 37x | |
204 | * bits bits | |
205 | * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. | |
206 | * cycles = value + 1 | |
207 | * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. | |
208 | * cycles = value + 1 | |
209 | * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file | |
210 | * register access. | |
211 | * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file | |
212 | * register access. | |
213 | * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer. | |
214 | * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock. | |
215 | * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and | |
216 | * MW DMA xfer. | |
217 | * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for | |
218 | * task file register access. | |
219 | * 28 28 UDMA enable. | |
220 | * 29 29 DMA enable. | |
221 | * 30 30 PIO MST enable. If set, the chip is in bus master mode during | |
222 | * PIO xfer. | |
223 | * 31 31 FIFO enable. | |
1da177e4 | 224 | */ |
1da177e4 | 225 | |
471a0bda SS |
226 | static u32 forty_base_hpt36x[] = { |
227 | /* XFER_UDMA_6 */ 0x900fd943, | |
228 | /* XFER_UDMA_5 */ 0x900fd943, | |
229 | /* XFER_UDMA_4 */ 0x900fd943, | |
230 | /* XFER_UDMA_3 */ 0x900ad943, | |
231 | /* XFER_UDMA_2 */ 0x900bd943, | |
232 | /* XFER_UDMA_1 */ 0x9008d943, | |
233 | /* XFER_UDMA_0 */ 0x9008d943, | |
234 | ||
235 | /* XFER_MW_DMA_2 */ 0xa008d943, | |
236 | /* XFER_MW_DMA_1 */ 0xa010d955, | |
237 | /* XFER_MW_DMA_0 */ 0xa010d9fc, | |
238 | ||
239 | /* XFER_PIO_4 */ 0xc008d963, | |
240 | /* XFER_PIO_3 */ 0xc010d974, | |
241 | /* XFER_PIO_2 */ 0xc010d997, | |
242 | /* XFER_PIO_1 */ 0xc010d9c7, | |
243 | /* XFER_PIO_0 */ 0xc018d9d9 | |
1da177e4 LT |
244 | }; |
245 | ||
471a0bda SS |
246 | static u32 thirty_three_base_hpt36x[] = { |
247 | /* XFER_UDMA_6 */ 0x90c9a731, | |
248 | /* XFER_UDMA_5 */ 0x90c9a731, | |
249 | /* XFER_UDMA_4 */ 0x90c9a731, | |
250 | /* XFER_UDMA_3 */ 0x90cfa731, | |
251 | /* XFER_UDMA_2 */ 0x90caa731, | |
252 | /* XFER_UDMA_1 */ 0x90cba731, | |
253 | /* XFER_UDMA_0 */ 0x90c8a731, | |
254 | ||
255 | /* XFER_MW_DMA_2 */ 0xa0c8a731, | |
256 | /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */ | |
257 | /* XFER_MW_DMA_0 */ 0xa0c8a797, | |
258 | ||
259 | /* XFER_PIO_4 */ 0xc0c8a731, | |
260 | /* XFER_PIO_3 */ 0xc0c8a742, | |
261 | /* XFER_PIO_2 */ 0xc0d0a753, | |
262 | /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */ | |
263 | /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */ | |
1da177e4 LT |
264 | }; |
265 | ||
471a0bda SS |
266 | static u32 twenty_five_base_hpt36x[] = { |
267 | /* XFER_UDMA_6 */ 0x90c98521, | |
268 | /* XFER_UDMA_5 */ 0x90c98521, | |
269 | /* XFER_UDMA_4 */ 0x90c98521, | |
270 | /* XFER_UDMA_3 */ 0x90cf8521, | |
271 | /* XFER_UDMA_2 */ 0x90cf8521, | |
272 | /* XFER_UDMA_1 */ 0x90cb8521, | |
273 | /* XFER_UDMA_0 */ 0x90cb8521, | |
274 | ||
275 | /* XFER_MW_DMA_2 */ 0xa0ca8521, | |
276 | /* XFER_MW_DMA_1 */ 0xa0ca8532, | |
277 | /* XFER_MW_DMA_0 */ 0xa0ca8575, | |
278 | ||
279 | /* XFER_PIO_4 */ 0xc0ca8521, | |
280 | /* XFER_PIO_3 */ 0xc0ca8532, | |
281 | /* XFER_PIO_2 */ 0xc0ca8542, | |
282 | /* XFER_PIO_1 */ 0xc0d08572, | |
283 | /* XFER_PIO_0 */ 0xc0d08585 | |
1da177e4 LT |
284 | }; |
285 | ||
471a0bda SS |
286 | static u32 thirty_three_base_hpt37x[] = { |
287 | /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */ | |
288 | /* XFER_UDMA_5 */ 0x12446231, | |
289 | /* XFER_UDMA_4 */ 0x12446231, | |
290 | /* XFER_UDMA_3 */ 0x126c6231, | |
291 | /* XFER_UDMA_2 */ 0x12486231, | |
292 | /* XFER_UDMA_1 */ 0x124c6233, | |
293 | /* XFER_UDMA_0 */ 0x12506297, | |
294 | ||
295 | /* XFER_MW_DMA_2 */ 0x22406c31, | |
296 | /* XFER_MW_DMA_1 */ 0x22406c33, | |
297 | /* XFER_MW_DMA_0 */ 0x22406c97, | |
298 | ||
299 | /* XFER_PIO_4 */ 0x06414e31, | |
300 | /* XFER_PIO_3 */ 0x06414e42, | |
301 | /* XFER_PIO_2 */ 0x06414e53, | |
302 | /* XFER_PIO_1 */ 0x06814e93, | |
303 | /* XFER_PIO_0 */ 0x06814ea7 | |
1da177e4 LT |
304 | }; |
305 | ||
471a0bda SS |
306 | static u32 fifty_base_hpt37x[] = { |
307 | /* XFER_UDMA_6 */ 0x12848242, | |
308 | /* XFER_UDMA_5 */ 0x12848242, | |
309 | /* XFER_UDMA_4 */ 0x12ac8242, | |
310 | /* XFER_UDMA_3 */ 0x128c8242, | |
311 | /* XFER_UDMA_2 */ 0x120c8242, | |
312 | /* XFER_UDMA_1 */ 0x12148254, | |
313 | /* XFER_UDMA_0 */ 0x121882ea, | |
314 | ||
315 | /* XFER_MW_DMA_2 */ 0x22808242, | |
316 | /* XFER_MW_DMA_1 */ 0x22808254, | |
317 | /* XFER_MW_DMA_0 */ 0x228082ea, | |
318 | ||
319 | /* XFER_PIO_4 */ 0x0a81f442, | |
320 | /* XFER_PIO_3 */ 0x0a81f443, | |
321 | /* XFER_PIO_2 */ 0x0a81f454, | |
322 | /* XFER_PIO_1 */ 0x0ac1f465, | |
323 | /* XFER_PIO_0 */ 0x0ac1f48a | |
1da177e4 LT |
324 | }; |
325 | ||
471a0bda SS |
326 | static u32 sixty_six_base_hpt37x[] = { |
327 | /* XFER_UDMA_6 */ 0x1c869c62, | |
328 | /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */ | |
329 | /* XFER_UDMA_4 */ 0x1c8a9c62, | |
330 | /* XFER_UDMA_3 */ 0x1c8e9c62, | |
331 | /* XFER_UDMA_2 */ 0x1c929c62, | |
332 | /* XFER_UDMA_1 */ 0x1c9a9c62, | |
333 | /* XFER_UDMA_0 */ 0x1c829c62, | |
334 | ||
335 | /* XFER_MW_DMA_2 */ 0x2c829c62, | |
336 | /* XFER_MW_DMA_1 */ 0x2c829c66, | |
337 | /* XFER_MW_DMA_0 */ 0x2c829d2e, | |
338 | ||
339 | /* XFER_PIO_4 */ 0x0c829c62, | |
340 | /* XFER_PIO_3 */ 0x0c829c84, | |
341 | /* XFER_PIO_2 */ 0x0c829ca6, | |
342 | /* XFER_PIO_1 */ 0x0d029d26, | |
343 | /* XFER_PIO_0 */ 0x0d029d5e | |
1da177e4 LT |
344 | }; |
345 | ||
1da177e4 LT |
346 | #define HPT366_DEBUG_DRIVE_INFO 0 |
347 | #define HPT374_ALLOW_ATA133_6 0 | |
348 | #define HPT371_ALLOW_ATA133_6 0 | |
349 | #define HPT302_ALLOW_ATA133_6 0 | |
836c0063 | 350 | #define HPT372_ALLOW_ATA133_6 0 |
e139b0b0 | 351 | #define HPT370_ALLOW_ATA100_5 0 |
1da177e4 LT |
352 | #define HPT366_ALLOW_ATA66_4 1 |
353 | #define HPT366_ALLOW_ATA66_3 1 | |
354 | #define HPT366_MAX_DEVS 8 | |
355 | ||
356 | #define F_LOW_PCI_33 0x23 | |
357 | #define F_LOW_PCI_40 0x29 | |
358 | #define F_LOW_PCI_50 0x2d | |
359 | #define F_LOW_PCI_66 0x42 | |
360 | ||
b39b01ff AC |
361 | /* |
362 | * Hold all the highpoint quirks and revision information in one | |
363 | * place. | |
364 | */ | |
1da177e4 | 365 | |
b39b01ff AC |
366 | struct hpt_info |
367 | { | |
368 | u8 max_mode; /* Speeds allowed */ | |
e139b0b0 SS |
369 | u8 revision; /* Chipset revision */ |
370 | u8 flags; /* Chipset properties */ | |
b39b01ff | 371 | #define PLL_MODE 1 |
836c0063 SS |
372 | #define IS_3xxN 2 |
373 | #define PCI_66MHZ 4 | |
b39b01ff | 374 | /* Speed table */ |
471a0bda | 375 | u32 *speed; |
b39b01ff AC |
376 | }; |
377 | ||
378 | /* | |
e139b0b0 | 379 | * This wants fixing so that we do everything not by revision |
b39b01ff AC |
380 | * (which breaks on the newest chips) but by creating an |
381 | * enumeration of chip variants and using that | |
382 | */ | |
383 | ||
e139b0b0 | 384 | static __devinit u8 hpt_revision(struct pci_dev *dev) |
1da177e4 | 385 | { |
e139b0b0 SS |
386 | u8 rev = 0; |
387 | ||
388 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); | |
1da177e4 LT |
389 | |
390 | switch(dev->device) { | |
391 | /* Remap new 372N onto 372 */ | |
392 | case PCI_DEVICE_ID_TTI_HPT372N: | |
f36702b4 AM |
393 | rev = PCI_DEVICE_ID_TTI_HPT372; |
394 | break; | |
1da177e4 | 395 | case PCI_DEVICE_ID_TTI_HPT374: |
f36702b4 AM |
396 | rev = PCI_DEVICE_ID_TTI_HPT374; |
397 | break; | |
1da177e4 | 398 | case PCI_DEVICE_ID_TTI_HPT371: |
f36702b4 AM |
399 | rev = PCI_DEVICE_ID_TTI_HPT371; |
400 | break; | |
1da177e4 | 401 | case PCI_DEVICE_ID_TTI_HPT302: |
f36702b4 AM |
402 | rev = PCI_DEVICE_ID_TTI_HPT302; |
403 | break; | |
1da177e4 | 404 | case PCI_DEVICE_ID_TTI_HPT372: |
f36702b4 AM |
405 | rev = PCI_DEVICE_ID_TTI_HPT372; |
406 | break; | |
1da177e4 LT |
407 | default: |
408 | break; | |
409 | } | |
e139b0b0 | 410 | return rev; |
1da177e4 LT |
411 | } |
412 | ||
e139b0b0 SS |
413 | static int check_in_drive_list(ide_drive_t *drive, const char **list) |
414 | { | |
415 | struct hd_driveid *id = drive->id; | |
416 | ||
417 | while (*list) | |
418 | if (!strcmp(*list++,id->model)) | |
419 | return 1; | |
420 | return 0; | |
421 | } | |
1da177e4 | 422 | |
e139b0b0 | 423 | static u8 hpt3xx_ratemask(ide_drive_t *drive) |
1da177e4 | 424 | { |
e139b0b0 SS |
425 | struct hpt_info *info = ide_get_hwifdata(HWIF(drive)); |
426 | u8 mode = info->max_mode; | |
427 | ||
b39b01ff | 428 | if (!eighty_ninty_three(drive) && mode) |
1da177e4 LT |
429 | mode = min(mode, (u8)1); |
430 | return mode; | |
431 | } | |
432 | ||
433 | /* | |
434 | * Note for the future; the SATA hpt37x we must set | |
435 | * either PIO or UDMA modes 0,4,5 | |
436 | */ | |
437 | ||
e139b0b0 | 438 | static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed) |
1da177e4 | 439 | { |
e139b0b0 | 440 | struct hpt_info *info = ide_get_hwifdata(HWIF(drive)); |
1da177e4 LT |
441 | u8 mode = hpt3xx_ratemask(drive); |
442 | ||
443 | if (drive->media != ide_disk) | |
444 | return min(speed, (u8)XFER_PIO_4); | |
445 | ||
e139b0b0 | 446 | switch (mode) { |
1da177e4 LT |
447 | case 0x04: |
448 | speed = min(speed, (u8)XFER_UDMA_6); | |
449 | break; | |
450 | case 0x03: | |
451 | speed = min(speed, (u8)XFER_UDMA_5); | |
b39b01ff | 452 | if (info->revision >= 5) |
1da177e4 | 453 | break; |
e139b0b0 SS |
454 | if (!check_in_drive_list(drive, bad_ata100_5)) |
455 | goto check_bad_ata33; | |
456 | /* fall thru */ | |
1da177e4 | 457 | case 0x02: |
f36702b4 | 458 | speed = min_t(u8, speed, XFER_UDMA_4); |
1da177e4 LT |
459 | /* |
460 | * CHECK ME, Does this need to be set to 5 ?? | |
461 | */ | |
b39b01ff | 462 | if (info->revision >= 3) |
e139b0b0 SS |
463 | goto check_bad_ata33; |
464 | if (HPT366_ALLOW_ATA66_4 && | |
465 | !check_in_drive_list(drive, bad_ata66_4)) | |
466 | goto check_bad_ata33; | |
467 | ||
f36702b4 | 468 | speed = min_t(u8, speed, XFER_UDMA_3); |
e139b0b0 SS |
469 | if (HPT366_ALLOW_ATA66_3 && |
470 | !check_in_drive_list(drive, bad_ata66_3)) | |
471 | goto check_bad_ata33; | |
472 | /* fall thru */ | |
1da177e4 | 473 | case 0x01: |
f36702b4 | 474 | speed = min_t(u8, speed, XFER_UDMA_2); |
e139b0b0 SS |
475 | |
476 | check_bad_ata33: | |
477 | if (info->revision >= 4) | |
1da177e4 | 478 | break; |
e139b0b0 SS |
479 | if (!check_in_drive_list(drive, bad_ata33)) |
480 | break; | |
481 | /* fall thru */ | |
1da177e4 LT |
482 | case 0x00: |
483 | default: | |
f36702b4 | 484 | speed = min_t(u8, speed, XFER_MW_DMA_2); |
1da177e4 LT |
485 | break; |
486 | } | |
487 | return speed; | |
488 | } | |
489 | ||
471a0bda | 490 | static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table) |
1da177e4 | 491 | { |
471a0bda SS |
492 | int i; |
493 | ||
494 | /* | |
495 | * Lookup the transfer mode table to get the index into | |
496 | * the timing table. | |
497 | * | |
498 | * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used. | |
499 | */ | |
500 | for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++) | |
501 | if (xfer_speeds[i] == speed) | |
502 | break; | |
503 | return chipset_table[i]; | |
1da177e4 LT |
504 | } |
505 | ||
506 | static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed) | |
507 | { | |
abc4ad4c SS |
508 | ide_hwif_t *hwif = HWIF(drive); |
509 | struct pci_dev *dev = hwif->pci_dev; | |
510 | struct hpt_info *info = ide_get_hwifdata (hwif); | |
511 | u8 speed = hpt3xx_ratefilter(drive, xferspeed); | |
512 | u8 itr_addr = drive->dn ? 0x44 : 0x40; | |
abc4ad4c | 513 | u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x30070000 : 0xc0000000; |
26ccb802 SS |
514 | u32 new_itr = pci_bus_clock_list(speed, info->speed); |
515 | u32 old_itr = 0; | |
b39b01ff | 516 | |
1da177e4 | 517 | /* |
abc4ad4c SS |
518 | * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) |
519 | * to avoid problems handling I/O errors later | |
1da177e4 | 520 | */ |
abc4ad4c SS |
521 | pci_read_config_dword(dev, itr_addr, &old_itr); |
522 | new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask); | |
523 | new_itr &= ~0xc0000000; | |
1da177e4 | 524 | |
abc4ad4c | 525 | pci_write_config_dword(dev, itr_addr, new_itr); |
1da177e4 LT |
526 | |
527 | return ide_config_drive_speed(drive, speed); | |
528 | } | |
529 | ||
26ccb802 | 530 | static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed) |
1da177e4 | 531 | { |
abc4ad4c SS |
532 | ide_hwif_t *hwif = HWIF(drive); |
533 | struct pci_dev *dev = hwif->pci_dev; | |
534 | struct hpt_info *info = ide_get_hwifdata (hwif); | |
535 | u8 speed = hpt3xx_ratefilter(drive, xferspeed); | |
abc4ad4c | 536 | u8 itr_addr = 0x40 + (drive->dn * 4); |
abc4ad4c | 537 | u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000; |
26ccb802 SS |
538 | u32 new_itr = pci_bus_clock_list(speed, info->speed); |
539 | u32 old_itr = 0; | |
1da177e4 | 540 | |
abc4ad4c SS |
541 | pci_read_config_dword(dev, itr_addr, &old_itr); |
542 | new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask); | |
1da177e4 | 543 | |
b39b01ff | 544 | if (speed < XFER_MW_DMA_0) |
abc4ad4c SS |
545 | new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */ |
546 | pci_write_config_dword(dev, itr_addr, new_itr); | |
1da177e4 LT |
547 | |
548 | return ide_config_drive_speed(drive, speed); | |
549 | } | |
550 | ||
26ccb802 | 551 | static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed) |
1da177e4 | 552 | { |
abc4ad4c | 553 | ide_hwif_t *hwif = HWIF(drive); |
b39b01ff | 554 | struct hpt_info *info = ide_get_hwifdata(hwif); |
1da177e4 | 555 | |
26ccb802 SS |
556 | if (info->revision >= 3) |
557 | return hpt37x_tune_chipset(drive, speed); | |
1da177e4 LT |
558 | else /* hpt368: hpt_minimum_revision(dev, 2) */ |
559 | return hpt36x_tune_chipset(drive, speed); | |
560 | } | |
561 | ||
26ccb802 | 562 | static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio) |
1da177e4 | 563 | { |
26ccb802 SS |
564 | pio = ide_get_best_pio_mode(drive, pio, 4, NULL); |
565 | (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio); | |
1da177e4 LT |
566 | } |
567 | ||
568 | /* | |
569 | * This allows the configuration of ide_pci chipset registers | |
570 | * for cards that learn about the drive's UDMA, DMA, PIO capabilities | |
26ccb802 | 571 | * after the drive is reported by the OS. Initially designed for |
1da177e4 LT |
572 | * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc. |
573 | * | |
1da177e4 | 574 | */ |
26ccb802 | 575 | static int config_chipset_for_dma(ide_drive_t *drive) |
1da177e4 LT |
576 | { |
577 | u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive)); | |
26ccb802 | 578 | ide_hwif_t *hwif = HWIF(drive); |
b39b01ff | 579 | struct hpt_info *info = ide_get_hwifdata(hwif); |
1da177e4 | 580 | |
b39b01ff AC |
581 | if (!speed) |
582 | return 0; | |
583 | ||
584 | /* If we don't have any timings we can't do a lot */ | |
585 | if (info->speed == NULL) | |
1da177e4 LT |
586 | return 0; |
587 | ||
588 | (void) hpt3xx_tune_chipset(drive, speed); | |
589 | return ide_dma_enable(drive); | |
590 | } | |
591 | ||
e139b0b0 | 592 | static int hpt3xx_quirkproc(ide_drive_t *drive) |
1da177e4 | 593 | { |
e139b0b0 SS |
594 | struct hd_driveid *id = drive->id; |
595 | const char **list = quirk_drives; | |
596 | ||
597 | while (*list) | |
598 | if (strstr(id->model, *list++)) | |
599 | return 1; | |
600 | return 0; | |
1da177e4 LT |
601 | } |
602 | ||
26ccb802 | 603 | static void hpt3xx_intrproc(ide_drive_t *drive) |
1da177e4 | 604 | { |
abc4ad4c | 605 | ide_hwif_t *hwif = HWIF(drive); |
1da177e4 LT |
606 | |
607 | if (drive->quirk_list) | |
608 | return; | |
609 | /* drives in the quirk_list may not like intr setups/cleanups */ | |
abc4ad4c | 610 | hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG); |
1da177e4 LT |
611 | } |
612 | ||
26ccb802 | 613 | static void hpt3xx_maskproc(ide_drive_t *drive, int mask) |
1da177e4 | 614 | { |
abc4ad4c SS |
615 | ide_hwif_t *hwif = HWIF(drive); |
616 | struct pci_dev *dev = hwif->pci_dev; | |
617 | struct hpt_info *info = ide_get_hwifdata(hwif); | |
1da177e4 LT |
618 | |
619 | if (drive->quirk_list) { | |
b39b01ff | 620 | if (info->revision >= 3) { |
abc4ad4c SS |
621 | u8 scr1 = 0; |
622 | ||
623 | pci_read_config_byte(dev, 0x5a, &scr1); | |
624 | if (((scr1 & 0x10) >> 4) != mask) { | |
625 | if (mask) | |
626 | scr1 |= 0x10; | |
627 | else | |
628 | scr1 &= ~0x10; | |
629 | pci_write_config_byte(dev, 0x5a, scr1); | |
630 | } | |
1da177e4 | 631 | } else { |
abc4ad4c | 632 | if (mask) |
b39b01ff | 633 | disable_irq(hwif->irq); |
abc4ad4c SS |
634 | else |
635 | enable_irq (hwif->irq); | |
1da177e4 | 636 | } |
abc4ad4c SS |
637 | } else |
638 | hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2), | |
639 | IDE_CONTROL_REG); | |
1da177e4 LT |
640 | } |
641 | ||
26ccb802 | 642 | static int hpt366_config_drive_xfer_rate(ide_drive_t *drive) |
1da177e4 | 643 | { |
26ccb802 | 644 | ide_hwif_t *hwif = HWIF(drive); |
1da177e4 LT |
645 | struct hd_driveid *id = drive->id; |
646 | ||
647 | drive->init_speed = 0; | |
648 | ||
b39b01ff | 649 | if ((id->capability & 1) && drive->autodma) { |
26ccb802 SS |
650 | if (ide_use_dma(drive) && config_chipset_for_dma(drive)) |
651 | return hwif->ide_dma_on(drive); | |
1da177e4 LT |
652 | |
653 | goto fast_ata_pio; | |
654 | ||
655 | } else if ((id->capability & 8) || (id->field_valid & 2)) { | |
656 | fast_ata_pio: | |
26ccb802 | 657 | hpt3xx_tune_drive(drive, 255); |
1da177e4 LT |
658 | return hwif->ide_dma_off_quietly(drive); |
659 | } | |
660 | /* IORDY not supported */ | |
661 | return 0; | |
662 | } | |
663 | ||
664 | /* | |
abc4ad4c | 665 | * This is specific to the HPT366 UDMA chipset |
1da177e4 LT |
666 | * by HighPoint|Triones Technologies, Inc. |
667 | */ | |
abc4ad4c | 668 | static int hpt366_ide_dma_lostirq(ide_drive_t *drive) |
1da177e4 | 669 | { |
abc4ad4c SS |
670 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
671 | u8 mcr1 = 0, mcr3 = 0, scr1 = 0; | |
672 | ||
673 | pci_read_config_byte(dev, 0x50, &mcr1); | |
674 | pci_read_config_byte(dev, 0x52, &mcr3); | |
675 | pci_read_config_byte(dev, 0x5a, &scr1); | |
676 | printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n", | |
677 | drive->name, __FUNCTION__, mcr1, mcr3, scr1); | |
678 | if (scr1 & 0x10) | |
679 | pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); | |
1da177e4 LT |
680 | return __ide_dma_lostirq(drive); |
681 | } | |
682 | ||
683 | static void hpt370_clear_engine (ide_drive_t *drive) | |
684 | { | |
abc4ad4c SS |
685 | ide_hwif_t *hwif = HWIF(drive); |
686 | ||
687 | pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37); | |
1da177e4 LT |
688 | udelay(10); |
689 | } | |
690 | ||
691 | static void hpt370_ide_dma_start(ide_drive_t *drive) | |
692 | { | |
693 | #ifdef HPT_RESET_STATE_ENGINE | |
694 | hpt370_clear_engine(drive); | |
695 | #endif | |
696 | ide_dma_start(drive); | |
697 | } | |
698 | ||
699 | static int hpt370_ide_dma_end (ide_drive_t *drive) | |
700 | { | |
701 | ide_hwif_t *hwif = HWIF(drive); | |
702 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
703 | ||
704 | if (dma_stat & 0x01) { | |
705 | /* wait a little */ | |
706 | udelay(20); | |
707 | dma_stat = hwif->INB(hwif->dma_status); | |
708 | } | |
709 | if ((dma_stat & 0x01) != 0) | |
710 | /* fallthrough */ | |
711 | (void) HWIF(drive)->ide_dma_timeout(drive); | |
712 | ||
713 | return __ide_dma_end(drive); | |
714 | } | |
715 | ||
716 | static void hpt370_lostirq_timeout (ide_drive_t *drive) | |
717 | { | |
718 | ide_hwif_t *hwif = HWIF(drive); | |
abc4ad4c | 719 | u8 bfifo = 0; |
1da177e4 LT |
720 | u8 dma_stat = 0, dma_cmd = 0; |
721 | ||
abc4ad4c | 722 | pci_read_config_byte(HWIF(drive)->pci_dev, hwif->select_data + 2, &bfifo); |
b39b01ff | 723 | printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo); |
1da177e4 LT |
724 | hpt370_clear_engine(drive); |
725 | /* get dma command mode */ | |
726 | dma_cmd = hwif->INB(hwif->dma_command); | |
727 | /* stop dma */ | |
728 | hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command); | |
729 | dma_stat = hwif->INB(hwif->dma_status); | |
730 | /* clear errors */ | |
731 | hwif->OUTB(dma_stat | 0x6, hwif->dma_status); | |
732 | } | |
733 | ||
734 | static int hpt370_ide_dma_timeout (ide_drive_t *drive) | |
735 | { | |
736 | hpt370_lostirq_timeout(drive); | |
737 | hpt370_clear_engine(drive); | |
738 | return __ide_dma_timeout(drive); | |
739 | } | |
740 | ||
741 | static int hpt370_ide_dma_lostirq (ide_drive_t *drive) | |
742 | { | |
743 | hpt370_lostirq_timeout(drive); | |
744 | hpt370_clear_engine(drive); | |
745 | return __ide_dma_lostirq(drive); | |
746 | } | |
747 | ||
748 | /* returns 1 if DMA IRQ issued, 0 otherwise */ | |
749 | static int hpt374_ide_dma_test_irq(ide_drive_t *drive) | |
750 | { | |
751 | ide_hwif_t *hwif = HWIF(drive); | |
752 | u16 bfifo = 0; | |
abc4ad4c | 753 | u8 dma_stat; |
1da177e4 | 754 | |
abc4ad4c | 755 | pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo); |
1da177e4 LT |
756 | if (bfifo & 0x1FF) { |
757 | // printk("%s: %d bytes in FIFO\n", drive->name, bfifo); | |
758 | return 0; | |
759 | } | |
760 | ||
761 | dma_stat = hwif->INB(hwif->dma_status); | |
762 | /* return 1 if INTR asserted */ | |
abc4ad4c | 763 | if (dma_stat & 4) |
1da177e4 LT |
764 | return 1; |
765 | ||
766 | if (!drive->waiting_for_dma) | |
767 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
768 | drive->name, __FUNCTION__); | |
769 | return 0; | |
770 | } | |
771 | ||
abc4ad4c | 772 | static int hpt374_ide_dma_end(ide_drive_t *drive) |
1da177e4 | 773 | { |
1da177e4 | 774 | ide_hwif_t *hwif = HWIF(drive); |
abc4ad4c SS |
775 | struct pci_dev *dev = hwif->pci_dev; |
776 | u8 mcr = 0, mcr_addr = hwif->select_data; | |
777 | u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01; | |
778 | ||
779 | pci_read_config_byte(dev, 0x6a, &bwsr); | |
780 | pci_read_config_byte(dev, mcr_addr, &mcr); | |
781 | if (bwsr & mask) | |
782 | pci_write_config_byte(dev, mcr_addr, mcr | 0x30); | |
1da177e4 LT |
783 | return __ide_dma_end(drive); |
784 | } | |
785 | ||
786 | /** | |
836c0063 SS |
787 | * hpt3xxn_set_clock - perform clock switching dance |
788 | * @hwif: hwif to switch | |
789 | * @mode: clocking mode (0x21 for write, 0x23 otherwise) | |
1da177e4 | 790 | * |
836c0063 SS |
791 | * Switch the DPLL clock on the HPT3xxN devices. This is a right mess. |
792 | * NOTE: avoid touching the disabled primary channel on HPT371N -- it | |
793 | * doesn't physically exist anyway... | |
1da177e4 | 794 | */ |
836c0063 SS |
795 | |
796 | static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) | |
1da177e4 | 797 | { |
836c0063 SS |
798 | u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b); |
799 | ||
800 | if ((scr2 & 0x7f) == mode) | |
801 | return; | |
802 | ||
803 | /* MISC. control register 1 has the channel enable bit... */ | |
804 | mcr1 = hwif->INB(hwif->dma_master + 0x70); | |
805 | ||
1da177e4 | 806 | /* Tristate the bus */ |
836c0063 SS |
807 | if (mcr1 & 0x04) |
808 | hwif->OUTB(0x80, hwif->dma_master + 0x73); | |
809 | hwif->OUTB(0x80, hwif->dma_master + 0x77); | |
810 | ||
1da177e4 | 811 | /* Switch clock and reset channels */ |
836c0063 SS |
812 | hwif->OUTB(mode, hwif->dma_master + 0x7b); |
813 | hwif->OUTB(0xc0, hwif->dma_master + 0x79); | |
814 | ||
1da177e4 | 815 | /* Reset state machines */ |
836c0063 SS |
816 | if (mcr1 & 0x04) |
817 | hwif->OUTB(0x37, hwif->dma_master + 0x70); | |
818 | hwif->OUTB(0x37, hwif->dma_master + 0x74); | |
819 | ||
1da177e4 | 820 | /* Complete reset */ |
836c0063 SS |
821 | hwif->OUTB(0x00, hwif->dma_master + 0x79); |
822 | ||
1da177e4 | 823 | /* Reconnect channels to bus */ |
836c0063 SS |
824 | if (mcr1 & 0x04) |
825 | hwif->OUTB(0x00, hwif->dma_master + 0x73); | |
826 | hwif->OUTB(0x00, hwif->dma_master + 0x77); | |
1da177e4 LT |
827 | } |
828 | ||
829 | /** | |
836c0063 | 830 | * hpt3xxn_rw_disk - prepare for I/O |
1da177e4 LT |
831 | * @drive: drive for command |
832 | * @rq: block request structure | |
833 | * | |
836c0063 | 834 | * This is called when a disk I/O is issued to HPT3xxN. |
1da177e4 LT |
835 | * We need it because of the clock switching. |
836 | */ | |
837 | ||
836c0063 | 838 | static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) |
1da177e4 | 839 | { |
836c0063 SS |
840 | ide_hwif_t *hwif = HWIF(drive); |
841 | u8 wantclock = rq_data_dir(rq) ? 0x23 : 0x21; | |
1da177e4 | 842 | |
836c0063 | 843 | hpt3xxn_set_clock(hwif, wantclock); |
1da177e4 LT |
844 | } |
845 | ||
1da177e4 | 846 | /* |
33b18a60 | 847 | * Set/get power state for a drive. |
abc4ad4c | 848 | * NOTE: affects both drives on each channel. |
1da177e4 | 849 | * |
33b18a60 | 850 | * When we turn the power back on, we need to re-initialize things. |
1da177e4 LT |
851 | */ |
852 | #define TRISTATE_BIT 0x8000 | |
33b18a60 SS |
853 | |
854 | static int hpt3xx_busproc(ide_drive_t *drive, int state) | |
1da177e4 | 855 | { |
abc4ad4c | 856 | ide_hwif_t *hwif = HWIF(drive); |
1da177e4 | 857 | struct pci_dev *dev = hwif->pci_dev; |
abc4ad4c SS |
858 | u8 mcr_addr = hwif->select_data + 2; |
859 | u8 resetmask = hwif->channel ? 0x80 : 0x40; | |
860 | u8 bsr2 = 0; | |
861 | u16 mcr = 0; | |
1da177e4 LT |
862 | |
863 | hwif->bus_state = state; | |
864 | ||
33b18a60 | 865 | /* Grab the status. */ |
abc4ad4c SS |
866 | pci_read_config_word(dev, mcr_addr, &mcr); |
867 | pci_read_config_byte(dev, 0x59, &bsr2); | |
1da177e4 | 868 | |
33b18a60 SS |
869 | /* |
870 | * Set the state. We don't set it if we don't need to do so. | |
871 | * Make sure that the drive knows that it has failed if it's off. | |
872 | */ | |
1da177e4 LT |
873 | switch (state) { |
874 | case BUSSTATE_ON: | |
abc4ad4c | 875 | if (!(bsr2 & resetmask)) |
1da177e4 | 876 | return 0; |
33b18a60 SS |
877 | hwif->drives[0].failures = hwif->drives[1].failures = 0; |
878 | ||
abc4ad4c SS |
879 | pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask); |
880 | pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT); | |
33b18a60 | 881 | return 0; |
1da177e4 | 882 | case BUSSTATE_OFF: |
abc4ad4c | 883 | if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT)) |
1da177e4 | 884 | return 0; |
abc4ad4c | 885 | mcr &= ~TRISTATE_BIT; |
1da177e4 LT |
886 | break; |
887 | case BUSSTATE_TRISTATE: | |
abc4ad4c | 888 | if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT)) |
1da177e4 | 889 | return 0; |
abc4ad4c | 890 | mcr |= TRISTATE_BIT; |
1da177e4 | 891 | break; |
33b18a60 SS |
892 | default: |
893 | return -EINVAL; | |
1da177e4 | 894 | } |
1da177e4 | 895 | |
33b18a60 SS |
896 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; |
897 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
898 | ||
abc4ad4c SS |
899 | pci_write_config_word(dev, mcr_addr, mcr); |
900 | pci_write_config_byte(dev, 0x59, bsr2 | resetmask); | |
1da177e4 LT |
901 | return 0; |
902 | } | |
903 | ||
b39b01ff | 904 | static void __devinit hpt366_clocking(ide_hwif_t *hwif) |
1da177e4 | 905 | { |
abc4ad4c | 906 | u32 itr1 = 0; |
b39b01ff AC |
907 | struct hpt_info *info = ide_get_hwifdata(hwif); |
908 | ||
abc4ad4c | 909 | pci_read_config_dword(hwif->pci_dev, 0x40, &itr1); |
b39b01ff AC |
910 | |
911 | /* detect bus speed by looking at control reg timing: */ | |
abc4ad4c | 912 | switch((itr1 >> 8) & 7) { |
b39b01ff | 913 | case 5: |
471a0bda | 914 | info->speed = forty_base_hpt36x; |
b39b01ff AC |
915 | break; |
916 | case 9: | |
471a0bda | 917 | info->speed = twenty_five_base_hpt36x; |
b39b01ff AC |
918 | break; |
919 | case 7: | |
920 | default: | |
471a0bda | 921 | info->speed = thirty_three_base_hpt36x; |
b39b01ff AC |
922 | break; |
923 | } | |
924 | } | |
925 | ||
926 | static void __devinit hpt37x_clocking(ide_hwif_t *hwif) | |
927 | { | |
90778574 SS |
928 | struct hpt_info *info = ide_get_hwifdata(hwif); |
929 | struct pci_dev *dev = hwif->pci_dev; | |
930 | char *name = hwif->cds->name; | |
1da177e4 | 931 | int adjust, i; |
26c068da SS |
932 | u16 freq = 0; |
933 | u32 pll, temp = 0; | |
abc4ad4c | 934 | u8 scr2 = 0, mcr1 = 0; |
1da177e4 | 935 | |
1da177e4 LT |
936 | /* |
937 | * default to pci clock. make sure MA15/16 are set to output | |
b39b01ff AC |
938 | * to prevent drives having problems with 40-pin cables. Needed |
939 | * for some drives such as IBM-DTLA which will not enter ready | |
940 | * state on reset when PDIAG is a input. | |
941 | * | |
942 | * ToDo: should we set 0x21 when using PLL mode ? | |
1da177e4 LT |
943 | */ |
944 | pci_write_config_byte(dev, 0x5b, 0x23); | |
945 | ||
946 | /* | |
26c068da SS |
947 | * We'll have to read f_CNT value in order to determine |
948 | * the PCI clock frequency according to the following ratio: | |
1da177e4 | 949 | * |
26c068da SS |
950 | * f_CNT = Fpci * 192 / Fdpll |
951 | * | |
952 | * First try reading the register in which the HighPoint BIOS | |
953 | * saves f_CNT value before reprogramming the DPLL from its | |
954 | * default setting (which differs for the various chips). | |
f13c1526 SS |
955 | * NOTE: This register is only accessible via I/O space. |
956 | * | |
26c068da SS |
957 | * In case the signature check fails, we'll have to resort to |
958 | * reading the f_CNT register itself in hopes that nobody has | |
959 | * touched the DPLL yet... | |
1da177e4 | 960 | */ |
f13c1526 | 961 | temp = inl(pci_resource_start(dev, 4) + 0x90); |
26c068da | 962 | if ((temp & 0xFFFFF000) != 0xABCDE000) { |
90778574 | 963 | printk(KERN_WARNING "%s: no clock data saved by BIOS\n", name); |
26c068da SS |
964 | |
965 | /* Calculate the average value of f_CNT */ | |
966 | for (temp = i = 0; i < 128; i++) { | |
967 | pci_read_config_word(dev, 0x78, &freq); | |
968 | temp += freq & 0x1ff; | |
969 | mdelay(1); | |
970 | } | |
971 | freq = temp / 128; | |
972 | } else | |
973 | freq = temp & 0x1ff; | |
974 | ||
1da177e4 | 975 | /* |
836c0063 SS |
976 | * HPT3xxN chips use different PCI clock information. |
977 | * Currently we always set up the PLL for them. | |
1da177e4 | 978 | */ |
836c0063 SS |
979 | |
980 | if (info->flags & IS_3xxN) { | |
1da177e4 LT |
981 | if(freq < 0x55) |
982 | pll = F_LOW_PCI_33; | |
983 | else if(freq < 0x70) | |
984 | pll = F_LOW_PCI_40; | |
985 | else if(freq < 0x7F) | |
986 | pll = F_LOW_PCI_50; | |
987 | else | |
988 | pll = F_LOW_PCI_66; | |
836c0063 | 989 | |
90778574 | 990 | } else { |
1da177e4 LT |
991 | if(freq < 0x9C) |
992 | pll = F_LOW_PCI_33; | |
993 | else if(freq < 0xb0) | |
994 | pll = F_LOW_PCI_40; | |
995 | else if(freq <0xc8) | |
996 | pll = F_LOW_PCI_50; | |
997 | else | |
998 | pll = F_LOW_PCI_66; | |
90778574 SS |
999 | } |
1000 | printk(KERN_INFO "%s: FREQ: %d, PLL: %d\n", name, freq, pll); | |
1da177e4 | 1001 | |
90778574 | 1002 | if (!(info->flags & IS_3xxN)) { |
1da177e4 | 1003 | if (pll == F_LOW_PCI_33) { |
471a0bda | 1004 | info->speed = thirty_three_base_hpt37x; |
90778574 | 1005 | printk(KERN_DEBUG "%s: using 33MHz PCI clock\n", name); |
1da177e4 LT |
1006 | } else if (pll == F_LOW_PCI_40) { |
1007 | /* Unsupported */ | |
1008 | } else if (pll == F_LOW_PCI_50) { | |
471a0bda | 1009 | info->speed = fifty_base_hpt37x; |
90778574 | 1010 | printk(KERN_DEBUG "%s: using 50MHz PCI clock\n", name); |
1da177e4 | 1011 | } else { |
471a0bda | 1012 | info->speed = sixty_six_base_hpt37x; |
90778574 | 1013 | printk(KERN_DEBUG "%s: using 66MHz PCI clock\n", name); |
1da177e4 LT |
1014 | } |
1015 | } | |
836c0063 SS |
1016 | |
1017 | if (pll == F_LOW_PCI_66) | |
1018 | info->flags |= PCI_66MHZ; | |
1019 | ||
1da177e4 LT |
1020 | /* |
1021 | * only try the pll if we don't have a table for the clock | |
1022 | * speed that we're running at. NOTE: the internal PLL will | |
1023 | * result in slow reads when using a 33MHz PCI clock. we also | |
1024 | * don't like to use the PLL because it will cause glitches | |
1025 | * on PRST/SRST when the HPT state engine gets reset. | |
b39b01ff AC |
1026 | * |
1027 | * ToDo: Use 66MHz PLL when ATA133 devices are present on a | |
1028 | * 372 device so we can get ATA133 support | |
1da177e4 | 1029 | */ |
b39b01ff | 1030 | if (info->speed) |
1da177e4 | 1031 | goto init_hpt37X_done; |
b39b01ff AC |
1032 | |
1033 | info->flags |= PLL_MODE; | |
1da177e4 LT |
1034 | |
1035 | /* | |
26c068da SS |
1036 | * Adjust the PLL based upon the PCI clock, enable it, and |
1037 | * wait for stabilization... | |
1da177e4 LT |
1038 | */ |
1039 | adjust = 0; | |
1040 | freq = (pll < F_LOW_PCI_50) ? 2 : 4; | |
1041 | while (adjust++ < 6) { | |
1042 | pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 | | |
1043 | pll | 0x100); | |
1044 | ||
1045 | /* wait for clock stabilization */ | |
1046 | for (i = 0; i < 0x50000; i++) { | |
abc4ad4c SS |
1047 | pci_read_config_byte(dev, 0x5b, &scr2); |
1048 | if (scr2 & 0x80) { | |
1da177e4 LT |
1049 | /* spin looking for the clock to destabilize */ |
1050 | for (i = 0; i < 0x1000; ++i) { | |
1051 | pci_read_config_byte(dev, 0x5b, | |
abc4ad4c SS |
1052 | &scr2); |
1053 | if ((scr2 & 0x80) == 0) | |
1da177e4 LT |
1054 | goto pll_recal; |
1055 | } | |
1056 | pci_read_config_dword(dev, 0x5c, &pll); | |
1057 | pci_write_config_dword(dev, 0x5c, | |
1058 | pll & ~0x100); | |
1059 | pci_write_config_byte(dev, 0x5b, 0x21); | |
471a0bda SS |
1060 | |
1061 | info->speed = fifty_base_hpt37x; | |
90778574 | 1062 | printk("%s: using 50MHz internal PLL\n", name); |
1da177e4 LT |
1063 | goto init_hpt37X_done; |
1064 | } | |
1065 | } | |
1066 | pll_recal: | |
1067 | if (adjust & 1) | |
1068 | pll -= (adjust >> 1); | |
1069 | else | |
1070 | pll += (adjust >> 1); | |
1071 | } | |
1072 | ||
1073 | init_hpt37X_done: | |
b39b01ff | 1074 | if (!info->speed) |
90778574 SS |
1075 | printk(KERN_ERR "%s: unknown bus timing [%d %d].\n", |
1076 | name, pll, freq); | |
836c0063 SS |
1077 | /* |
1078 | * Reset the state engines. | |
1079 | * NOTE: avoid accidentally enabling the primary channel on HPT371N. | |
1080 | */ | |
1081 | pci_read_config_byte(dev, 0x50, &mcr1); | |
1082 | if (mcr1 & 0x04) | |
1083 | pci_write_config_byte(dev, 0x50, 0x37); | |
1084 | pci_write_config_byte(dev, 0x54, 0x37); | |
1da177e4 | 1085 | udelay(100); |
b39b01ff AC |
1086 | } |
1087 | ||
1da177e4 LT |
1088 | static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name) |
1089 | { | |
9ec4ff42 LT |
1090 | /* |
1091 | * FIXME: Not portable. Also, why do we enable the ROM in the first place? | |
1092 | * We don't seem to be using it. | |
1093 | */ | |
1da177e4 | 1094 | if (dev->resource[PCI_ROM_RESOURCE].start) |
9ec4ff42 | 1095 | pci_write_config_dword(dev, PCI_ROM_ADDRESS, |
1da177e4 LT |
1096 | dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); |
1097 | ||
b39b01ff AC |
1098 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); |
1099 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
1100 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
1101 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
1da177e4 | 1102 | |
26ccb802 SS |
1103 | if (hpt_revision(dev) >= 3) { |
1104 | u8 scr1 = 0; | |
b39b01ff | 1105 | |
26ccb802 SS |
1106 | /* Interrupt force enable. */ |
1107 | pci_read_config_byte(dev, 0x5a, &scr1); | |
1108 | if (scr1 & 0x10) | |
1109 | pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); | |
1110 | } | |
1da177e4 LT |
1111 | |
1112 | return dev->irq; | |
1113 | } | |
1114 | ||
1115 | static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) | |
1116 | { | |
26ccb802 | 1117 | struct pci_dev *dev = hwif->pci_dev; |
b39b01ff | 1118 | struct hpt_info *info = ide_get_hwifdata(hwif); |
836c0063 | 1119 | int serialize = HPT_SERIALIZE_IO; |
abc4ad4c | 1120 | u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02; |
26ccb802 | 1121 | u8 new_mcr, old_mcr = 0; |
abc4ad4c SS |
1122 | |
1123 | /* Cache the channel's MISC. control registers' offset */ | |
1124 | hwif->select_data = hwif->channel ? 0x54 : 0x50; | |
1125 | ||
1da177e4 LT |
1126 | hwif->tuneproc = &hpt3xx_tune_drive; |
1127 | hwif->speedproc = &hpt3xx_tune_chipset; | |
1128 | hwif->quirkproc = &hpt3xx_quirkproc; | |
1129 | hwif->intrproc = &hpt3xx_intrproc; | |
1130 | hwif->maskproc = &hpt3xx_maskproc; | |
abc4ad4c SS |
1131 | hwif->busproc = &hpt3xx_busproc; |
1132 | ||
836c0063 SS |
1133 | /* |
1134 | * HPT3xxN chips have some complications: | |
1135 | * | |
1136 | * - on 33 MHz PCI we must clock switch | |
1137 | * - on 66 MHz PCI we must NOT use the PCI clock | |
1138 | */ | |
1139 | if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) { | |
1140 | /* | |
1141 | * Clock is shared between the channels, | |
1142 | * so we'll have to serialize them... :-( | |
1143 | */ | |
1144 | serialize = 1; | |
1145 | hwif->rw_disk = &hpt3xxn_rw_disk; | |
1146 | } | |
1da177e4 | 1147 | |
26ccb802 SS |
1148 | /* Serialize access to this device if needed */ |
1149 | if (serialize && hwif->mate) | |
1150 | hwif->serialized = hwif->mate->serialized = 1; | |
1151 | ||
1152 | /* | |
1153 | * Disable the "fast interrupt" prediction. Don't hold off | |
1154 | * on interrupts. (== 0x01 despite what the docs say) | |
1155 | */ | |
1156 | pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr); | |
1157 | ||
1158 | if (info->revision >= 5) /* HPT372 and newer */ | |
1159 | new_mcr = old_mcr & ~0x07; | |
1160 | else if (info->revision >= 3) { /* HPT370 and HPT370A */ | |
1161 | new_mcr = old_mcr; | |
1162 | new_mcr &= ~0x02; | |
1163 | ||
1164 | #ifdef HPT_DELAY_INTERRUPT | |
1165 | new_mcr &= ~0x01; | |
1166 | #else | |
1167 | new_mcr |= 0x01; | |
1168 | #endif | |
1169 | } else /* HPT366 and HPT368 */ | |
1170 | new_mcr = old_mcr & ~0x80; | |
1171 | ||
1172 | if (new_mcr != old_mcr) | |
1173 | pci_write_config_byte(dev, hwif->select_data + 1, new_mcr); | |
1174 | ||
1175 | if (!hwif->dma_base) { | |
1176 | hwif->drives[0].autotune = hwif->drives[1].autotune = 1; | |
1177 | return; | |
1178 | } | |
1179 | ||
1180 | hwif->ultra_mask = 0x7f; | |
1181 | hwif->mwdma_mask = 0x07; | |
1182 | ||
1da177e4 LT |
1183 | /* |
1184 | * The HPT37x uses the CBLID pins as outputs for MA15/MA16 | |
abc4ad4c | 1185 | * address lines to access an external EEPROM. To read valid |
1da177e4 LT |
1186 | * cable detect state the pins must be enabled as inputs. |
1187 | */ | |
b39b01ff | 1188 | if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) { |
1da177e4 LT |
1189 | /* |
1190 | * HPT374 PCI function 1 | |
1191 | * - set bit 15 of reg 0x52 to enable TCBLID as input | |
1192 | * - set bit 15 of reg 0x56 to enable FCBLID as input | |
1193 | */ | |
abc4ad4c SS |
1194 | u8 mcr_addr = hwif->select_data + 2; |
1195 | u16 mcr; | |
1196 | ||
1197 | pci_read_config_word (dev, mcr_addr, &mcr); | |
1198 | pci_write_config_word(dev, mcr_addr, (mcr | 0x8000)); | |
1da177e4 | 1199 | /* now read cable id register */ |
abc4ad4c SS |
1200 | pci_read_config_byte (dev, 0x5a, &scr1); |
1201 | pci_write_config_word(dev, mcr_addr, mcr); | |
b39b01ff | 1202 | } else if (info->revision >= 3) { |
1da177e4 LT |
1203 | /* |
1204 | * HPT370/372 and 374 pcifn 0 | |
abc4ad4c | 1205 | * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs |
1da177e4 | 1206 | */ |
abc4ad4c | 1207 | u8 scr2 = 0; |
1da177e4 | 1208 | |
abc4ad4c SS |
1209 | pci_read_config_byte (dev, 0x5b, &scr2); |
1210 | pci_write_config_byte(dev, 0x5b, (scr2 & ~1)); | |
1211 | /* now read cable id register */ | |
1212 | pci_read_config_byte (dev, 0x5a, &scr1); | |
1213 | pci_write_config_byte(dev, 0x5b, scr2); | |
1214 | } else | |
1215 | pci_read_config_byte (dev, 0x5a, &scr1); | |
1da177e4 | 1216 | |
26ccb802 SS |
1217 | if (!hwif->udma_four) |
1218 | hwif->udma_four = (scr1 & ata66) ? 0 : 1; | |
1da177e4 | 1219 | |
26ccb802 | 1220 | hwif->ide_dma_check = &hpt366_config_drive_xfer_rate; |
1da177e4 | 1221 | |
26ccb802 SS |
1222 | if (info->revision >= 5) { |
1223 | hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq; | |
1224 | hwif->ide_dma_end = &hpt374_ide_dma_end; | |
b39b01ff | 1225 | } else if (info->revision >= 3) { |
26ccb802 SS |
1226 | hwif->dma_start = &hpt370_ide_dma_start; |
1227 | hwif->ide_dma_end = &hpt370_ide_dma_end; | |
1228 | hwif->ide_dma_timeout = &hpt370_ide_dma_timeout; | |
1229 | hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq; | |
1230 | } else | |
1231 | hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq; | |
1da177e4 LT |
1232 | |
1233 | if (!noautodma) | |
1234 | hwif->autodma = 1; | |
26ccb802 | 1235 | hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma; |
1da177e4 LT |
1236 | } |
1237 | ||
1238 | static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase) | |
1239 | { | |
26ccb802 | 1240 | struct pci_dev *dev = hwif->pci_dev; |
abc4ad4c SS |
1241 | struct hpt_info *info = ide_get_hwifdata(hwif); |
1242 | u8 masterdma = 0, slavedma = 0; | |
1243 | u8 dma_new = 0, dma_old = 0; | |
1da177e4 LT |
1244 | unsigned long flags; |
1245 | ||
1246 | if (!dmabase) | |
1247 | return; | |
1248 | ||
b39b01ff | 1249 | if(info->speed == NULL) { |
90778574 SS |
1250 | printk(KERN_WARNING "%s: no known IDE timings, disabling DMA.\n", |
1251 | hwif->cds->name); | |
1da177e4 LT |
1252 | return; |
1253 | } | |
1254 | ||
26ccb802 | 1255 | dma_old = hwif->INB(dmabase + 2); |
1da177e4 LT |
1256 | |
1257 | local_irq_save(flags); | |
1258 | ||
1259 | dma_new = dma_old; | |
abc4ad4c SS |
1260 | pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma); |
1261 | pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma); | |
1da177e4 LT |
1262 | |
1263 | if (masterdma & 0x30) dma_new |= 0x20; | |
abc4ad4c | 1264 | if ( slavedma & 0x30) dma_new |= 0x40; |
1da177e4 | 1265 | if (dma_new != dma_old) |
abc4ad4c | 1266 | hwif->OUTB(dma_new, dmabase + 2); |
1da177e4 LT |
1267 | |
1268 | local_irq_restore(flags); | |
1269 | ||
1270 | ide_setup_dma(hwif, dmabase, 8); | |
1271 | } | |
1272 | ||
b39b01ff AC |
1273 | /* |
1274 | * We "borrow" this hook in order to set the data structures | |
1275 | * up early enough before dma or init_hwif calls are made. | |
1276 | */ | |
1277 | ||
1278 | static void __devinit init_iops_hpt366(ide_hwif_t *hwif) | |
1279 | { | |
836c0063 SS |
1280 | struct hpt_info *info = kzalloc(sizeof(struct hpt_info), GFP_KERNEL); |
1281 | struct pci_dev *dev = hwif->pci_dev; | |
1282 | u16 did = dev->device; | |
e139b0b0 | 1283 | u8 mode, rid = 0; |
b39b01ff AC |
1284 | |
1285 | if(info == NULL) { | |
90778574 | 1286 | printk(KERN_WARNING "%s: out of memory.\n", hwif->cds->name); |
b39b01ff AC |
1287 | return; |
1288 | } | |
b39b01ff AC |
1289 | ide_set_hwifdata(hwif, info); |
1290 | ||
836c0063 SS |
1291 | /* Avoid doing the same thing twice. */ |
1292 | if (hwif->channel && hwif->mate) { | |
1293 | memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info)); | |
1294 | return; | |
b39b01ff AC |
1295 | } |
1296 | ||
e139b0b0 | 1297 | pci_read_config_byte(dev, PCI_REVISION_ID, &rid); |
836c0063 SS |
1298 | |
1299 | if (( did == PCI_DEVICE_ID_TTI_HPT366 && rid == 6) || | |
1300 | ((did == PCI_DEVICE_ID_TTI_HPT372 || | |
1301 | did == PCI_DEVICE_ID_TTI_HPT302 || | |
1302 | did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) || | |
1303 | did == PCI_DEVICE_ID_TTI_HPT372N) | |
1304 | info->flags |= IS_3xxN; | |
1305 | ||
e139b0b0 SS |
1306 | rid = info->revision = hpt_revision(dev); |
1307 | if (rid >= 8) /* HPT374 */ | |
1308 | mode = HPT374_ALLOW_ATA133_6 ? 4 : 3; | |
1309 | else if (rid >= 7) /* HPT371 and HPT371N */ | |
1310 | mode = HPT371_ALLOW_ATA133_6 ? 4 : 3; | |
1311 | else if (rid >= 6) /* HPT302 and HPT302N */ | |
1312 | mode = HPT302_ALLOW_ATA133_6 ? 4 : 3; | |
1313 | else if (rid >= 5) /* HPT372, HPT372A, and HPT372N */ | |
1314 | mode = HPT372_ALLOW_ATA133_6 ? 4 : 3; | |
1315 | else if (rid >= 3) /* HPT370 and HPT370A */ | |
1316 | mode = HPT370_ALLOW_ATA100_5 ? 3 : 2; | |
1317 | else /* HPT366 and HPT368 */ | |
1318 | mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1; | |
1319 | info->max_mode = mode; | |
1320 | ||
1321 | if (rid >= 3) | |
b39b01ff AC |
1322 | hpt37x_clocking(hwif); |
1323 | else | |
1324 | hpt366_clocking(hwif); | |
1325 | } | |
1326 | ||
1da177e4 LT |
1327 | static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d) |
1328 | { | |
b4586715 | 1329 | struct pci_dev *dev2; |
1da177e4 LT |
1330 | |
1331 | if (PCI_FUNC(dev->devfn) & 1) | |
1332 | return -ENODEV; | |
1333 | ||
b4586715 SS |
1334 | if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) { |
1335 | int ret; | |
1336 | ||
1337 | if (dev2->irq != dev->irq) { | |
1338 | /* FIXME: we need a core pci_set_interrupt() */ | |
1339 | dev2->irq = dev->irq; | |
1340 | printk(KERN_WARNING "%s: PCI config space interrupt " | |
1341 | "fixed.\n", d->name); | |
1da177e4 | 1342 | } |
b4586715 SS |
1343 | ret = ide_setup_pci_devices(dev, dev2, d); |
1344 | if (ret < 0) | |
1345 | pci_dev_put(dev2); | |
1346 | return ret; | |
1da177e4 LT |
1347 | } |
1348 | return ide_setup_pci_device(dev, d); | |
1349 | } | |
1350 | ||
90778574 | 1351 | static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d) |
1da177e4 LT |
1352 | { |
1353 | return ide_setup_pci_device(dev, d); | |
1354 | } | |
1355 | ||
836c0063 SS |
1356 | static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d) |
1357 | { | |
90778574 SS |
1358 | u8 rev = 0, mcr1 = 0; |
1359 | ||
1360 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); | |
1361 | ||
1362 | if (rev > 1) | |
1363 | d->name = "HPT371N"; | |
836c0063 SS |
1364 | |
1365 | /* | |
1366 | * HPT371 chips physically have only one channel, the secondary one, | |
1367 | * but the primary channel registers do exist! Go figure... | |
1368 | * So, we manually disable the non-existing channel here | |
1369 | * (if the BIOS hasn't done this already). | |
1370 | */ | |
1371 | pci_read_config_byte(dev, 0x50, &mcr1); | |
1372 | if (mcr1 & 0x04) | |
90778574 SS |
1373 | pci_write_config_byte(dev, 0x50, mcr1 & ~0x04); |
1374 | ||
1375 | return ide_setup_pci_device(dev, d); | |
1376 | } | |
1377 | ||
1378 | static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d) | |
1379 | { | |
1380 | u8 rev = 0; | |
1381 | ||
1382 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); | |
1383 | ||
1384 | if (rev > 1) | |
1385 | d->name = "HPT372N"; | |
1386 | ||
1387 | return ide_setup_pci_device(dev, d); | |
1388 | } | |
1389 | ||
1390 | static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d) | |
1391 | { | |
1392 | u8 rev = 0; | |
1393 | ||
1394 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); | |
1395 | ||
1396 | if (rev > 1) | |
1397 | d->name = "HPT302N"; | |
836c0063 SS |
1398 | |
1399 | return ide_setup_pci_device(dev, d); | |
1400 | } | |
1401 | ||
1da177e4 LT |
1402 | static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d) |
1403 | { | |
b4586715 SS |
1404 | struct pci_dev *dev2; |
1405 | u8 rev = 0; | |
90778574 SS |
1406 | static char *chipset_names[] = { "HPT366", "HPT366", "HPT368", |
1407 | "HPT370", "HPT370A", "HPT372", | |
1408 | "HPT372N" }; | |
1da177e4 LT |
1409 | |
1410 | if (PCI_FUNC(dev->devfn) & 1) | |
1411 | return -ENODEV; | |
1412 | ||
e139b0b0 | 1413 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); |
1da177e4 | 1414 | |
90778574 | 1415 | if (rev > 6) |
e139b0b0 | 1416 | rev = 6; |
1da177e4 | 1417 | |
90778574 | 1418 | d->name = chipset_names[rev]; |
1da177e4 | 1419 | |
90778574 SS |
1420 | if (rev > 2) |
1421 | goto init_single; | |
1da177e4 LT |
1422 | |
1423 | d->channels = 1; | |
1424 | ||
b4586715 SS |
1425 | if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) { |
1426 | u8 pin1 = 0, pin2 = 0; | |
1427 | int ret; | |
1428 | ||
1429 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); | |
1430 | pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2); | |
1431 | if (pin1 != pin2 && dev->irq == dev2->irq) { | |
1432 | d->bootable = ON_BOARD; | |
1433 | printk("%s: onboard version of chipset, pin1=%d pin2=%d\n", | |
1434 | d->name, pin1, pin2); | |
1da177e4 | 1435 | } |
b4586715 SS |
1436 | ret = ide_setup_pci_devices(dev, dev2, d); |
1437 | if (ret < 0) | |
1438 | pci_dev_put(dev2); | |
1439 | return ret; | |
1da177e4 LT |
1440 | } |
1441 | init_single: | |
1442 | return ide_setup_pci_device(dev, d); | |
1443 | } | |
1444 | ||
1445 | static ide_pci_device_t hpt366_chipsets[] __devinitdata = { | |
1446 | { /* 0 */ | |
1447 | .name = "HPT366", | |
1448 | .init_setup = init_setup_hpt366, | |
1449 | .init_chipset = init_chipset_hpt366, | |
b39b01ff | 1450 | .init_iops = init_iops_hpt366, |
1da177e4 LT |
1451 | .init_hwif = init_hwif_hpt366, |
1452 | .init_dma = init_dma_hpt366, | |
1453 | .channels = 2, | |
1454 | .autodma = AUTODMA, | |
1455 | .bootable = OFF_BOARD, | |
1456 | .extra = 240 | |
1457 | },{ /* 1 */ | |
1458 | .name = "HPT372A", | |
90778574 | 1459 | .init_setup = init_setup_hpt372a, |
1da177e4 | 1460 | .init_chipset = init_chipset_hpt366, |
b39b01ff | 1461 | .init_iops = init_iops_hpt366, |
1da177e4 LT |
1462 | .init_hwif = init_hwif_hpt366, |
1463 | .init_dma = init_dma_hpt366, | |
1464 | .channels = 2, | |
1465 | .autodma = AUTODMA, | |
1466 | .bootable = OFF_BOARD, | |
90778574 | 1467 | .extra = 240 |
1da177e4 LT |
1468 | },{ /* 2 */ |
1469 | .name = "HPT302", | |
90778574 | 1470 | .init_setup = init_setup_hpt302, |
1da177e4 | 1471 | .init_chipset = init_chipset_hpt366, |
b39b01ff | 1472 | .init_iops = init_iops_hpt366, |
1da177e4 LT |
1473 | .init_hwif = init_hwif_hpt366, |
1474 | .init_dma = init_dma_hpt366, | |
1475 | .channels = 2, | |
1476 | .autodma = AUTODMA, | |
1477 | .bootable = OFF_BOARD, | |
90778574 | 1478 | .extra = 240 |
1da177e4 LT |
1479 | },{ /* 3 */ |
1480 | .name = "HPT371", | |
836c0063 | 1481 | .init_setup = init_setup_hpt371, |
1da177e4 | 1482 | .init_chipset = init_chipset_hpt366, |
b39b01ff | 1483 | .init_iops = init_iops_hpt366, |
1da177e4 LT |
1484 | .init_hwif = init_hwif_hpt366, |
1485 | .init_dma = init_dma_hpt366, | |
1486 | .channels = 2, | |
1487 | .autodma = AUTODMA, | |
836c0063 | 1488 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
1da177e4 | 1489 | .bootable = OFF_BOARD, |
90778574 | 1490 | .extra = 240 |
1da177e4 LT |
1491 | },{ /* 4 */ |
1492 | .name = "HPT374", | |
1493 | .init_setup = init_setup_hpt374, | |
1494 | .init_chipset = init_chipset_hpt366, | |
b39b01ff | 1495 | .init_iops = init_iops_hpt366, |
1da177e4 LT |
1496 | .init_hwif = init_hwif_hpt366, |
1497 | .init_dma = init_dma_hpt366, | |
1498 | .channels = 2, /* 4 */ | |
1499 | .autodma = AUTODMA, | |
1500 | .bootable = OFF_BOARD, | |
90778574 | 1501 | .extra = 240 |
1da177e4 LT |
1502 | },{ /* 5 */ |
1503 | .name = "HPT372N", | |
90778574 | 1504 | .init_setup = init_setup_hpt372n, |
1da177e4 | 1505 | .init_chipset = init_chipset_hpt366, |
b39b01ff | 1506 | .init_iops = init_iops_hpt366, |
1da177e4 LT |
1507 | .init_hwif = init_hwif_hpt366, |
1508 | .init_dma = init_dma_hpt366, | |
1509 | .channels = 2, /* 4 */ | |
1510 | .autodma = AUTODMA, | |
1511 | .bootable = OFF_BOARD, | |
90778574 | 1512 | .extra = 240 |
1da177e4 LT |
1513 | } |
1514 | }; | |
1515 | ||
1516 | /** | |
1517 | * hpt366_init_one - called when an HPT366 is found | |
1518 | * @dev: the hpt366 device | |
1519 | * @id: the matching pci id | |
1520 | * | |
1521 | * Called when the PCI registration layer (or the IDE initialization) | |
1522 | * finds a device matching our IDE device tables. | |
73d1dd93 SS |
1523 | * |
1524 | * NOTE: since we'll have to modify some fields of the ide_pci_device_t | |
1525 | * structure depending on the chip's revision, we'd better pass a local | |
1526 | * copy down the call chain... | |
1da177e4 | 1527 | */ |
1da177e4 LT |
1528 | static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
1529 | { | |
73d1dd93 | 1530 | ide_pci_device_t d = hpt366_chipsets[id->driver_data]; |
1da177e4 | 1531 | |
73d1dd93 | 1532 | return d.init_setup(dev, &d); |
1da177e4 LT |
1533 | } |
1534 | ||
1535 | static struct pci_device_id hpt366_pci_tbl[] = { | |
1536 | { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1537 | { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, | |
1538 | { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
1539 | { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, | |
1540 | { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, | |
1541 | { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5}, | |
1542 | { 0, }, | |
1543 | }; | |
1544 | MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl); | |
1545 | ||
1546 | static struct pci_driver driver = { | |
1547 | .name = "HPT366_IDE", | |
1548 | .id_table = hpt366_pci_tbl, | |
1549 | .probe = hpt366_init_one, | |
1550 | }; | |
1551 | ||
82ab1eec | 1552 | static int __init hpt366_ide_init(void) |
1da177e4 LT |
1553 | { |
1554 | return ide_pci_register_driver(&driver); | |
1555 | } | |
1556 | ||
1557 | module_init(hpt366_ide_init); | |
1558 | ||
1559 | MODULE_AUTHOR("Andre Hedrick"); | |
1560 | MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE"); | |
1561 | MODULE_LICENSE("GPL"); |