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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> |
3 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
4 | * Portions Copyright (C) 2003 Red Hat Inc | |
fbf47840 | 5 | * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
38b66f84 | 6 | * Portions Copyright (C) 2005-2007 MontaVista Software, Inc. |
1da177e4 LT |
7 | * |
8 | * Thanks to HighPoint Technologies for their assistance, and hardware. | |
9 | * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his | |
10 | * donation of an ABit BP6 mainboard, processor, and memory acellerated | |
11 | * development and support. | |
12 | * | |
b39b01ff | 13 | * |
836c0063 SS |
14 | * HighPoint has its own drivers (open source except for the RAID part) |
15 | * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/. | |
16 | * This may be useful to anyone wanting to work on this driver, however do not | |
17 | * trust them too much since the code tends to become less and less meaningful | |
18 | * as the time passes... :-/ | |
b39b01ff | 19 | * |
1da177e4 LT |
20 | * Note that final HPT370 support was done by force extraction of GPL. |
21 | * | |
22 | * - add function for getting/setting power status of drive | |
23 | * - the HPT370's state machine can get confused. reset it before each dma | |
24 | * xfer to prevent that from happening. | |
25 | * - reset state engine whenever we get an error. | |
26 | * - check for busmaster state at end of dma. | |
27 | * - use new highpoint timings. | |
28 | * - detect bus speed using highpoint register. | |
29 | * - use pll if we don't have a clock table. added a 66MHz table that's | |
30 | * just 2x the 33MHz table. | |
31 | * - removed turnaround. NOTE: we never want to switch between pll and | |
32 | * pci clocks as the chip can glitch in those cases. the highpoint | |
33 | * approved workaround slows everything down too much to be useful. in | |
34 | * addition, we would have to serialize access to each chip. | |
35 | * Adrian Sun <a.sun@sun.com> | |
36 | * | |
37 | * add drive timings for 66MHz PCI bus, | |
38 | * fix ATA Cable signal detection, fix incorrect /proc info | |
39 | * add /proc display for per-drive PIO/DMA/UDMA mode and | |
40 | * per-channel ATA-33/66 Cable detect. | |
41 | * Duncan Laurie <void@sun.com> | |
42 | * | |
43 | * fixup /proc output for multiple controllers | |
44 | * Tim Hockin <thockin@sun.com> | |
45 | * | |
46 | * On hpt366: | |
47 | * Reset the hpt366 on error, reset on dma | |
48 | * Fix disabling Fast Interrupt hpt366. | |
49 | * Mike Waychison <crlf@sun.com> | |
50 | * | |
51 | * Added support for 372N clocking and clock switching. The 372N needs | |
52 | * different clocks on read/write. This requires overloading rw_disk and | |
53 | * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for | |
54 | * keeping me sane. | |
55 | * Alan Cox <alan@redhat.com> | |
56 | * | |
836c0063 SS |
57 | * - fix the clock turnaround code: it was writing to the wrong ports when |
58 | * called for the secondary channel, caching the current clock mode per- | |
59 | * channel caused the cached register value to get out of sync with the | |
60 | * actual one, the channels weren't serialized, the turnaround shouldn't | |
61 | * be done on 66 MHz PCI bus | |
7b73ee05 SS |
62 | * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used |
63 | * does not allow for this speed anyway | |
64 | * - avoid touching disabled channels (e.g. HPT371/N are single channel chips, | |
65 | * their primary channel is kind of virtual, it isn't tied to any pins) | |
471a0bda SS |
66 | * - fix/remove bad/unused timing tables and use one set of tables for the whole |
67 | * HPT37x chip family; save space by introducing the separate transfer mode | |
68 | * table in which the mode lookup is done | |
26c068da | 69 | * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives |
72931368 SS |
70 | * the wrong PCI frequency since DPLL has already been calibrated by BIOS; |
71 | * read it only from the function 0 of HPT374 chips | |
33b18a60 SS |
72 | * - fix the hotswap code: it caused RESET- to glitch when tristating the bus, |
73 | * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead | |
73d1dd93 SS |
74 | * - pass to init_chipset() handlers a copy of the IDE PCI device structure as |
75 | * they tamper with its fields | |
7b73ee05 SS |
76 | * - pass to the init_setup handlers a copy of the ide_pci_device_t structure |
77 | * since they may tamper with its fields | |
90778574 SS |
78 | * - prefix the driver startup messages with the real chip name |
79 | * - claim the extra 240 bytes of I/O space for all chips | |
2648e5d9 | 80 | * - optimize the UltraDMA filtering and the drive list lookup code |
b4586715 | 81 | * - use pci_get_slot() to get to the function 1 of HPT36x/374 |
7b73ee05 SS |
82 | * - cache offset of the channel's misc. control registers (MCRs) being used |
83 | * throughout the driver | |
84 | * - only touch the relevant MCR when detecting the cable type on HPT374's | |
85 | * function 1 | |
abc4ad4c | 86 | * - rename all the register related variables consistently |
7b73ee05 SS |
87 | * - move all the interrupt twiddling code from the speedproc handlers into |
88 | * init_hwif_hpt366(), also grouping all the DMA related code together there | |
866664d7 | 89 | * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and |
7b73ee05 SS |
90 | * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings |
91 | * when setting an UltraDMA mode | |
92 | * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select | |
93 | * the best possible one | |
4bf63de2 | 94 | * - clean up DMA timeout handling for HPT370 |
7b73ee05 SS |
95 | * - switch to using the enumeration type to differ between the numerous chip |
96 | * variants, matching PCI device/revision ID with the chip type early, at the | |
97 | * init_setup stage | |
98 | * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies, | |
99 | * stop duplicating it for each channel by storing the pointer in the pci_dev | |
100 | * structure: first, at the init_setup stage, point it to a static "template" | |
101 | * with only the chip type and its specific base DPLL frequency, the highest | |
2648e5d9 SS |
102 | * UltraDMA mode, and the chip settings table pointer filled, then, at the |
103 | * init_chipset stage, allocate per-chip instance and fill it with the rest | |
104 | * of the necessary information | |
7b73ee05 SS |
105 | * - get rid of the constant thresholds in the HPT37x PCI clock detection code, |
106 | * switch to calculating PCI clock frequency based on the chip's base DPLL | |
107 | * frequency | |
108 | * - switch to using the DPLL clock and enable UltraATA/133 mode by default on | |
278978e9 SS |
109 | * anything newer than HPT370/A (except HPT374 that is not capable of this |
110 | * mode according to the manual) | |
6273d26a SS |
111 | * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(), |
112 | * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips; | |
7b73ee05 SS |
113 | * unify HPT36x/37x timing setup code and the speedproc handlers by joining |
114 | * the register setting lists into the table indexed by the clock selected | |
2648e5d9 | 115 | * - set the correct hwif->ultra_mask for each individual chip |
b4e44369 | 116 | * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards |
7b73ee05 | 117 | * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com> |
1da177e4 LT |
118 | */ |
119 | ||
1da177e4 LT |
120 | #include <linux/types.h> |
121 | #include <linux/module.h> | |
122 | #include <linux/kernel.h> | |
123 | #include <linux/delay.h> | |
1da177e4 LT |
124 | #include <linux/blkdev.h> |
125 | #include <linux/hdreg.h> | |
1da177e4 LT |
126 | #include <linux/interrupt.h> |
127 | #include <linux/pci.h> | |
128 | #include <linux/init.h> | |
129 | #include <linux/ide.h> | |
130 | ||
131 | #include <asm/uaccess.h> | |
132 | #include <asm/io.h> | |
1da177e4 LT |
133 | |
134 | /* various tuning parameters */ | |
135 | #define HPT_RESET_STATE_ENGINE | |
836c0063 SS |
136 | #undef HPT_DELAY_INTERRUPT |
137 | #define HPT_SERIALIZE_IO 0 | |
1da177e4 LT |
138 | |
139 | static const char *quirk_drives[] = { | |
140 | "QUANTUM FIREBALLlct08 08", | |
141 | "QUANTUM FIREBALLP KA6.4", | |
142 | "QUANTUM FIREBALLP LM20.4", | |
143 | "QUANTUM FIREBALLP LM20.5", | |
144 | NULL | |
145 | }; | |
146 | ||
147 | static const char *bad_ata100_5[] = { | |
148 | "IBM-DTLA-307075", | |
149 | "IBM-DTLA-307060", | |
150 | "IBM-DTLA-307045", | |
151 | "IBM-DTLA-307030", | |
152 | "IBM-DTLA-307020", | |
153 | "IBM-DTLA-307015", | |
154 | "IBM-DTLA-305040", | |
155 | "IBM-DTLA-305030", | |
156 | "IBM-DTLA-305020", | |
157 | "IC35L010AVER07-0", | |
158 | "IC35L020AVER07-0", | |
159 | "IC35L030AVER07-0", | |
160 | "IC35L040AVER07-0", | |
161 | "IC35L060AVER07-0", | |
162 | "WDC AC310200R", | |
163 | NULL | |
164 | }; | |
165 | ||
166 | static const char *bad_ata66_4[] = { | |
167 | "IBM-DTLA-307075", | |
168 | "IBM-DTLA-307060", | |
169 | "IBM-DTLA-307045", | |
170 | "IBM-DTLA-307030", | |
171 | "IBM-DTLA-307020", | |
172 | "IBM-DTLA-307015", | |
173 | "IBM-DTLA-305040", | |
174 | "IBM-DTLA-305030", | |
175 | "IBM-DTLA-305020", | |
176 | "IC35L010AVER07-0", | |
177 | "IC35L020AVER07-0", | |
178 | "IC35L030AVER07-0", | |
179 | "IC35L040AVER07-0", | |
180 | "IC35L060AVER07-0", | |
181 | "WDC AC310200R", | |
783353b1 | 182 | "MAXTOR STM3320620A", |
1da177e4 LT |
183 | NULL |
184 | }; | |
185 | ||
186 | static const char *bad_ata66_3[] = { | |
187 | "WDC AC310200R", | |
188 | NULL | |
189 | }; | |
190 | ||
191 | static const char *bad_ata33[] = { | |
192 | "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", | |
193 | "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", | |
194 | "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", | |
195 | "Maxtor 90510D4", | |
196 | "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", | |
197 | "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", | |
198 | "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", | |
199 | NULL | |
200 | }; | |
201 | ||
471a0bda SS |
202 | static u8 xfer_speeds[] = { |
203 | XFER_UDMA_6, | |
204 | XFER_UDMA_5, | |
205 | XFER_UDMA_4, | |
206 | XFER_UDMA_3, | |
207 | XFER_UDMA_2, | |
208 | XFER_UDMA_1, | |
209 | XFER_UDMA_0, | |
210 | ||
211 | XFER_MW_DMA_2, | |
212 | XFER_MW_DMA_1, | |
213 | XFER_MW_DMA_0, | |
214 | ||
215 | XFER_PIO_4, | |
216 | XFER_PIO_3, | |
217 | XFER_PIO_2, | |
218 | XFER_PIO_1, | |
219 | XFER_PIO_0 | |
1da177e4 LT |
220 | }; |
221 | ||
471a0bda SS |
222 | /* Key for bus clock timings |
223 | * 36x 37x | |
224 | * bits bits | |
225 | * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. | |
226 | * cycles = value + 1 | |
227 | * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. | |
228 | * cycles = value + 1 | |
229 | * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file | |
230 | * register access. | |
231 | * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file | |
232 | * register access. | |
233 | * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer. | |
234 | * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock. | |
235 | * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and | |
236 | * MW DMA xfer. | |
237 | * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for | |
238 | * task file register access. | |
239 | * 28 28 UDMA enable. | |
240 | * 29 29 DMA enable. | |
241 | * 30 30 PIO MST enable. If set, the chip is in bus master mode during | |
242 | * PIO xfer. | |
243 | * 31 31 FIFO enable. | |
1da177e4 | 244 | */ |
1da177e4 | 245 | |
471a0bda SS |
246 | static u32 forty_base_hpt36x[] = { |
247 | /* XFER_UDMA_6 */ 0x900fd943, | |
248 | /* XFER_UDMA_5 */ 0x900fd943, | |
249 | /* XFER_UDMA_4 */ 0x900fd943, | |
250 | /* XFER_UDMA_3 */ 0x900ad943, | |
251 | /* XFER_UDMA_2 */ 0x900bd943, | |
252 | /* XFER_UDMA_1 */ 0x9008d943, | |
253 | /* XFER_UDMA_0 */ 0x9008d943, | |
254 | ||
255 | /* XFER_MW_DMA_2 */ 0xa008d943, | |
256 | /* XFER_MW_DMA_1 */ 0xa010d955, | |
257 | /* XFER_MW_DMA_0 */ 0xa010d9fc, | |
258 | ||
259 | /* XFER_PIO_4 */ 0xc008d963, | |
260 | /* XFER_PIO_3 */ 0xc010d974, | |
261 | /* XFER_PIO_2 */ 0xc010d997, | |
262 | /* XFER_PIO_1 */ 0xc010d9c7, | |
263 | /* XFER_PIO_0 */ 0xc018d9d9 | |
1da177e4 LT |
264 | }; |
265 | ||
471a0bda SS |
266 | static u32 thirty_three_base_hpt36x[] = { |
267 | /* XFER_UDMA_6 */ 0x90c9a731, | |
268 | /* XFER_UDMA_5 */ 0x90c9a731, | |
269 | /* XFER_UDMA_4 */ 0x90c9a731, | |
270 | /* XFER_UDMA_3 */ 0x90cfa731, | |
271 | /* XFER_UDMA_2 */ 0x90caa731, | |
272 | /* XFER_UDMA_1 */ 0x90cba731, | |
273 | /* XFER_UDMA_0 */ 0x90c8a731, | |
274 | ||
275 | /* XFER_MW_DMA_2 */ 0xa0c8a731, | |
276 | /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */ | |
277 | /* XFER_MW_DMA_0 */ 0xa0c8a797, | |
278 | ||
279 | /* XFER_PIO_4 */ 0xc0c8a731, | |
280 | /* XFER_PIO_3 */ 0xc0c8a742, | |
281 | /* XFER_PIO_2 */ 0xc0d0a753, | |
282 | /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */ | |
283 | /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */ | |
1da177e4 LT |
284 | }; |
285 | ||
471a0bda SS |
286 | static u32 twenty_five_base_hpt36x[] = { |
287 | /* XFER_UDMA_6 */ 0x90c98521, | |
288 | /* XFER_UDMA_5 */ 0x90c98521, | |
289 | /* XFER_UDMA_4 */ 0x90c98521, | |
290 | /* XFER_UDMA_3 */ 0x90cf8521, | |
291 | /* XFER_UDMA_2 */ 0x90cf8521, | |
292 | /* XFER_UDMA_1 */ 0x90cb8521, | |
293 | /* XFER_UDMA_0 */ 0x90cb8521, | |
294 | ||
295 | /* XFER_MW_DMA_2 */ 0xa0ca8521, | |
296 | /* XFER_MW_DMA_1 */ 0xa0ca8532, | |
297 | /* XFER_MW_DMA_0 */ 0xa0ca8575, | |
298 | ||
299 | /* XFER_PIO_4 */ 0xc0ca8521, | |
300 | /* XFER_PIO_3 */ 0xc0ca8532, | |
301 | /* XFER_PIO_2 */ 0xc0ca8542, | |
302 | /* XFER_PIO_1 */ 0xc0d08572, | |
303 | /* XFER_PIO_0 */ 0xc0d08585 | |
1da177e4 LT |
304 | }; |
305 | ||
809b53c4 SS |
306 | #if 0 |
307 | /* These are the timing tables from the HighPoint open source drivers... */ | |
471a0bda SS |
308 | static u32 thirty_three_base_hpt37x[] = { |
309 | /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */ | |
310 | /* XFER_UDMA_5 */ 0x12446231, | |
311 | /* XFER_UDMA_4 */ 0x12446231, | |
312 | /* XFER_UDMA_3 */ 0x126c6231, | |
313 | /* XFER_UDMA_2 */ 0x12486231, | |
314 | /* XFER_UDMA_1 */ 0x124c6233, | |
315 | /* XFER_UDMA_0 */ 0x12506297, | |
316 | ||
317 | /* XFER_MW_DMA_2 */ 0x22406c31, | |
318 | /* XFER_MW_DMA_1 */ 0x22406c33, | |
319 | /* XFER_MW_DMA_0 */ 0x22406c97, | |
320 | ||
321 | /* XFER_PIO_4 */ 0x06414e31, | |
322 | /* XFER_PIO_3 */ 0x06414e42, | |
323 | /* XFER_PIO_2 */ 0x06414e53, | |
324 | /* XFER_PIO_1 */ 0x06814e93, | |
325 | /* XFER_PIO_0 */ 0x06814ea7 | |
1da177e4 LT |
326 | }; |
327 | ||
471a0bda SS |
328 | static u32 fifty_base_hpt37x[] = { |
329 | /* XFER_UDMA_6 */ 0x12848242, | |
330 | /* XFER_UDMA_5 */ 0x12848242, | |
331 | /* XFER_UDMA_4 */ 0x12ac8242, | |
332 | /* XFER_UDMA_3 */ 0x128c8242, | |
333 | /* XFER_UDMA_2 */ 0x120c8242, | |
334 | /* XFER_UDMA_1 */ 0x12148254, | |
335 | /* XFER_UDMA_0 */ 0x121882ea, | |
336 | ||
337 | /* XFER_MW_DMA_2 */ 0x22808242, | |
338 | /* XFER_MW_DMA_1 */ 0x22808254, | |
339 | /* XFER_MW_DMA_0 */ 0x228082ea, | |
340 | ||
341 | /* XFER_PIO_4 */ 0x0a81f442, | |
342 | /* XFER_PIO_3 */ 0x0a81f443, | |
343 | /* XFER_PIO_2 */ 0x0a81f454, | |
344 | /* XFER_PIO_1 */ 0x0ac1f465, | |
345 | /* XFER_PIO_0 */ 0x0ac1f48a | |
1da177e4 LT |
346 | }; |
347 | ||
471a0bda SS |
348 | static u32 sixty_six_base_hpt37x[] = { |
349 | /* XFER_UDMA_6 */ 0x1c869c62, | |
350 | /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */ | |
351 | /* XFER_UDMA_4 */ 0x1c8a9c62, | |
352 | /* XFER_UDMA_3 */ 0x1c8e9c62, | |
353 | /* XFER_UDMA_2 */ 0x1c929c62, | |
354 | /* XFER_UDMA_1 */ 0x1c9a9c62, | |
355 | /* XFER_UDMA_0 */ 0x1c829c62, | |
356 | ||
357 | /* XFER_MW_DMA_2 */ 0x2c829c62, | |
358 | /* XFER_MW_DMA_1 */ 0x2c829c66, | |
359 | /* XFER_MW_DMA_0 */ 0x2c829d2e, | |
360 | ||
361 | /* XFER_PIO_4 */ 0x0c829c62, | |
362 | /* XFER_PIO_3 */ 0x0c829c84, | |
363 | /* XFER_PIO_2 */ 0x0c829ca6, | |
364 | /* XFER_PIO_1 */ 0x0d029d26, | |
365 | /* XFER_PIO_0 */ 0x0d029d5e | |
1da177e4 | 366 | }; |
809b53c4 SS |
367 | #else |
368 | /* | |
369 | * The following are the new timing tables with PIO mode data/taskfile transfer | |
370 | * overclocking fixed... | |
371 | */ | |
372 | ||
373 | /* This table is taken from the HPT370 data manual rev. 1.02 */ | |
374 | static u32 thirty_three_base_hpt37x[] = { | |
375 | /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */ | |
376 | /* XFER_UDMA_5 */ 0x16455031, | |
377 | /* XFER_UDMA_4 */ 0x16455031, | |
378 | /* XFER_UDMA_3 */ 0x166d5031, | |
379 | /* XFER_UDMA_2 */ 0x16495031, | |
380 | /* XFER_UDMA_1 */ 0x164d5033, | |
381 | /* XFER_UDMA_0 */ 0x16515097, | |
382 | ||
383 | /* XFER_MW_DMA_2 */ 0x26515031, | |
384 | /* XFER_MW_DMA_1 */ 0x26515033, | |
385 | /* XFER_MW_DMA_0 */ 0x26515097, | |
386 | ||
387 | /* XFER_PIO_4 */ 0x06515021, | |
388 | /* XFER_PIO_3 */ 0x06515022, | |
389 | /* XFER_PIO_2 */ 0x06515033, | |
390 | /* XFER_PIO_1 */ 0x06915065, | |
391 | /* XFER_PIO_0 */ 0x06d1508a | |
392 | }; | |
393 | ||
394 | static u32 fifty_base_hpt37x[] = { | |
395 | /* XFER_UDMA_6 */ 0x1a861842, | |
396 | /* XFER_UDMA_5 */ 0x1a861842, | |
397 | /* XFER_UDMA_4 */ 0x1aae1842, | |
398 | /* XFER_UDMA_3 */ 0x1a8e1842, | |
399 | /* XFER_UDMA_2 */ 0x1a0e1842, | |
400 | /* XFER_UDMA_1 */ 0x1a161854, | |
401 | /* XFER_UDMA_0 */ 0x1a1a18ea, | |
402 | ||
403 | /* XFER_MW_DMA_2 */ 0x2a821842, | |
404 | /* XFER_MW_DMA_1 */ 0x2a821854, | |
405 | /* XFER_MW_DMA_0 */ 0x2a8218ea, | |
406 | ||
407 | /* XFER_PIO_4 */ 0x0a821842, | |
408 | /* XFER_PIO_3 */ 0x0a821843, | |
409 | /* XFER_PIO_2 */ 0x0a821855, | |
410 | /* XFER_PIO_1 */ 0x0ac218a8, | |
411 | /* XFER_PIO_0 */ 0x0b02190c | |
412 | }; | |
413 | ||
414 | static u32 sixty_six_base_hpt37x[] = { | |
415 | /* XFER_UDMA_6 */ 0x1c86fe62, | |
416 | /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */ | |
417 | /* XFER_UDMA_4 */ 0x1c8afe62, | |
418 | /* XFER_UDMA_3 */ 0x1c8efe62, | |
419 | /* XFER_UDMA_2 */ 0x1c92fe62, | |
420 | /* XFER_UDMA_1 */ 0x1c9afe62, | |
421 | /* XFER_UDMA_0 */ 0x1c82fe62, | |
422 | ||
423 | /* XFER_MW_DMA_2 */ 0x2c82fe62, | |
424 | /* XFER_MW_DMA_1 */ 0x2c82fe66, | |
425 | /* XFER_MW_DMA_0 */ 0x2c82ff2e, | |
426 | ||
427 | /* XFER_PIO_4 */ 0x0c82fe62, | |
428 | /* XFER_PIO_3 */ 0x0c82fe84, | |
429 | /* XFER_PIO_2 */ 0x0c82fea6, | |
430 | /* XFER_PIO_1 */ 0x0d02ff26, | |
431 | /* XFER_PIO_0 */ 0x0d42ff7f | |
432 | }; | |
433 | #endif | |
1da177e4 | 434 | |
1da177e4 | 435 | #define HPT366_DEBUG_DRIVE_INFO 0 |
7b73ee05 SS |
436 | #define HPT371_ALLOW_ATA133_6 1 |
437 | #define HPT302_ALLOW_ATA133_6 1 | |
438 | #define HPT372_ALLOW_ATA133_6 1 | |
e139b0b0 | 439 | #define HPT370_ALLOW_ATA100_5 0 |
1da177e4 LT |
440 | #define HPT366_ALLOW_ATA66_4 1 |
441 | #define HPT366_ALLOW_ATA66_3 1 | |
442 | #define HPT366_MAX_DEVS 8 | |
443 | ||
7b73ee05 SS |
444 | /* Supported ATA clock frequencies */ |
445 | enum ata_clock { | |
446 | ATA_CLOCK_25MHZ, | |
447 | ATA_CLOCK_33MHZ, | |
448 | ATA_CLOCK_40MHZ, | |
449 | ATA_CLOCK_50MHZ, | |
450 | ATA_CLOCK_66MHZ, | |
451 | NUM_ATA_CLOCKS | |
452 | }; | |
1da177e4 | 453 | |
866664d7 SS |
454 | struct hpt_timings { |
455 | u32 pio_mask; | |
456 | u32 dma_mask; | |
457 | u32 ultra_mask; | |
458 | u32 *clock_table[NUM_ATA_CLOCKS]; | |
459 | }; | |
460 | ||
b39b01ff | 461 | /* |
7b73ee05 | 462 | * Hold all the HighPoint chip information in one place. |
b39b01ff | 463 | */ |
1da177e4 | 464 | |
7b73ee05 | 465 | struct hpt_info { |
fbf47840 | 466 | char *chip_name; /* Chip name */ |
7b73ee05 | 467 | u8 chip_type; /* Chip type */ |
fbf47840 | 468 | u8 udma_mask; /* Allowed UltraDMA modes mask. */ |
7b73ee05 SS |
469 | u8 dpll_clk; /* DPLL clock in MHz */ |
470 | u8 pci_clk; /* PCI clock in MHz */ | |
866664d7 SS |
471 | struct hpt_timings *timings; /* Chipset timing data */ |
472 | u8 clock; /* ATA clock selected */ | |
b39b01ff AC |
473 | }; |
474 | ||
7b73ee05 SS |
475 | /* Supported HighPoint chips */ |
476 | enum { | |
477 | HPT36x, | |
478 | HPT370, | |
479 | HPT370A, | |
480 | HPT374, | |
481 | HPT372, | |
482 | HPT372A, | |
483 | HPT302, | |
484 | HPT371, | |
485 | HPT372N, | |
486 | HPT302N, | |
487 | HPT371N | |
488 | }; | |
b39b01ff | 489 | |
866664d7 SS |
490 | static struct hpt_timings hpt36x_timings = { |
491 | .pio_mask = 0xc1f8ffff, | |
492 | .dma_mask = 0x303800ff, | |
493 | .ultra_mask = 0x30070000, | |
494 | .clock_table = { | |
495 | [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x, | |
496 | [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x, | |
497 | [ATA_CLOCK_40MHZ] = forty_base_hpt36x, | |
498 | [ATA_CLOCK_50MHZ] = NULL, | |
499 | [ATA_CLOCK_66MHZ] = NULL | |
500 | } | |
7b73ee05 | 501 | }; |
e139b0b0 | 502 | |
866664d7 SS |
503 | static struct hpt_timings hpt37x_timings = { |
504 | .pio_mask = 0xcfc3ffff, | |
505 | .dma_mask = 0x31c001ff, | |
506 | .ultra_mask = 0x303c0000, | |
507 | .clock_table = { | |
508 | [ATA_CLOCK_25MHZ] = NULL, | |
509 | [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x, | |
510 | [ATA_CLOCK_40MHZ] = NULL, | |
511 | [ATA_CLOCK_50MHZ] = fifty_base_hpt37x, | |
512 | [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x | |
513 | } | |
7b73ee05 | 514 | }; |
1da177e4 | 515 | |
282037f1 | 516 | static const struct hpt_info hpt36x __devinitdata = { |
fbf47840 | 517 | .chip_name = "HPT36x", |
7b73ee05 | 518 | .chip_type = HPT36x, |
fbf47840 | 519 | .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2, |
7b73ee05 | 520 | .dpll_clk = 0, /* no DPLL */ |
866664d7 | 521 | .timings = &hpt36x_timings |
7b73ee05 SS |
522 | }; |
523 | ||
282037f1 | 524 | static const struct hpt_info hpt370 __devinitdata = { |
fbf47840 | 525 | .chip_name = "HPT370", |
7b73ee05 | 526 | .chip_type = HPT370, |
fbf47840 | 527 | .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, |
7b73ee05 | 528 | .dpll_clk = 48, |
866664d7 | 529 | .timings = &hpt37x_timings |
7b73ee05 SS |
530 | }; |
531 | ||
282037f1 | 532 | static const struct hpt_info hpt370a __devinitdata = { |
fbf47840 | 533 | .chip_name = "HPT370A", |
7b73ee05 | 534 | .chip_type = HPT370A, |
fbf47840 | 535 | .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, |
7b73ee05 | 536 | .dpll_clk = 48, |
866664d7 | 537 | .timings = &hpt37x_timings |
7b73ee05 SS |
538 | }; |
539 | ||
282037f1 | 540 | static const struct hpt_info hpt374 __devinitdata = { |
fbf47840 | 541 | .chip_name = "HPT374", |
7b73ee05 | 542 | .chip_type = HPT374, |
fbf47840 | 543 | .udma_mask = ATA_UDMA5, |
7b73ee05 | 544 | .dpll_clk = 48, |
866664d7 | 545 | .timings = &hpt37x_timings |
7b73ee05 SS |
546 | }; |
547 | ||
282037f1 | 548 | static const struct hpt_info hpt372 __devinitdata = { |
fbf47840 | 549 | .chip_name = "HPT372", |
7b73ee05 | 550 | .chip_type = HPT372, |
fbf47840 | 551 | .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 552 | .dpll_clk = 55, |
866664d7 | 553 | .timings = &hpt37x_timings |
7b73ee05 SS |
554 | }; |
555 | ||
282037f1 | 556 | static const struct hpt_info hpt372a __devinitdata = { |
fbf47840 | 557 | .chip_name = "HPT372A", |
7b73ee05 | 558 | .chip_type = HPT372A, |
fbf47840 | 559 | .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 560 | .dpll_clk = 66, |
866664d7 | 561 | .timings = &hpt37x_timings |
7b73ee05 SS |
562 | }; |
563 | ||
282037f1 | 564 | static const struct hpt_info hpt302 __devinitdata = { |
fbf47840 | 565 | .chip_name = "HPT302", |
7b73ee05 | 566 | .chip_type = HPT302, |
fbf47840 | 567 | .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 568 | .dpll_clk = 66, |
866664d7 | 569 | .timings = &hpt37x_timings |
7b73ee05 SS |
570 | }; |
571 | ||
282037f1 | 572 | static const struct hpt_info hpt371 __devinitdata = { |
fbf47840 | 573 | .chip_name = "HPT371", |
7b73ee05 | 574 | .chip_type = HPT371, |
fbf47840 | 575 | .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 576 | .dpll_clk = 66, |
866664d7 | 577 | .timings = &hpt37x_timings |
7b73ee05 SS |
578 | }; |
579 | ||
282037f1 | 580 | static const struct hpt_info hpt372n __devinitdata = { |
fbf47840 | 581 | .chip_name = "HPT372N", |
7b73ee05 | 582 | .chip_type = HPT372N, |
fbf47840 | 583 | .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 584 | .dpll_clk = 77, |
866664d7 | 585 | .timings = &hpt37x_timings |
7b73ee05 SS |
586 | }; |
587 | ||
282037f1 | 588 | static const struct hpt_info hpt302n __devinitdata = { |
fbf47840 | 589 | .chip_name = "HPT302N", |
7b73ee05 | 590 | .chip_type = HPT302N, |
fbf47840 | 591 | .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 592 | .dpll_clk = 77, |
866664d7 | 593 | .timings = &hpt37x_timings |
7b73ee05 SS |
594 | }; |
595 | ||
282037f1 | 596 | static const struct hpt_info hpt371n __devinitdata = { |
fbf47840 | 597 | .chip_name = "HPT371N", |
7b73ee05 | 598 | .chip_type = HPT371N, |
fbf47840 | 599 | .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 600 | .dpll_clk = 77, |
866664d7 | 601 | .timings = &hpt37x_timings |
7b73ee05 | 602 | }; |
1da177e4 | 603 | |
e139b0b0 SS |
604 | static int check_in_drive_list(ide_drive_t *drive, const char **list) |
605 | { | |
606 | struct hd_driveid *id = drive->id; | |
607 | ||
608 | while (*list) | |
609 | if (!strcmp(*list++,id->model)) | |
610 | return 1; | |
611 | return 0; | |
612 | } | |
1da177e4 | 613 | |
1da177e4 | 614 | /* |
2808b0a9 SS |
615 | * The Marvell bridge chips used on the HighPoint SATA cards do not seem |
616 | * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... | |
1da177e4 | 617 | */ |
2d5eaa6d BZ |
618 | |
619 | static u8 hpt3xx_udma_filter(ide_drive_t *drive) | |
1da177e4 | 620 | { |
2808b0a9 | 621 | ide_hwif_t *hwif = HWIF(drive); |
36501650 BZ |
622 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
623 | struct hpt_info *info = pci_get_drvdata(dev); | |
2808b0a9 | 624 | u8 mask = hwif->ultra_mask; |
1da177e4 | 625 | |
2648e5d9 | 626 | switch (info->chip_type) { |
2648e5d9 SS |
627 | case HPT36x: |
628 | if (!HPT366_ALLOW_ATA66_4 || | |
629 | check_in_drive_list(drive, bad_ata66_4)) | |
2808b0a9 | 630 | mask = ATA_UDMA3; |
7b73ee05 | 631 | |
2648e5d9 SS |
632 | if (!HPT366_ALLOW_ATA66_3 || |
633 | check_in_drive_list(drive, bad_ata66_3)) | |
2808b0a9 | 634 | mask = ATA_UDMA2; |
2648e5d9 | 635 | break; |
2808b0a9 SS |
636 | case HPT370: |
637 | if (!HPT370_ALLOW_ATA100_5 || | |
638 | check_in_drive_list(drive, bad_ata100_5)) | |
639 | mask = ATA_UDMA4; | |
640 | break; | |
641 | case HPT370A: | |
642 | if (!HPT370_ALLOW_ATA100_5 || | |
643 | check_in_drive_list(drive, bad_ata100_5)) | |
644 | return ATA_UDMA4; | |
645 | case HPT372 : | |
646 | case HPT372A: | |
647 | case HPT372N: | |
648 | case HPT374 : | |
649 | if (ide_dev_is_sata(drive->id)) | |
650 | mask &= ~0x0e; | |
651 | /* Fall thru */ | |
2648e5d9 | 652 | default: |
2808b0a9 | 653 | return mask; |
1da177e4 | 654 | } |
2648e5d9 SS |
655 | |
656 | return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask; | |
1da177e4 LT |
657 | } |
658 | ||
b4e44369 SS |
659 | static u8 hpt3xx_mdma_filter(ide_drive_t *drive) |
660 | { | |
661 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 BZ |
662 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
663 | struct hpt_info *info = pci_get_drvdata(dev); | |
b4e44369 SS |
664 | |
665 | switch (info->chip_type) { | |
666 | case HPT372 : | |
667 | case HPT372A: | |
668 | case HPT372N: | |
669 | case HPT374 : | |
670 | if (ide_dev_is_sata(drive->id)) | |
671 | return 0x00; | |
672 | /* Fall thru */ | |
673 | default: | |
674 | return 0x07; | |
675 | } | |
676 | } | |
677 | ||
7b73ee05 | 678 | static u32 get_speed_setting(u8 speed, struct hpt_info *info) |
1da177e4 | 679 | { |
471a0bda SS |
680 | int i; |
681 | ||
682 | /* | |
683 | * Lookup the transfer mode table to get the index into | |
684 | * the timing table. | |
685 | * | |
686 | * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used. | |
687 | */ | |
688 | for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++) | |
689 | if (xfer_speeds[i] == speed) | |
690 | break; | |
866664d7 SS |
691 | |
692 | return info->timings->clock_table[info->clock][i]; | |
1da177e4 LT |
693 | } |
694 | ||
866664d7 | 695 | static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 696 | { |
36501650 | 697 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
7b73ee05 | 698 | struct hpt_info *info = pci_get_drvdata(dev); |
866664d7 SS |
699 | struct hpt_timings *t = info->timings; |
700 | u8 itr_addr = 0x40 + (drive->dn * 4); | |
26ccb802 | 701 | u32 old_itr = 0; |
ceb1b2c5 | 702 | u32 new_itr = get_speed_setting(speed, info); |
866664d7 SS |
703 | u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask : |
704 | (speed < XFER_UDMA_0 ? t->dma_mask : | |
705 | t->ultra_mask); | |
b39b01ff | 706 | |
ceb1b2c5 SS |
707 | pci_read_config_dword(dev, itr_addr, &old_itr); |
708 | new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask); | |
1da177e4 | 709 | /* |
abc4ad4c SS |
710 | * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) |
711 | * to avoid problems handling I/O errors later | |
1da177e4 | 712 | */ |
abc4ad4c | 713 | new_itr &= ~0xc0000000; |
1da177e4 | 714 | |
abc4ad4c | 715 | pci_write_config_dword(dev, itr_addr, new_itr); |
1da177e4 LT |
716 | } |
717 | ||
26bcb879 | 718 | static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 719 | { |
866664d7 | 720 | hpt3xx_set_mode(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
721 | } |
722 | ||
f01393e4 | 723 | static void hpt3xx_quirkproc(ide_drive_t *drive) |
1da177e4 | 724 | { |
e139b0b0 SS |
725 | struct hd_driveid *id = drive->id; |
726 | const char **list = quirk_drives; | |
727 | ||
728 | while (*list) | |
f01393e4 BZ |
729 | if (strstr(id->model, *list++)) { |
730 | drive->quirk_list = 1; | |
731 | return; | |
732 | } | |
733 | ||
734 | drive->quirk_list = 0; | |
1da177e4 LT |
735 | } |
736 | ||
26ccb802 | 737 | static void hpt3xx_maskproc(ide_drive_t *drive, int mask) |
1da177e4 | 738 | { |
abc4ad4c | 739 | ide_hwif_t *hwif = HWIF(drive); |
36501650 | 740 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
7b73ee05 | 741 | struct hpt_info *info = pci_get_drvdata(dev); |
1da177e4 LT |
742 | |
743 | if (drive->quirk_list) { | |
7b73ee05 | 744 | if (info->chip_type >= HPT370) { |
abc4ad4c SS |
745 | u8 scr1 = 0; |
746 | ||
747 | pci_read_config_byte(dev, 0x5a, &scr1); | |
748 | if (((scr1 & 0x10) >> 4) != mask) { | |
749 | if (mask) | |
750 | scr1 |= 0x10; | |
751 | else | |
752 | scr1 &= ~0x10; | |
753 | pci_write_config_byte(dev, 0x5a, scr1); | |
754 | } | |
1da177e4 | 755 | } else { |
abc4ad4c | 756 | if (mask) |
b39b01ff | 757 | disable_irq(hwif->irq); |
abc4ad4c SS |
758 | else |
759 | enable_irq (hwif->irq); | |
1da177e4 | 760 | } |
abc4ad4c | 761 | } else |
31e8a465 BZ |
762 | outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), |
763 | IDE_CONTROL_REG); | |
1da177e4 LT |
764 | } |
765 | ||
1da177e4 | 766 | /* |
abc4ad4c | 767 | * This is specific to the HPT366 UDMA chipset |
1da177e4 LT |
768 | * by HighPoint|Triones Technologies, Inc. |
769 | */ | |
841d2a9b | 770 | static void hpt366_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 771 | { |
36501650 | 772 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
abc4ad4c SS |
773 | u8 mcr1 = 0, mcr3 = 0, scr1 = 0; |
774 | ||
775 | pci_read_config_byte(dev, 0x50, &mcr1); | |
776 | pci_read_config_byte(dev, 0x52, &mcr3); | |
777 | pci_read_config_byte(dev, 0x5a, &scr1); | |
778 | printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n", | |
779 | drive->name, __FUNCTION__, mcr1, mcr3, scr1); | |
780 | if (scr1 & 0x10) | |
781 | pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); | |
841d2a9b | 782 | ide_dma_lost_irq(drive); |
1da177e4 LT |
783 | } |
784 | ||
4bf63de2 | 785 | static void hpt370_clear_engine(ide_drive_t *drive) |
1da177e4 | 786 | { |
abc4ad4c | 787 | ide_hwif_t *hwif = HWIF(drive); |
36501650 | 788 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
abc4ad4c | 789 | |
36501650 | 790 | pci_write_config_byte(dev, hwif->select_data, 0x37); |
1da177e4 LT |
791 | udelay(10); |
792 | } | |
793 | ||
4bf63de2 SS |
794 | static void hpt370_irq_timeout(ide_drive_t *drive) |
795 | { | |
796 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 797 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
4bf63de2 SS |
798 | u16 bfifo = 0; |
799 | u8 dma_cmd; | |
800 | ||
36501650 | 801 | pci_read_config_word(dev, hwif->select_data + 2, &bfifo); |
4bf63de2 SS |
802 | printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff); |
803 | ||
804 | /* get DMA command mode */ | |
31e8a465 | 805 | dma_cmd = inb(hwif->dma_command); |
4bf63de2 | 806 | /* stop DMA */ |
31e8a465 | 807 | outb(dma_cmd & ~0x1, hwif->dma_command); |
4bf63de2 SS |
808 | hpt370_clear_engine(drive); |
809 | } | |
810 | ||
1da177e4 LT |
811 | static void hpt370_ide_dma_start(ide_drive_t *drive) |
812 | { | |
813 | #ifdef HPT_RESET_STATE_ENGINE | |
814 | hpt370_clear_engine(drive); | |
815 | #endif | |
816 | ide_dma_start(drive); | |
817 | } | |
818 | ||
4bf63de2 | 819 | static int hpt370_ide_dma_end(ide_drive_t *drive) |
1da177e4 LT |
820 | { |
821 | ide_hwif_t *hwif = HWIF(drive); | |
31e8a465 | 822 | u8 dma_stat = inb(hwif->dma_status); |
1da177e4 LT |
823 | |
824 | if (dma_stat & 0x01) { | |
825 | /* wait a little */ | |
826 | udelay(20); | |
31e8a465 | 827 | dma_stat = inb(hwif->dma_status); |
4bf63de2 SS |
828 | if (dma_stat & 0x01) |
829 | hpt370_irq_timeout(drive); | |
1da177e4 | 830 | } |
1da177e4 LT |
831 | return __ide_dma_end(drive); |
832 | } | |
833 | ||
c283f5db | 834 | static void hpt370_dma_timeout(ide_drive_t *drive) |
1da177e4 | 835 | { |
4bf63de2 | 836 | hpt370_irq_timeout(drive); |
c283f5db | 837 | ide_dma_timeout(drive); |
1da177e4 LT |
838 | } |
839 | ||
1da177e4 LT |
840 | /* returns 1 if DMA IRQ issued, 0 otherwise */ |
841 | static int hpt374_ide_dma_test_irq(ide_drive_t *drive) | |
842 | { | |
843 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 844 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 845 | u16 bfifo = 0; |
abc4ad4c | 846 | u8 dma_stat; |
1da177e4 | 847 | |
36501650 | 848 | pci_read_config_word(dev, hwif->select_data + 2, &bfifo); |
1da177e4 LT |
849 | if (bfifo & 0x1FF) { |
850 | // printk("%s: %d bytes in FIFO\n", drive->name, bfifo); | |
851 | return 0; | |
852 | } | |
853 | ||
0ecdca26 | 854 | dma_stat = inb(hwif->dma_status); |
1da177e4 | 855 | /* return 1 if INTR asserted */ |
abc4ad4c | 856 | if (dma_stat & 4) |
1da177e4 LT |
857 | return 1; |
858 | ||
859 | if (!drive->waiting_for_dma) | |
860 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
861 | drive->name, __FUNCTION__); | |
862 | return 0; | |
863 | } | |
864 | ||
abc4ad4c | 865 | static int hpt374_ide_dma_end(ide_drive_t *drive) |
1da177e4 | 866 | { |
1da177e4 | 867 | ide_hwif_t *hwif = HWIF(drive); |
36501650 | 868 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
abc4ad4c SS |
869 | u8 mcr = 0, mcr_addr = hwif->select_data; |
870 | u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01; | |
871 | ||
872 | pci_read_config_byte(dev, 0x6a, &bwsr); | |
873 | pci_read_config_byte(dev, mcr_addr, &mcr); | |
874 | if (bwsr & mask) | |
875 | pci_write_config_byte(dev, mcr_addr, mcr | 0x30); | |
1da177e4 LT |
876 | return __ide_dma_end(drive); |
877 | } | |
878 | ||
879 | /** | |
836c0063 SS |
880 | * hpt3xxn_set_clock - perform clock switching dance |
881 | * @hwif: hwif to switch | |
882 | * @mode: clocking mode (0x21 for write, 0x23 otherwise) | |
1da177e4 | 883 | * |
836c0063 | 884 | * Switch the DPLL clock on the HPT3xxN devices. This is a right mess. |
1da177e4 | 885 | */ |
836c0063 SS |
886 | |
887 | static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) | |
1da177e4 | 888 | { |
1c029fd6 BZ |
889 | unsigned long base = hwif->extra_base; |
890 | u8 scr2 = inb(base + 0x6b); | |
836c0063 SS |
891 | |
892 | if ((scr2 & 0x7f) == mode) | |
893 | return; | |
894 | ||
1da177e4 | 895 | /* Tristate the bus */ |
1c029fd6 BZ |
896 | outb(0x80, base + 0x63); |
897 | outb(0x80, base + 0x67); | |
836c0063 | 898 | |
1da177e4 | 899 | /* Switch clock and reset channels */ |
1c029fd6 BZ |
900 | outb(mode, base + 0x6b); |
901 | outb(0xc0, base + 0x69); | |
836c0063 | 902 | |
7b73ee05 SS |
903 | /* |
904 | * Reset the state machines. | |
905 | * NOTE: avoid accidentally enabling the disabled channels. | |
906 | */ | |
1c029fd6 BZ |
907 | outb(inb(base + 0x60) | 0x32, base + 0x60); |
908 | outb(inb(base + 0x64) | 0x32, base + 0x64); | |
836c0063 | 909 | |
1da177e4 | 910 | /* Complete reset */ |
1c029fd6 | 911 | outb(0x00, base + 0x69); |
836c0063 | 912 | |
1da177e4 | 913 | /* Reconnect channels to bus */ |
1c029fd6 BZ |
914 | outb(0x00, base + 0x63); |
915 | outb(0x00, base + 0x67); | |
1da177e4 LT |
916 | } |
917 | ||
918 | /** | |
836c0063 | 919 | * hpt3xxn_rw_disk - prepare for I/O |
1da177e4 LT |
920 | * @drive: drive for command |
921 | * @rq: block request structure | |
922 | * | |
836c0063 | 923 | * This is called when a disk I/O is issued to HPT3xxN. |
1da177e4 LT |
924 | * We need it because of the clock switching. |
925 | */ | |
926 | ||
836c0063 | 927 | static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) |
1da177e4 | 928 | { |
7b73ee05 | 929 | hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21); |
1da177e4 LT |
930 | } |
931 | ||
1da177e4 | 932 | /* |
33b18a60 | 933 | * Set/get power state for a drive. |
abc4ad4c | 934 | * NOTE: affects both drives on each channel. |
1da177e4 | 935 | * |
33b18a60 | 936 | * When we turn the power back on, we need to re-initialize things. |
1da177e4 LT |
937 | */ |
938 | #define TRISTATE_BIT 0x8000 | |
33b18a60 SS |
939 | |
940 | static int hpt3xx_busproc(ide_drive_t *drive, int state) | |
1da177e4 | 941 | { |
abc4ad4c | 942 | ide_hwif_t *hwif = HWIF(drive); |
36501650 | 943 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
abc4ad4c SS |
944 | u8 mcr_addr = hwif->select_data + 2; |
945 | u8 resetmask = hwif->channel ? 0x80 : 0x40; | |
946 | u8 bsr2 = 0; | |
947 | u16 mcr = 0; | |
1da177e4 LT |
948 | |
949 | hwif->bus_state = state; | |
950 | ||
33b18a60 | 951 | /* Grab the status. */ |
abc4ad4c SS |
952 | pci_read_config_word(dev, mcr_addr, &mcr); |
953 | pci_read_config_byte(dev, 0x59, &bsr2); | |
1da177e4 | 954 | |
33b18a60 SS |
955 | /* |
956 | * Set the state. We don't set it if we don't need to do so. | |
957 | * Make sure that the drive knows that it has failed if it's off. | |
958 | */ | |
1da177e4 LT |
959 | switch (state) { |
960 | case BUSSTATE_ON: | |
abc4ad4c | 961 | if (!(bsr2 & resetmask)) |
1da177e4 | 962 | return 0; |
33b18a60 SS |
963 | hwif->drives[0].failures = hwif->drives[1].failures = 0; |
964 | ||
abc4ad4c SS |
965 | pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask); |
966 | pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT); | |
33b18a60 | 967 | return 0; |
1da177e4 | 968 | case BUSSTATE_OFF: |
abc4ad4c | 969 | if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT)) |
1da177e4 | 970 | return 0; |
abc4ad4c | 971 | mcr &= ~TRISTATE_BIT; |
1da177e4 LT |
972 | break; |
973 | case BUSSTATE_TRISTATE: | |
abc4ad4c | 974 | if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT)) |
1da177e4 | 975 | return 0; |
abc4ad4c | 976 | mcr |= TRISTATE_BIT; |
1da177e4 | 977 | break; |
33b18a60 SS |
978 | default: |
979 | return -EINVAL; | |
1da177e4 | 980 | } |
1da177e4 | 981 | |
33b18a60 SS |
982 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; |
983 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
984 | ||
abc4ad4c SS |
985 | pci_write_config_word(dev, mcr_addr, mcr); |
986 | pci_write_config_byte(dev, 0x59, bsr2 | resetmask); | |
1da177e4 LT |
987 | return 0; |
988 | } | |
989 | ||
7b73ee05 SS |
990 | /** |
991 | * hpt37x_calibrate_dpll - calibrate the DPLL | |
992 | * @dev: PCI device | |
993 | * | |
994 | * Perform a calibration cycle on the DPLL. | |
995 | * Returns 1 if this succeeds | |
996 | */ | |
997 | static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high) | |
1da177e4 | 998 | { |
7b73ee05 SS |
999 | u32 dpll = (f_high << 16) | f_low | 0x100; |
1000 | u8 scr2; | |
1001 | int i; | |
b39b01ff | 1002 | |
7b73ee05 | 1003 | pci_write_config_dword(dev, 0x5c, dpll); |
b39b01ff | 1004 | |
7b73ee05 SS |
1005 | /* Wait for oscillator ready */ |
1006 | for(i = 0; i < 0x5000; ++i) { | |
1007 | udelay(50); | |
1008 | pci_read_config_byte(dev, 0x5b, &scr2); | |
1009 | if (scr2 & 0x80) | |
b39b01ff AC |
1010 | break; |
1011 | } | |
7b73ee05 SS |
1012 | /* See if it stays ready (we'll just bail out if it's not yet) */ |
1013 | for(i = 0; i < 0x1000; ++i) { | |
1014 | pci_read_config_byte(dev, 0x5b, &scr2); | |
1015 | /* DPLL destabilized? */ | |
1016 | if(!(scr2 & 0x80)) | |
1017 | return 0; | |
1018 | } | |
1019 | /* Turn off tuning, we have the DPLL set */ | |
1020 | pci_read_config_dword (dev, 0x5c, &dpll); | |
1021 | pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); | |
1022 | return 1; | |
b39b01ff AC |
1023 | } |
1024 | ||
7b73ee05 | 1025 | static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name) |
b39b01ff | 1026 | { |
7b73ee05 SS |
1027 | struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL); |
1028 | unsigned long io_base = pci_resource_start(dev, 4); | |
1029 | u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */ | |
72931368 | 1030 | u8 chip_type; |
7b73ee05 SS |
1031 | enum ata_clock clock; |
1032 | ||
1033 | if (info == NULL) { | |
1034 | printk(KERN_ERR "%s: out of memory!\n", name); | |
1035 | return -ENOMEM; | |
1036 | } | |
1037 | ||
1da177e4 | 1038 | /* |
7b73ee05 SS |
1039 | * Copy everything from a static "template" structure |
1040 | * to just allocated per-chip hpt_info structure. | |
1da177e4 | 1041 | */ |
72931368 SS |
1042 | memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info)); |
1043 | chip_type = info->chip_type; | |
1da177e4 | 1044 | |
7b73ee05 SS |
1045 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); |
1046 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
1047 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
1048 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
26c068da | 1049 | |
1da177e4 | 1050 | /* |
7b73ee05 | 1051 | * First, try to estimate the PCI clock frequency... |
1da177e4 | 1052 | */ |
72931368 | 1053 | if (chip_type >= HPT370) { |
7b73ee05 SS |
1054 | u8 scr1 = 0; |
1055 | u16 f_cnt = 0; | |
1056 | u32 temp = 0; | |
1057 | ||
1058 | /* Interrupt force enable. */ | |
1059 | pci_read_config_byte(dev, 0x5a, &scr1); | |
1060 | if (scr1 & 0x10) | |
1061 | pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); | |
1062 | ||
1063 | /* | |
1064 | * HighPoint does this for HPT372A. | |
1065 | * NOTE: This register is only writeable via I/O space. | |
1066 | */ | |
72931368 | 1067 | if (chip_type == HPT372A) |
7b73ee05 SS |
1068 | outb(0x0e, io_base + 0x9c); |
1069 | ||
1070 | /* | |
1071 | * Default to PCI clock. Make sure MA15/16 are set to output | |
1072 | * to prevent drives having problems with 40-pin cables. | |
1073 | */ | |
1074 | pci_write_config_byte(dev, 0x5b, 0x23); | |
836c0063 | 1075 | |
7b73ee05 SS |
1076 | /* |
1077 | * We'll have to read f_CNT value in order to determine | |
1078 | * the PCI clock frequency according to the following ratio: | |
1079 | * | |
1080 | * f_CNT = Fpci * 192 / Fdpll | |
1081 | * | |
1082 | * First try reading the register in which the HighPoint BIOS | |
1083 | * saves f_CNT value before reprogramming the DPLL from its | |
1084 | * default setting (which differs for the various chips). | |
7b73ee05 | 1085 | * |
72931368 SS |
1086 | * NOTE: This register is only accessible via I/O space; |
1087 | * HPT374 BIOS only saves it for the function 0, so we have to | |
1088 | * always read it from there -- no need to check the result of | |
1089 | * pci_get_slot() for the function 0 as the whole device has | |
1090 | * been already "pinned" (via function 1) in init_setup_hpt374() | |
1091 | */ | |
1092 | if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { | |
1093 | struct pci_dev *dev1 = pci_get_slot(dev->bus, | |
1094 | dev->devfn - 1); | |
1095 | unsigned long io_base = pci_resource_start(dev1, 4); | |
1096 | ||
1097 | temp = inl(io_base + 0x90); | |
1098 | pci_dev_put(dev1); | |
1099 | } else | |
1100 | temp = inl(io_base + 0x90); | |
1101 | ||
1102 | /* | |
1103 | * In case the signature check fails, we'll have to | |
1104 | * resort to reading the f_CNT register itself in hopes | |
1105 | * that nobody has touched the DPLL yet... | |
7b73ee05 | 1106 | */ |
7b73ee05 SS |
1107 | if ((temp & 0xFFFFF000) != 0xABCDE000) { |
1108 | int i; | |
1109 | ||
1110 | printk(KERN_WARNING "%s: no clock data saved by BIOS\n", | |
1111 | name); | |
1112 | ||
1113 | /* Calculate the average value of f_CNT. */ | |
1114 | for (temp = i = 0; i < 128; i++) { | |
1115 | pci_read_config_word(dev, 0x78, &f_cnt); | |
1116 | temp += f_cnt & 0x1ff; | |
1117 | mdelay(1); | |
1118 | } | |
1119 | f_cnt = temp / 128; | |
1120 | } else | |
1121 | f_cnt = temp & 0x1ff; | |
1122 | ||
1123 | dpll_clk = info->dpll_clk; | |
1124 | pci_clk = (f_cnt * dpll_clk) / 192; | |
1125 | ||
1126 | /* Clamp PCI clock to bands. */ | |
1127 | if (pci_clk < 40) | |
1128 | pci_clk = 33; | |
1129 | else if(pci_clk < 45) | |
1130 | pci_clk = 40; | |
1131 | else if(pci_clk < 55) | |
1132 | pci_clk = 50; | |
1da177e4 | 1133 | else |
7b73ee05 | 1134 | pci_clk = 66; |
836c0063 | 1135 | |
7b73ee05 SS |
1136 | printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, " |
1137 | "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk); | |
90778574 | 1138 | } else { |
7b73ee05 SS |
1139 | u32 itr1 = 0; |
1140 | ||
1141 | pci_read_config_dword(dev, 0x40, &itr1); | |
1142 | ||
1143 | /* Detect PCI clock by looking at cmd_high_time. */ | |
1144 | switch((itr1 >> 8) & 0x07) { | |
1145 | case 0x09: | |
1146 | pci_clk = 40; | |
6273d26a | 1147 | break; |
7b73ee05 SS |
1148 | case 0x05: |
1149 | pci_clk = 25; | |
6273d26a | 1150 | break; |
7b73ee05 SS |
1151 | case 0x07: |
1152 | default: | |
1153 | pci_clk = 33; | |
6273d26a | 1154 | break; |
1da177e4 LT |
1155 | } |
1156 | } | |
836c0063 | 1157 | |
7b73ee05 SS |
1158 | /* Let's assume we'll use PCI clock for the ATA clock... */ |
1159 | switch (pci_clk) { | |
1160 | case 25: | |
1161 | clock = ATA_CLOCK_25MHZ; | |
1162 | break; | |
1163 | case 33: | |
1164 | default: | |
1165 | clock = ATA_CLOCK_33MHZ; | |
1166 | break; | |
1167 | case 40: | |
1168 | clock = ATA_CLOCK_40MHZ; | |
1169 | break; | |
1170 | case 50: | |
1171 | clock = ATA_CLOCK_50MHZ; | |
1172 | break; | |
1173 | case 66: | |
1174 | clock = ATA_CLOCK_66MHZ; | |
1175 | break; | |
1176 | } | |
836c0063 | 1177 | |
1da177e4 | 1178 | /* |
7b73ee05 SS |
1179 | * Only try the DPLL if we don't have a table for the PCI clock that |
1180 | * we are running at for HPT370/A, always use it for anything newer... | |
b39b01ff | 1181 | * |
7b73ee05 SS |
1182 | * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI. |
1183 | * We also don't like using the DPLL because this causes glitches | |
1184 | * on PRST-/SRST- when the state engine gets reset... | |
1da177e4 | 1185 | */ |
866664d7 | 1186 | if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) { |
7b73ee05 SS |
1187 | u16 f_low, delta = pci_clk < 50 ? 2 : 4; |
1188 | int adjust; | |
1189 | ||
1190 | /* | |
1191 | * Select 66 MHz DPLL clock only if UltraATA/133 mode is | |
1192 | * supported/enabled, use 50 MHz DPLL clock otherwise... | |
1193 | */ | |
fbf47840 | 1194 | if (info->udma_mask == ATA_UDMA6) { |
7b73ee05 SS |
1195 | dpll_clk = 66; |
1196 | clock = ATA_CLOCK_66MHZ; | |
1197 | } else if (dpll_clk) { /* HPT36x chips don't have DPLL */ | |
1198 | dpll_clk = 50; | |
1199 | clock = ATA_CLOCK_50MHZ; | |
1200 | } | |
b39b01ff | 1201 | |
866664d7 | 1202 | if (info->timings->clock_table[clock] == NULL) { |
7b73ee05 SS |
1203 | printk(KERN_ERR "%s: unknown bus timing!\n", name); |
1204 | kfree(info); | |
1205 | return -EIO; | |
1da177e4 | 1206 | } |
1da177e4 | 1207 | |
7b73ee05 SS |
1208 | /* Select the DPLL clock. */ |
1209 | pci_write_config_byte(dev, 0x5b, 0x21); | |
1210 | ||
1211 | /* | |
1212 | * Adjust the DPLL based upon PCI clock, enable it, | |
1213 | * and wait for stabilization... | |
1214 | */ | |
1215 | f_low = (pci_clk * 48) / dpll_clk; | |
1216 | ||
1217 | for (adjust = 0; adjust < 8; adjust++) { | |
1218 | if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta)) | |
1219 | break; | |
1220 | ||
1221 | /* | |
1222 | * See if it'll settle at a fractionally different clock | |
1223 | */ | |
1224 | if (adjust & 1) | |
1225 | f_low -= adjust >> 1; | |
1226 | else | |
1227 | f_low += adjust >> 1; | |
1228 | } | |
1229 | if (adjust == 8) { | |
1230 | printk(KERN_ERR "%s: DPLL did not stabilize!\n", name); | |
1231 | kfree(info); | |
1232 | return -EIO; | |
1233 | } | |
1234 | ||
1235 | printk("%s: using %d MHz DPLL clock\n", name, dpll_clk); | |
1236 | } else { | |
1237 | /* Mark the fact that we're not using the DPLL. */ | |
1238 | dpll_clk = 0; | |
1239 | ||
1240 | printk("%s: using %d MHz PCI clock\n", name, pci_clk); | |
1241 | } | |
b39b01ff | 1242 | |
7b73ee05 SS |
1243 | /* Store the clock frequencies. */ |
1244 | info->dpll_clk = dpll_clk; | |
1245 | info->pci_clk = pci_clk; | |
866664d7 | 1246 | info->clock = clock; |
1da177e4 | 1247 | |
7b73ee05 SS |
1248 | /* Point to this chip's own instance of the hpt_info structure. */ |
1249 | pci_set_drvdata(dev, info); | |
b39b01ff | 1250 | |
72931368 | 1251 | if (chip_type >= HPT370) { |
7b73ee05 SS |
1252 | u8 mcr1, mcr4; |
1253 | ||
1254 | /* | |
1255 | * Reset the state engines. | |
1256 | * NOTE: Avoid accidentally enabling the disabled channels. | |
1257 | */ | |
1258 | pci_read_config_byte (dev, 0x50, &mcr1); | |
1259 | pci_read_config_byte (dev, 0x54, &mcr4); | |
1260 | pci_write_config_byte(dev, 0x50, (mcr1 | 0x32)); | |
1261 | pci_write_config_byte(dev, 0x54, (mcr4 | 0x32)); | |
1262 | udelay(100); | |
26ccb802 | 1263 | } |
1da177e4 | 1264 | |
7b73ee05 SS |
1265 | /* |
1266 | * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in | |
1267 | * the MISC. register to stretch the UltraDMA Tss timing. | |
1268 | * NOTE: This register is only writeable via I/O space. | |
1269 | */ | |
72931368 | 1270 | if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ) |
7b73ee05 SS |
1271 | |
1272 | outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c); | |
1273 | ||
1da177e4 LT |
1274 | return dev->irq; |
1275 | } | |
1276 | ||
bfa14b42 BZ |
1277 | static u8 __devinit hpt3xx_cable_detect(ide_hwif_t *hwif) |
1278 | { | |
1279 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
1280 | struct hpt_info *info = pci_get_drvdata(dev); | |
1281 | u8 chip_type = info->chip_type; | |
1282 | u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02; | |
1283 | ||
1284 | /* | |
1285 | * The HPT37x uses the CBLID pins as outputs for MA15/MA16 | |
1286 | * address lines to access an external EEPROM. To read valid | |
1287 | * cable detect state the pins must be enabled as inputs. | |
1288 | */ | |
1289 | if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { | |
1290 | /* | |
1291 | * HPT374 PCI function 1 | |
1292 | * - set bit 15 of reg 0x52 to enable TCBLID as input | |
1293 | * - set bit 15 of reg 0x56 to enable FCBLID as input | |
1294 | */ | |
1295 | u8 mcr_addr = hwif->select_data + 2; | |
1296 | u16 mcr; | |
1297 | ||
1298 | pci_read_config_word(dev, mcr_addr, &mcr); | |
1299 | pci_write_config_word(dev, mcr_addr, (mcr | 0x8000)); | |
1300 | /* now read cable id register */ | |
1301 | pci_read_config_byte(dev, 0x5a, &scr1); | |
1302 | pci_write_config_word(dev, mcr_addr, mcr); | |
1303 | } else if (chip_type >= HPT370) { | |
1304 | /* | |
1305 | * HPT370/372 and 374 pcifn 0 | |
1306 | * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs | |
1307 | */ | |
1308 | u8 scr2 = 0; | |
1309 | ||
1310 | pci_read_config_byte(dev, 0x5b, &scr2); | |
1311 | pci_write_config_byte(dev, 0x5b, (scr2 & ~1)); | |
1312 | /* now read cable id register */ | |
1313 | pci_read_config_byte(dev, 0x5a, &scr1); | |
1314 | pci_write_config_byte(dev, 0x5b, scr2); | |
1315 | } else | |
1316 | pci_read_config_byte(dev, 0x5a, &scr1); | |
1317 | ||
1318 | return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; | |
1319 | } | |
1320 | ||
1da177e4 LT |
1321 | static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) |
1322 | { | |
36501650 | 1323 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
2808b0a9 SS |
1324 | struct hpt_info *info = pci_get_drvdata(dev); |
1325 | int serialize = HPT_SERIALIZE_IO; | |
2808b0a9 SS |
1326 | u8 chip_type = info->chip_type; |
1327 | u8 new_mcr, old_mcr = 0; | |
abc4ad4c SS |
1328 | |
1329 | /* Cache the channel's MISC. control registers' offset */ | |
2808b0a9 | 1330 | hwif->select_data = hwif->channel ? 0x54 : 0x50; |
abc4ad4c | 1331 | |
26bcb879 | 1332 | hwif->set_pio_mode = &hpt3xx_set_pio_mode; |
866664d7 | 1333 | hwif->set_dma_mode = &hpt3xx_set_mode; |
a488f34e | 1334 | |
2808b0a9 | 1335 | hwif->quirkproc = &hpt3xx_quirkproc; |
2808b0a9 SS |
1336 | hwif->maskproc = &hpt3xx_maskproc; |
1337 | hwif->busproc = &hpt3xx_busproc; | |
2648e5d9 | 1338 | |
2808b0a9 | 1339 | hwif->udma_filter = &hpt3xx_udma_filter; |
b4e44369 | 1340 | hwif->mdma_filter = &hpt3xx_mdma_filter; |
abc4ad4c | 1341 | |
bfa14b42 BZ |
1342 | hwif->cable_detect = hpt3xx_cable_detect; |
1343 | ||
836c0063 SS |
1344 | /* |
1345 | * HPT3xxN chips have some complications: | |
1346 | * | |
1347 | * - on 33 MHz PCI we must clock switch | |
1348 | * - on 66 MHz PCI we must NOT use the PCI clock | |
1349 | */ | |
7b73ee05 | 1350 | if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) { |
836c0063 SS |
1351 | /* |
1352 | * Clock is shared between the channels, | |
1353 | * so we'll have to serialize them... :-( | |
1354 | */ | |
1355 | serialize = 1; | |
1356 | hwif->rw_disk = &hpt3xxn_rw_disk; | |
1357 | } | |
1da177e4 | 1358 | |
26ccb802 SS |
1359 | /* Serialize access to this device if needed */ |
1360 | if (serialize && hwif->mate) | |
1361 | hwif->serialized = hwif->mate->serialized = 1; | |
1362 | ||
1363 | /* | |
1364 | * Disable the "fast interrupt" prediction. Don't hold off | |
1365 | * on interrupts. (== 0x01 despite what the docs say) | |
1366 | */ | |
1367 | pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr); | |
1368 | ||
7b73ee05 | 1369 | if (info->chip_type >= HPT374) |
26ccb802 | 1370 | new_mcr = old_mcr & ~0x07; |
7b73ee05 | 1371 | else if (info->chip_type >= HPT370) { |
26ccb802 SS |
1372 | new_mcr = old_mcr; |
1373 | new_mcr &= ~0x02; | |
1374 | ||
1375 | #ifdef HPT_DELAY_INTERRUPT | |
1376 | new_mcr &= ~0x01; | |
1377 | #else | |
1378 | new_mcr |= 0x01; | |
1379 | #endif | |
1380 | } else /* HPT366 and HPT368 */ | |
1381 | new_mcr = old_mcr & ~0x80; | |
1382 | ||
1383 | if (new_mcr != old_mcr) | |
1384 | pci_write_config_byte(dev, hwif->select_data + 1, new_mcr); | |
1385 | ||
a29ec3b2 | 1386 | if (hwif->dma_base == 0) |
26ccb802 | 1387 | return; |
26ccb802 | 1388 | |
7b73ee05 | 1389 | if (chip_type >= HPT374) { |
26ccb802 SS |
1390 | hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq; |
1391 | hwif->ide_dma_end = &hpt374_ide_dma_end; | |
7b73ee05 | 1392 | } else if (chip_type >= HPT370) { |
26ccb802 SS |
1393 | hwif->dma_start = &hpt370_ide_dma_start; |
1394 | hwif->ide_dma_end = &hpt370_ide_dma_end; | |
c283f5db | 1395 | hwif->dma_timeout = &hpt370_dma_timeout; |
26ccb802 | 1396 | } else |
841d2a9b | 1397 | hwif->dma_lost_irq = &hpt366_dma_lost_irq; |
1da177e4 LT |
1398 | } |
1399 | ||
1400 | static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase) | |
1401 | { | |
36501650 | 1402 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
abc4ad4c SS |
1403 | u8 masterdma = 0, slavedma = 0; |
1404 | u8 dma_new = 0, dma_old = 0; | |
1da177e4 LT |
1405 | unsigned long flags; |
1406 | ||
31e8a465 | 1407 | dma_old = inb(dmabase + 2); |
1da177e4 LT |
1408 | |
1409 | local_irq_save(flags); | |
1410 | ||
1411 | dma_new = dma_old; | |
abc4ad4c SS |
1412 | pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma); |
1413 | pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma); | |
1da177e4 LT |
1414 | |
1415 | if (masterdma & 0x30) dma_new |= 0x20; | |
abc4ad4c | 1416 | if ( slavedma & 0x30) dma_new |= 0x40; |
1da177e4 | 1417 | if (dma_new != dma_old) |
31e8a465 | 1418 | outb(dma_new, dmabase + 2); |
1da177e4 LT |
1419 | |
1420 | local_irq_restore(flags); | |
1421 | ||
ecf32796 | 1422 | ide_setup_dma(hwif, dmabase); |
1da177e4 LT |
1423 | } |
1424 | ||
fbf47840 | 1425 | static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2) |
1da177e4 | 1426 | { |
fbf47840 BZ |
1427 | if (dev2->irq != dev->irq) { |
1428 | /* FIXME: we need a core pci_set_interrupt() */ | |
1429 | dev2->irq = dev->irq; | |
1430 | printk(KERN_INFO "HPT374: PCI config space interrupt fixed\n"); | |
1da177e4 | 1431 | } |
1da177e4 LT |
1432 | } |
1433 | ||
fbf47840 | 1434 | static void __devinit hpt371_init(struct pci_dev *dev) |
836c0063 | 1435 | { |
44c10138 | 1436 | u8 mcr1 = 0; |
90778574 | 1437 | |
836c0063 SS |
1438 | /* |
1439 | * HPT371 chips physically have only one channel, the secondary one, | |
1440 | * but the primary channel registers do exist! Go figure... | |
1441 | * So, we manually disable the non-existing channel here | |
1442 | * (if the BIOS hasn't done this already). | |
1443 | */ | |
1444 | pci_read_config_byte(dev, 0x50, &mcr1); | |
1445 | if (mcr1 & 0x04) | |
90778574 | 1446 | pci_write_config_byte(dev, 0x50, mcr1 & ~0x04); |
90778574 SS |
1447 | } |
1448 | ||
fbf47840 | 1449 | static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2) |
90778574 | 1450 | { |
fbf47840 | 1451 | u8 mcr1 = 0, pin1 = 0, pin2 = 0; |
7b73ee05 | 1452 | |
fbf47840 BZ |
1453 | /* |
1454 | * Now we'll have to force both channels enabled if | |
1455 | * at least one of them has been enabled by BIOS... | |
1456 | */ | |
1457 | pci_read_config_byte(dev, 0x50, &mcr1); | |
1458 | if (mcr1 & 0x30) | |
1459 | pci_write_config_byte(dev, 0x50, mcr1 | 0x30); | |
836c0063 | 1460 | |
fbf47840 BZ |
1461 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); |
1462 | pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2); | |
1da177e4 | 1463 | |
fbf47840 BZ |
1464 | if (pin1 != pin2 && dev->irq == dev2->irq) { |
1465 | printk(KERN_INFO "HPT36x: onboard version of chipset, " | |
1466 | "pin1=%d pin2=%d\n", pin1, pin2); | |
1467 | return 1; | |
2648e5d9 SS |
1468 | } |
1469 | ||
fbf47840 | 1470 | return 0; |
1da177e4 LT |
1471 | } |
1472 | ||
4db90a14 BZ |
1473 | #define IDE_HFLAGS_HPT3XX \ |
1474 | (IDE_HFLAG_NO_ATAPI_DMA | \ | |
1475 | IDE_HFLAG_ABUSE_SET_DMA_MODE | \ | |
1476 | IDE_HFLAG_OFF_BOARD) | |
1477 | ||
85620436 | 1478 | static const struct ide_port_info hpt366_chipsets[] __devinitdata = { |
1da177e4 | 1479 | { /* 0 */ |
fbf47840 | 1480 | .name = "HPT36x", |
1da177e4 LT |
1481 | .init_chipset = init_chipset_hpt366, |
1482 | .init_hwif = init_hwif_hpt366, | |
1483 | .init_dma = init_dma_hpt366, | |
fbf47840 BZ |
1484 | /* |
1485 | * HPT36x chips have one channel per function and have | |
1486 | * both channel enable bits located differently and visible | |
1487 | * to both functions -- really stupid design decision... :-( | |
1488 | * Bit 4 is for the primary channel, bit 5 for the secondary. | |
1489 | */ | |
1490 | .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}}, | |
4099d143 | 1491 | .extra = 240, |
4db90a14 | 1492 | .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE, |
4099d143 | 1493 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1494 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1495 | },{ /* 1 */ |
1496 | .name = "HPT372A", | |
1da177e4 LT |
1497 | .init_chipset = init_chipset_hpt366, |
1498 | .init_hwif = init_hwif_hpt366, | |
1499 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1500 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
4099d143 | 1501 | .extra = 240, |
4db90a14 | 1502 | .host_flags = IDE_HFLAGS_HPT3XX, |
4099d143 | 1503 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1504 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1505 | },{ /* 2 */ |
1506 | .name = "HPT302", | |
1da177e4 LT |
1507 | .init_chipset = init_chipset_hpt366, |
1508 | .init_hwif = init_hwif_hpt366, | |
1509 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1510 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
4099d143 | 1511 | .extra = 240, |
4db90a14 | 1512 | .host_flags = IDE_HFLAGS_HPT3XX, |
4099d143 | 1513 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1514 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1515 | },{ /* 3 */ |
1516 | .name = "HPT371", | |
1da177e4 LT |
1517 | .init_chipset = init_chipset_hpt366, |
1518 | .init_hwif = init_hwif_hpt366, | |
1519 | .init_dma = init_dma_hpt366, | |
836c0063 | 1520 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
4099d143 | 1521 | .extra = 240, |
4db90a14 | 1522 | .host_flags = IDE_HFLAGS_HPT3XX, |
4099d143 | 1523 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1524 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1525 | },{ /* 4 */ |
1526 | .name = "HPT374", | |
1da177e4 LT |
1527 | .init_chipset = init_chipset_hpt366, |
1528 | .init_hwif = init_hwif_hpt366, | |
1529 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1530 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
2808b0a9 | 1531 | .udma_mask = ATA_UDMA5, |
4099d143 | 1532 | .extra = 240, |
4db90a14 | 1533 | .host_flags = IDE_HFLAGS_HPT3XX, |
4099d143 | 1534 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1535 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1536 | },{ /* 5 */ |
1537 | .name = "HPT372N", | |
1da177e4 LT |
1538 | .init_chipset = init_chipset_hpt366, |
1539 | .init_hwif = init_hwif_hpt366, | |
1540 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1541 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
4099d143 | 1542 | .extra = 240, |
4db90a14 | 1543 | .host_flags = IDE_HFLAGS_HPT3XX, |
4099d143 | 1544 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1545 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1546 | } |
1547 | }; | |
1548 | ||
1549 | /** | |
1550 | * hpt366_init_one - called when an HPT366 is found | |
1551 | * @dev: the hpt366 device | |
1552 | * @id: the matching pci id | |
1553 | * | |
1554 | * Called when the PCI registration layer (or the IDE initialization) | |
1555 | * finds a device matching our IDE device tables. | |
1556 | */ | |
1da177e4 LT |
1557 | static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
1558 | { | |
282037f1 | 1559 | const struct hpt_info *info = NULL; |
fbf47840 | 1560 | struct pci_dev *dev2 = NULL; |
039788e1 | 1561 | struct ide_port_info d; |
fbf47840 BZ |
1562 | u8 idx = id->driver_data; |
1563 | u8 rev = dev->revision; | |
1564 | ||
1565 | if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1)) | |
1566 | return -ENODEV; | |
1567 | ||
1568 | switch (idx) { | |
1569 | case 0: | |
1570 | if (rev < 3) | |
1571 | info = &hpt36x; | |
1572 | else { | |
282037f1 | 1573 | static const struct hpt_info *hpt37x_info[] = |
fbf47840 BZ |
1574 | { &hpt370, &hpt370a, &hpt372, &hpt372n }; |
1575 | ||
1576 | info = hpt37x_info[min_t(u8, rev, 6) - 3]; | |
1577 | idx++; | |
1578 | } | |
1579 | break; | |
1580 | case 1: | |
1581 | info = (rev > 1) ? &hpt372n : &hpt372a; | |
1582 | break; | |
1583 | case 2: | |
1584 | info = (rev > 1) ? &hpt302n : &hpt302; | |
1585 | break; | |
1586 | case 3: | |
1587 | hpt371_init(dev); | |
1588 | info = (rev > 1) ? &hpt371n : &hpt371; | |
1589 | break; | |
1590 | case 4: | |
1591 | info = &hpt374; | |
1592 | break; | |
1593 | case 5: | |
1594 | info = &hpt372n; | |
1595 | break; | |
1596 | } | |
1597 | ||
1598 | d = hpt366_chipsets[idx]; | |
1599 | ||
1600 | d.name = info->chip_name; | |
1601 | d.udma_mask = info->udma_mask; | |
1602 | ||
282037f1 | 1603 | pci_set_drvdata(dev, (void *)info); |
fbf47840 BZ |
1604 | |
1605 | if (info == &hpt36x || info == &hpt374) | |
1606 | dev2 = pci_get_slot(dev->bus, dev->devfn + 1); | |
1607 | ||
1608 | if (dev2) { | |
1609 | int ret; | |
1610 | ||
282037f1 | 1611 | pci_set_drvdata(dev2, (void *)info); |
fbf47840 BZ |
1612 | |
1613 | if (info == &hpt374) | |
1614 | hpt374_init(dev, dev2); | |
1615 | else { | |
1616 | if (hpt36x_init(dev, dev2)) | |
1617 | d.host_flags |= IDE_HFLAG_BOOTABLE; | |
1618 | } | |
1619 | ||
1620 | ret = ide_setup_pci_devices(dev, dev2, &d); | |
1621 | if (ret < 0) | |
1622 | pci_dev_put(dev2); | |
1623 | return ret; | |
1624 | } | |
1da177e4 | 1625 | |
fbf47840 | 1626 | return ide_setup_pci_device(dev, &d); |
1da177e4 LT |
1627 | } |
1628 | ||
9cbcc5e3 BZ |
1629 | static const struct pci_device_id hpt366_pci_tbl[] = { |
1630 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 }, | |
1631 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 }, | |
1632 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 }, | |
1633 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 }, | |
1634 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 }, | |
1635 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 }, | |
1da177e4 LT |
1636 | { 0, }, |
1637 | }; | |
1638 | MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl); | |
1639 | ||
1640 | static struct pci_driver driver = { | |
1641 | .name = "HPT366_IDE", | |
1642 | .id_table = hpt366_pci_tbl, | |
1643 | .probe = hpt366_init_one, | |
1644 | }; | |
1645 | ||
82ab1eec | 1646 | static int __init hpt366_ide_init(void) |
1da177e4 LT |
1647 | { |
1648 | return ide_pci_register_driver(&driver); | |
1649 | } | |
1650 | ||
1651 | module_init(hpt366_ide_init); | |
1652 | ||
1653 | MODULE_AUTHOR("Andre Hedrick"); | |
1654 | MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE"); | |
1655 | MODULE_LICENSE("GPL"); |