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da9091ee | 1 | /* |
da9091ee | 2 | * Copyright (C) 2004 Red Hat <alan@redhat.com> |
0e9b4e53 | 3 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
da9091ee AC |
4 | * |
5 | * May be copied or modified under the terms of the GNU General Public License | |
6 | * Based in part on the ITE vendor provided SCSI driver. | |
7 | * | |
8 | * Documentation available from | |
9 | * http://www.ite.com.tw/pc/IT8212F_V04.pdf | |
10 | * Some other documents are NDA. | |
11 | * | |
12 | * The ITE8212 isn't exactly a standard IDE controller. It has two | |
13 | * modes. In pass through mode then it is an IDE controller. In its smart | |
14 | * mode its actually quite a capable hardware raid controller disguised | |
15 | * as an IDE controller. Smart mode only understands DMA read/write and | |
16 | * identify, none of the fancier commands apply. The IT8211 is identical | |
17 | * in other respects but lacks the raid mode. | |
18 | * | |
19 | * Errata: | |
20 | * o Rev 0x10 also requires master/slave hold the same DMA timings and | |
21 | * cannot do ATAPI MWDMA. | |
22 | * o The identify data for raid volumes lacks CHS info (technically ok) | |
23 | * but also fails to set the LBA28 and other bits. We fix these in | |
24 | * the IDE probe quirk code. | |
25 | * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode | |
26 | * raid then the controller firmware dies | |
27 | * o Smart mode without RAID doesn't clear all the necessary identify | |
28 | * bits to reduce the command set to the one used | |
29 | * | |
30 | * This has a few impacts on the driver | |
31 | * - In pass through mode we do all the work you would expect | |
32 | * - In smart mode the clocking set up is done by the controller generally | |
33 | * but we must watch the other limits and filter. | |
34 | * - There are a few extra vendor commands that actually talk to the | |
35 | * controller but only work PIO with no IRQ. | |
36 | * | |
37 | * Vendor areas of the identify block in smart mode are used for the | |
38 | * timing and policy set up. Each HDD in raid mode also has a serial | |
39 | * block on the disk. The hardware extra commands are get/set chip status, | |
40 | * rebuild, get rebuild status. | |
41 | * | |
42 | * In Linux the driver supports pass through mode as if the device was | |
43 | * just another IDE controller. If the smart mode is running then | |
44 | * volumes are managed by the controller firmware and each IDE "disk" | |
45 | * is a raid volume. Even more cute - the controller can do automated | |
46 | * hotplug and rebuild. | |
47 | * | |
48 | * The pass through controller itself is a little demented. It has a | |
49 | * flaw that it has a single set of PIO/MWDMA timings per channel so | |
50 | * non UDMA devices restrict each others performance. It also has a | |
51 | * single clock source per channel so mixed UDMA100/133 performance | |
52 | * isn't perfect and we have to pick a clock. Thankfully none of this | |
53 | * matters in smart mode. ATAPI DMA is not currently supported. | |
54 | * | |
55 | * It seems the smart mode is a win for RAID1/RAID10 but otherwise not. | |
56 | * | |
57 | * TODO | |
58 | * - ATAPI UDMA is ok but not MWDMA it seems | |
59 | * - RAID configuration ioctls | |
60 | * - Move to libata once it grows up | |
61 | */ | |
62 | ||
da9091ee AC |
63 | #include <linux/types.h> |
64 | #include <linux/module.h> | |
65 | #include <linux/pci.h> | |
da9091ee AC |
66 | #include <linux/hdreg.h> |
67 | #include <linux/ide.h> | |
68 | #include <linux/init.h> | |
69 | ||
da9091ee AC |
70 | struct it821x_dev |
71 | { | |
72 | unsigned int smart:1, /* Are we in smart raid mode */ | |
73 | timing10:1; /* Rev 0x10 */ | |
74 | u8 clock_mode; /* 0, ATA_50 or ATA_66 */ | |
75 | u8 want[2][2]; /* Mode/Pri log for master slave */ | |
76 | /* We need these for switching the clock when DMA goes on/off | |
77 | The high byte is the 66Mhz timing */ | |
78 | u16 pio[2]; /* Cached PIO values */ | |
79 | u16 mwdma[2]; /* Cached MWDMA values */ | |
80 | u16 udma[2]; /* Cached UDMA values (per drive) */ | |
81 | }; | |
82 | ||
83 | #define ATA_66 0 | |
84 | #define ATA_50 1 | |
85 | #define ATA_ANY 2 | |
86 | ||
87 | #define UDMA_OFF 0 | |
88 | #define MWDMA_OFF 0 | |
89 | ||
90 | /* | |
91 | * We allow users to force the card into non raid mode without | |
3a4fa0a2 | 92 | * flashing the alternative BIOS. This is also necessary right now |
da9091ee AC |
93 | * for embedded platforms that cannot run a PC BIOS but are using this |
94 | * device. | |
95 | */ | |
96 | ||
97 | static int it8212_noraid; | |
98 | ||
99 | /** | |
100 | * it821x_program - program the PIO/MWDMA registers | |
101 | * @drive: drive to tune | |
0e9b4e53 | 102 | * @timing: timing info |
da9091ee AC |
103 | * |
104 | * Program the PIO/MWDMA timing for this channel according to the | |
105 | * current clock. | |
106 | */ | |
107 | ||
108 | static void it821x_program(ide_drive_t *drive, u16 timing) | |
109 | { | |
36501650 BZ |
110 | ide_hwif_t *hwif = drive->hwif; |
111 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
112 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
113 | int channel = hwif->channel; | |
114 | u8 conf; | |
115 | ||
116 | /* Program PIO/MWDMA timing bits */ | |
117 | if(itdev->clock_mode == ATA_66) | |
118 | conf = timing >> 8; | |
119 | else | |
120 | conf = timing & 0xFF; | |
36501650 BZ |
121 | |
122 | pci_write_config_byte(dev, 0x54 + 4 * channel, conf); | |
da9091ee AC |
123 | } |
124 | ||
125 | /** | |
126 | * it821x_program_udma - program the UDMA registers | |
127 | * @drive: drive to tune | |
0e9b4e53 | 128 | * @timing: timing info |
da9091ee AC |
129 | * |
130 | * Program the UDMA timing for this drive according to the | |
131 | * current clock. | |
132 | */ | |
133 | ||
134 | static void it821x_program_udma(ide_drive_t *drive, u16 timing) | |
135 | { | |
36501650 BZ |
136 | ide_hwif_t *hwif = drive->hwif; |
137 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
138 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
139 | int channel = hwif->channel; | |
140 | int unit = drive->select.b.unit; | |
141 | u8 conf; | |
142 | ||
143 | /* Program UDMA timing bits */ | |
144 | if(itdev->clock_mode == ATA_66) | |
145 | conf = timing >> 8; | |
146 | else | |
147 | conf = timing & 0xFF; | |
36501650 BZ |
148 | |
149 | if (itdev->timing10 == 0) | |
150 | pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf); | |
da9091ee | 151 | else { |
36501650 BZ |
152 | pci_write_config_byte(dev, 0x56 + 4 * channel, conf); |
153 | pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf); | |
da9091ee AC |
154 | } |
155 | } | |
156 | ||
da9091ee AC |
157 | /** |
158 | * it821x_clock_strategy | |
0e9b4e53 | 159 | * @drive: drive to set up |
da9091ee AC |
160 | * |
161 | * Select between the 50 and 66Mhz base clocks to get the best | |
162 | * results for this interface. | |
163 | */ | |
164 | ||
165 | static void it821x_clock_strategy(ide_drive_t *drive) | |
166 | { | |
167 | ide_hwif_t *hwif = drive->hwif; | |
36501650 | 168 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
da9091ee AC |
169 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
170 | ||
171 | u8 unit = drive->select.b.unit; | |
172 | ide_drive_t *pair = &hwif->drives[1-unit]; | |
173 | ||
174 | int clock, altclock; | |
175 | u8 v; | |
176 | int sel = 0; | |
177 | ||
178 | if(itdev->want[0][0] > itdev->want[1][0]) { | |
179 | clock = itdev->want[0][1]; | |
180 | altclock = itdev->want[1][1]; | |
181 | } else { | |
182 | clock = itdev->want[1][1]; | |
183 | altclock = itdev->want[0][1]; | |
184 | } | |
185 | ||
0e9b4e53 BZ |
186 | /* |
187 | * if both clocks can be used for the mode with the higher priority | |
188 | * use the clock needed by the mode with the lower priority | |
189 | */ | |
190 | if (clock == ATA_ANY) | |
da9091ee AC |
191 | clock = altclock; |
192 | ||
193 | /* Nobody cares - keep the same clock */ | |
194 | if(clock == ATA_ANY) | |
195 | return; | |
196 | /* No change */ | |
197 | if(clock == itdev->clock_mode) | |
198 | return; | |
199 | ||
200 | /* Load this into the controller ? */ | |
201 | if(clock == ATA_66) | |
202 | itdev->clock_mode = ATA_66; | |
203 | else { | |
204 | itdev->clock_mode = ATA_50; | |
205 | sel = 1; | |
206 | } | |
36501650 BZ |
207 | |
208 | pci_read_config_byte(dev, 0x50, &v); | |
da9091ee AC |
209 | v &= ~(1 << (1 + hwif->channel)); |
210 | v |= sel << (1 + hwif->channel); | |
36501650 | 211 | pci_write_config_byte(dev, 0x50, v); |
da9091ee AC |
212 | |
213 | /* | |
214 | * Reprogram the UDMA/PIO of the pair drive for the switch | |
215 | * MWDMA will be dealt with by the dma switcher | |
216 | */ | |
217 | if(pair && itdev->udma[1-unit] != UDMA_OFF) { | |
218 | it821x_program_udma(pair, itdev->udma[1-unit]); | |
219 | it821x_program(pair, itdev->pio[1-unit]); | |
220 | } | |
221 | /* | |
222 | * Reprogram the UDMA/PIO of our drive for the switch. | |
223 | * MWDMA will be dealt with by the dma switcher | |
224 | */ | |
225 | if(itdev->udma[unit] != UDMA_OFF) { | |
226 | it821x_program_udma(drive, itdev->udma[unit]); | |
227 | it821x_program(drive, itdev->pio[unit]); | |
228 | } | |
229 | } | |
230 | ||
da9091ee | 231 | /** |
88b2b32b BZ |
232 | * it821x_set_pio_mode - set host controller for PIO mode |
233 | * @drive: drive | |
234 | * @pio: PIO mode number | |
da9091ee | 235 | * |
88b2b32b BZ |
236 | * Tune the host to the desired PIO mode taking into the consideration |
237 | * the maximum PIO mode supported by the other device on the cable. | |
da9091ee AC |
238 | */ |
239 | ||
88b2b32b | 240 | static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio) |
da9091ee AC |
241 | { |
242 | ide_hwif_t *hwif = drive->hwif; | |
243 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); | |
244 | int unit = drive->select.b.unit; | |
0e9b4e53 | 245 | ide_drive_t *pair = &hwif->drives[1 - unit]; |
88b2b32b | 246 | u8 set_pio = pio; |
da9091ee AC |
247 | |
248 | /* Spec says 89 ref driver uses 88 */ | |
88b2b32b | 249 | static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; |
da9091ee AC |
250 | static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; |
251 | ||
0e9b4e53 BZ |
252 | /* |
253 | * Compute the best PIO mode we can for a given device. We must | |
254 | * pick a speed that does not cause problems with the other device | |
255 | * on the cable. | |
256 | */ | |
257 | if (pair) { | |
2134758d | 258 | u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); |
0e9b4e53 BZ |
259 | /* trim PIO to the slowest of the master/slave */ |
260 | if (pair_pio < set_pio) | |
261 | set_pio = pair_pio; | |
262 | } | |
263 | ||
da9091ee | 264 | /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ |
0e9b4e53 | 265 | itdev->want[unit][1] = pio_want[set_pio]; |
da9091ee | 266 | itdev->want[unit][0] = 1; /* PIO is lowest priority */ |
88b2b32b | 267 | itdev->pio[unit] = pio_timings[set_pio]; |
da9091ee AC |
268 | it821x_clock_strategy(drive); |
269 | it821x_program(drive, itdev->pio[unit]); | |
270 | } | |
271 | ||
272 | /** | |
273 | * it821x_tune_mwdma - tune a channel for MWDMA | |
274 | * @drive: drive to set up | |
275 | * @mode_wanted: the target operating mode | |
276 | * | |
277 | * Load the timing settings for this device mode into the | |
278 | * controller when doing MWDMA in pass through mode. The caller | |
279 | * must manage the whole lack of per device MWDMA/PIO timings and | |
280 | * the shared MWDMA/PIO timing register. | |
281 | */ | |
282 | ||
283 | static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted) | |
284 | { | |
36501650 BZ |
285 | ide_hwif_t *hwif = drive->hwif; |
286 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
287 | struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif); |
288 | int unit = drive->select.b.unit; | |
289 | int channel = hwif->channel; | |
290 | u8 conf; | |
291 | ||
292 | static u16 dma[] = { 0x8866, 0x3222, 0x3121 }; | |
293 | static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY }; | |
294 | ||
295 | itdev->want[unit][1] = mwdma_want[mode_wanted]; | |
296 | itdev->want[unit][0] = 2; /* MWDMA is low priority */ | |
297 | itdev->mwdma[unit] = dma[mode_wanted]; | |
298 | itdev->udma[unit] = UDMA_OFF; | |
299 | ||
300 | /* UDMA bits off - Revision 0x10 do them in pairs */ | |
36501650 BZ |
301 | pci_read_config_byte(dev, 0x50, &conf); |
302 | if (itdev->timing10) | |
da9091ee AC |
303 | conf |= channel ? 0x60: 0x18; |
304 | else | |
305 | conf |= 1 << (3 + 2 * channel + unit); | |
36501650 | 306 | pci_write_config_byte(dev, 0x50, conf); |
da9091ee AC |
307 | |
308 | it821x_clock_strategy(drive); | |
309 | /* FIXME: do we need to program this ? */ | |
310 | /* it821x_program(drive, itdev->mwdma[unit]); */ | |
311 | } | |
312 | ||
313 | /** | |
314 | * it821x_tune_udma - tune a channel for UDMA | |
315 | * @drive: drive to set up | |
316 | * @mode_wanted: the target operating mode | |
317 | * | |
318 | * Load the timing settings for this device mode into the | |
319 | * controller when doing UDMA modes in pass through. | |
320 | */ | |
321 | ||
322 | static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted) | |
323 | { | |
36501650 BZ |
324 | ide_hwif_t *hwif = drive->hwif; |
325 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
326 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
327 | int unit = drive->select.b.unit; | |
328 | int channel = hwif->channel; | |
329 | u8 conf; | |
330 | ||
331 | static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 }; | |
332 | static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 }; | |
333 | ||
334 | itdev->want[unit][1] = udma_want[mode_wanted]; | |
335 | itdev->want[unit][0] = 3; /* UDMA is high priority */ | |
336 | itdev->mwdma[unit] = MWDMA_OFF; | |
337 | itdev->udma[unit] = udma[mode_wanted]; | |
338 | if(mode_wanted >= 5) | |
339 | itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */ | |
340 | ||
341 | /* UDMA on. Again revision 0x10 must do the pair */ | |
36501650 BZ |
342 | pci_read_config_byte(dev, 0x50, &conf); |
343 | if (itdev->timing10) | |
da9091ee AC |
344 | conf &= channel ? 0x9F: 0xE7; |
345 | else | |
346 | conf &= ~ (1 << (3 + 2 * channel + unit)); | |
36501650 | 347 | pci_write_config_byte(dev, 0x50, conf); |
da9091ee AC |
348 | |
349 | it821x_clock_strategy(drive); | |
350 | it821x_program_udma(drive, itdev->udma[unit]); | |
351 | ||
352 | } | |
353 | ||
da9091ee AC |
354 | /** |
355 | * it821x_dma_read - DMA hook | |
356 | * @drive: drive for DMA | |
357 | * | |
358 | * The IT821x has a single timing register for MWDMA and for PIO | |
359 | * operations. As we flip back and forth we have to reload the | |
360 | * clock. In addition the rev 0x10 device only works if the same | |
361 | * timing value is loaded into the master and slave UDMA clock | |
362 | * so we must also reload that. | |
363 | * | |
364 | * FIXME: we could figure out in advance if we need to do reloads | |
365 | */ | |
366 | ||
367 | static void it821x_dma_start(ide_drive_t *drive) | |
368 | { | |
369 | ide_hwif_t *hwif = drive->hwif; | |
370 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); | |
371 | int unit = drive->select.b.unit; | |
372 | if(itdev->mwdma[unit] != MWDMA_OFF) | |
373 | it821x_program(drive, itdev->mwdma[unit]); | |
374 | else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10) | |
375 | it821x_program_udma(drive, itdev->udma[unit]); | |
376 | ide_dma_start(drive); | |
377 | } | |
378 | ||
379 | /** | |
380 | * it821x_dma_write - DMA hook | |
381 | * @drive: drive for DMA stop | |
382 | * | |
383 | * The IT821x has a single timing register for MWDMA and for PIO | |
384 | * operations. As we flip back and forth we have to reload the | |
385 | * clock. | |
386 | */ | |
387 | ||
388 | static int it821x_dma_end(ide_drive_t *drive) | |
389 | { | |
390 | ide_hwif_t *hwif = drive->hwif; | |
391 | int unit = drive->select.b.unit; | |
392 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); | |
393 | int ret = __ide_dma_end(drive); | |
394 | if(itdev->mwdma[unit] != MWDMA_OFF) | |
395 | it821x_program(drive, itdev->pio[unit]); | |
396 | return ret; | |
397 | } | |
398 | ||
da9091ee | 399 | /** |
88b2b32b BZ |
400 | * it821x_set_dma_mode - set host controller for DMA mode |
401 | * @drive: drive | |
402 | * @speed: DMA mode | |
da9091ee | 403 | * |
88b2b32b | 404 | * Tune the ITE chipset for the desired DMA mode. |
da9091ee AC |
405 | */ |
406 | ||
88b2b32b | 407 | static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed) |
da9091ee | 408 | { |
88b2b32b BZ |
409 | /* |
410 | * MWDMA tuning is really hard because our MWDMA and PIO | |
411 | * timings are kept in the same place. We can switch in the | |
412 | * host dma on/off callbacks. | |
413 | */ | |
414 | if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6) | |
415 | it821x_tune_udma(drive, speed - XFER_UDMA_0); | |
416 | else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) | |
417 | it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0); | |
da9091ee AC |
418 | } |
419 | ||
da9091ee | 420 | /** |
ac95beed | 421 | * it821x_cable_detect - cable detection |
da9091ee AC |
422 | * @hwif: interface to check |
423 | * | |
424 | * Check for the presence of an ATA66 capable cable on the | |
425 | * interface. Problematic as it seems some cards don't have | |
426 | * the needed logic onboard. | |
427 | */ | |
428 | ||
ac95beed | 429 | static u8 __devinit it821x_cable_detect(ide_hwif_t *hwif) |
da9091ee AC |
430 | { |
431 | /* The reference driver also only does disk side */ | |
49521f97 | 432 | return ATA_CBL_PATA80; |
da9091ee AC |
433 | } |
434 | ||
435 | /** | |
f01393e4 BZ |
436 | * it821x_quirkproc - post init callback |
437 | * @drive: drive | |
da9091ee | 438 | * |
f01393e4 | 439 | * This callback is run after the drive has been probed but |
da9091ee AC |
440 | * before anything gets attached. It allows drivers to do any |
441 | * final tuning that is needed, or fixups to work around bugs. | |
442 | */ | |
443 | ||
f01393e4 | 444 | static void __devinit it821x_quirkproc(ide_drive_t *drive) |
da9091ee | 445 | { |
f01393e4 BZ |
446 | struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif); |
447 | struct hd_driveid *id = drive->id; | |
448 | u16 *idbits = (u16 *)drive->id; | |
da9091ee | 449 | |
f01393e4 | 450 | if (!itdev->smart) { |
da9091ee AC |
451 | /* |
452 | * If we are in pass through mode then not much | |
453 | * needs to be done, but we do bother to clear the | |
454 | * IRQ mask as we may well be in PIO (eg rev 0x10) | |
455 | * for now and we know unmasking is safe on this chipset. | |
456 | */ | |
f01393e4 BZ |
457 | drive->unmask = 1; |
458 | } else { | |
da9091ee AC |
459 | /* |
460 | * Perform fixups on smart mode. We need to "lose" some | |
461 | * capabilities the firmware lacks but does not filter, and | |
462 | * also patch up some capability bits that it forgets to set | |
463 | * in RAID mode. | |
464 | */ | |
465 | ||
da9091ee AC |
466 | /* Check for RAID v native */ |
467 | if(strstr(id->model, "Integrated Technology Express")) { | |
468 | /* In raid mode the ident block is slightly buggy | |
469 | We need to set the bits so that the IDE layer knows | |
470 | LBA28. LBA48 and DMA ar valid */ | |
471 | id->capability |= 3; /* LBA28, DMA */ | |
472 | id->command_set_2 |= 0x0400; /* LBA48 valid */ | |
473 | id->cfs_enable_2 |= 0x0400; /* LBA48 on */ | |
474 | /* Reporting logic */ | |
475 | printk(KERN_INFO "%s: IT8212 %sRAID %d volume", | |
476 | drive->name, | |
477 | idbits[147] ? "Bootable ":"", | |
478 | idbits[129]); | |
479 | if(idbits[129] != 1) | |
480 | printk("(%dK stripe)", idbits[146]); | |
481 | printk(".\n"); | |
da9091ee AC |
482 | } else { |
483 | /* Non RAID volume. Fixups to stop the core code | |
484 | doing unsupported things */ | |
0380dad4 | 485 | id->field_valid &= 3; |
da9091ee AC |
486 | id->queue_depth = 0; |
487 | id->command_set_1 = 0; | |
488 | id->command_set_2 &= 0xC400; | |
489 | id->cfsse &= 0xC000; | |
490 | id->cfs_enable_1 = 0; | |
491 | id->cfs_enable_2 &= 0xC400; | |
492 | id->csf_default &= 0xC000; | |
493 | id->word127 = 0; | |
494 | id->dlf = 0; | |
495 | id->csfo = 0; | |
496 | id->cfa_power = 0; | |
497 | printk(KERN_INFO "%s: Performing identify fixups.\n", | |
498 | drive->name); | |
499 | } | |
0380dad4 BZ |
500 | |
501 | /* | |
502 | * Set MWDMA0 mode as enabled/support - just to tell | |
503 | * IDE core that DMA is supported (it821x hardware | |
504 | * takes care of DMA mode programming). | |
505 | */ | |
506 | if (id->capability & 1) { | |
507 | id->dma_mword |= 0x0101; | |
508 | drive->current_speed = XFER_MW_DMA_0; | |
509 | } | |
da9091ee AC |
510 | } |
511 | ||
512 | } | |
513 | ||
5e37bdc0 | 514 | static struct ide_dma_ops it821x_pass_through_dma_ops = { |
84e0f3f6 DG |
515 | .dma_host_set = ide_dma_host_set, |
516 | .dma_setup = ide_dma_setup, | |
517 | .dma_exec_cmd = ide_dma_exec_cmd, | |
5e37bdc0 BZ |
518 | .dma_start = it821x_dma_start, |
519 | .dma_end = it821x_dma_end, | |
84e0f3f6 DG |
520 | .dma_test_irq = ide_dma_test_irq, |
521 | .dma_timeout = ide_dma_timeout, | |
522 | .dma_lost_irq = ide_dma_lost_irq, | |
5e37bdc0 BZ |
523 | }; |
524 | ||
da9091ee AC |
525 | /** |
526 | * init_hwif_it821x - set up hwif structs | |
527 | * @hwif: interface to set up | |
528 | * | |
529 | * We do the basic set up of the interface structure. The IT8212 | |
530 | * requires several custom handlers so we override the default | |
531 | * ide DMA handlers appropriately | |
532 | */ | |
533 | ||
534 | static void __devinit init_hwif_it821x(ide_hwif_t *hwif) | |
535 | { | |
36501650 | 536 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
eb7a07e8 BZ |
537 | struct it821x_dev **itdevs = (struct it821x_dev **)pci_get_drvdata(dev); |
538 | struct it821x_dev *idev = itdevs[hwif->channel]; | |
da9091ee AC |
539 | u8 conf; |
540 | ||
da9091ee AC |
541 | ide_set_hwifdata(hwif, idev); |
542 | ||
36501650 | 543 | pci_read_config_byte(dev, 0x50, &conf); |
33c1002e | 544 | if (conf & 1) { |
da9091ee | 545 | idev->smart = 1; |
33c1002e | 546 | hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
da9091ee AC |
547 | /* Long I/O's although allowed in LBA48 space cause the |
548 | onboard firmware to enter the twighlight zone */ | |
549 | hwif->rqsize = 256; | |
550 | } | |
551 | ||
552 | /* Pull the current clocks from 0x50 also */ | |
553 | if (conf & (1 << (1 + hwif->channel))) | |
554 | idev->clock_mode = ATA_50; | |
555 | else | |
556 | idev->clock_mode = ATA_66; | |
557 | ||
558 | idev->want[0][1] = ATA_ANY; | |
559 | idev->want[1][1] = ATA_ANY; | |
560 | ||
561 | /* | |
562 | * Not in the docs but according to the reference driver | |
3a4fa0a2 | 563 | * this is necessary. |
da9091ee AC |
564 | */ |
565 | ||
36501650 | 566 | pci_read_config_byte(dev, 0x08, &conf); |
33c1002e | 567 | if (conf == 0x10) { |
da9091ee | 568 | idev->timing10 = 1; |
33c1002e BZ |
569 | hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
570 | if (idev->smart == 0) | |
da9091ee AC |
571 | printk(KERN_WARNING "it821x: Revision 0x10, workarounds activated.\n"); |
572 | } | |
573 | ||
88b2b32b | 574 | if (idev->smart == 0) { |
88b2b32b | 575 | /* MWDMA/PIO clock switching for pass through mode */ |
5e37bdc0 | 576 | hwif->dma_ops = &it821x_pass_through_dma_ops; |
88b2b32b BZ |
577 | } else |
578 | hwif->host_flags |= IDE_HFLAG_NO_SET_MODE; | |
da9091ee | 579 | |
9ff6f72f BZ |
580 | if (hwif->dma_base == 0) |
581 | return; | |
da9091ee | 582 | |
5f8b6c34 BZ |
583 | hwif->ultra_mask = ATA_UDMA6; |
584 | hwif->mwdma_mask = ATA_MWDMA2; | |
da9091ee AC |
585 | } |
586 | ||
587 | static void __devinit it8212_disable_raid(struct pci_dev *dev) | |
588 | { | |
589 | /* Reset local CPU, and set BIOS not ready */ | |
590 | pci_write_config_byte(dev, 0x5E, 0x01); | |
591 | ||
592 | /* Set to bypass mode, and reset PCI bus */ | |
593 | pci_write_config_byte(dev, 0x50, 0x00); | |
594 | pci_write_config_word(dev, PCI_COMMAND, | |
595 | PCI_COMMAND_PARITY | PCI_COMMAND_IO | | |
596 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
597 | pci_write_config_word(dev, 0x40, 0xA0F3); | |
598 | ||
599 | pci_write_config_dword(dev,0x4C, 0x02040204); | |
600 | pci_write_config_byte(dev, 0x42, 0x36); | |
0c866b51 | 601 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); |
da9091ee AC |
602 | } |
603 | ||
604 | static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev, const char *name) | |
605 | { | |
606 | u8 conf; | |
607 | static char *mode[2] = { "pass through", "smart" }; | |
608 | ||
609 | /* Force the card into bypass mode if so requested */ | |
610 | if (it8212_noraid) { | |
611 | printk(KERN_INFO "it8212: forcing bypass mode.\n"); | |
612 | it8212_disable_raid(dev); | |
613 | } | |
614 | pci_read_config_byte(dev, 0x50, &conf); | |
615 | printk(KERN_INFO "it821x: controller in %s mode.\n", mode[conf & 1]); | |
616 | return 0; | |
617 | } | |
618 | ||
ac95beed BZ |
619 | static const struct ide_port_ops it821x_port_ops = { |
620 | /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */ | |
621 | .set_pio_mode = it821x_set_pio_mode, | |
622 | .set_dma_mode = it821x_set_dma_mode, | |
623 | .quirkproc = it821x_quirkproc, | |
624 | .cable_detect = it821x_cable_detect, | |
625 | }; | |
da9091ee AC |
626 | |
627 | #define DECLARE_ITE_DEV(name_str) \ | |
628 | { \ | |
629 | .name = name_str, \ | |
630 | .init_chipset = init_chipset_it821x, \ | |
631 | .init_hwif = init_hwif_it821x, \ | |
ac95beed | 632 | .port_ops = &it821x_port_ops, \ |
4099d143 | 633 | .pio_mask = ATA_PIO4, \ |
da9091ee AC |
634 | } |
635 | ||
85620436 | 636 | static const struct ide_port_info it821x_chipsets[] __devinitdata = { |
da9091ee AC |
637 | /* 0 */ DECLARE_ITE_DEV("IT8212"), |
638 | }; | |
639 | ||
640 | /** | |
641 | * it821x_init_one - pci layer discovery entry | |
642 | * @dev: PCI device | |
643 | * @id: ident table entry | |
644 | * | |
645 | * Called by the PCI code when it finds an ITE821x controller. | |
646 | * We then use the IDE PCI generic helper to do most of the work. | |
647 | */ | |
648 | ||
649 | static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
650 | { | |
eb7a07e8 BZ |
651 | struct it821x_dev *itdevs[2] = { NULL, NULL} , *itdev; |
652 | unsigned int i; | |
653 | ||
654 | for (i = 0; i < 2; i++) { | |
655 | itdev = kzalloc(sizeof(*itdev), GFP_KERNEL); | |
656 | if (itdev == NULL) { | |
657 | kfree(itdevs[0]); | |
658 | printk(KERN_ERR "it821x: out of memory\n"); | |
659 | return -ENOMEM; | |
660 | } | |
661 | ||
662 | itdevs[i] = itdev; | |
663 | } | |
664 | ||
665 | pci_set_drvdata(dev, itdevs); | |
666 | ||
6cdf6eb3 | 667 | return ide_pci_init_one(dev, &it821x_chipsets[id->driver_data], NULL); |
da9091ee AC |
668 | } |
669 | ||
9cbcc5e3 BZ |
670 | static const struct pci_device_id it821x_pci_tbl[] = { |
671 | { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 }, | |
672 | { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 }, | |
da9091ee AC |
673 | { 0, }, |
674 | }; | |
675 | ||
676 | MODULE_DEVICE_TABLE(pci, it821x_pci_tbl); | |
677 | ||
678 | static struct pci_driver driver = { | |
679 | .name = "ITE821x IDE", | |
680 | .id_table = it821x_pci_tbl, | |
681 | .probe = it821x_init_one, | |
682 | }; | |
683 | ||
684 | static int __init it821x_ide_init(void) | |
685 | { | |
686 | return ide_pci_register_driver(&driver); | |
687 | } | |
688 | ||
689 | module_init(it821x_ide_init); | |
690 | ||
691 | module_param_named(noraid, it8212_noraid, int, S_IRUGO); | |
da195665 | 692 | MODULE_PARM_DESC(noraid, "Force card into bypass mode"); |
da9091ee AC |
693 | |
694 | MODULE_AUTHOR("Alan Cox"); | |
695 | MODULE_DESCRIPTION("PCI driver module for the ITE 821x"); | |
696 | MODULE_LICENSE("GPL"); |