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da9091ee | 1 | /* |
da9091ee | 2 | * Copyright (C) 2004 Red Hat <alan@redhat.com> |
0e9b4e53 | 3 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
da9091ee AC |
4 | * |
5 | * May be copied or modified under the terms of the GNU General Public License | |
6 | * Based in part on the ITE vendor provided SCSI driver. | |
7 | * | |
8 | * Documentation available from | |
9 | * http://www.ite.com.tw/pc/IT8212F_V04.pdf | |
10 | * Some other documents are NDA. | |
11 | * | |
12 | * The ITE8212 isn't exactly a standard IDE controller. It has two | |
13 | * modes. In pass through mode then it is an IDE controller. In its smart | |
14 | * mode its actually quite a capable hardware raid controller disguised | |
15 | * as an IDE controller. Smart mode only understands DMA read/write and | |
16 | * identify, none of the fancier commands apply. The IT8211 is identical | |
17 | * in other respects but lacks the raid mode. | |
18 | * | |
19 | * Errata: | |
20 | * o Rev 0x10 also requires master/slave hold the same DMA timings and | |
21 | * cannot do ATAPI MWDMA. | |
22 | * o The identify data for raid volumes lacks CHS info (technically ok) | |
23 | * but also fails to set the LBA28 and other bits. We fix these in | |
24 | * the IDE probe quirk code. | |
25 | * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode | |
26 | * raid then the controller firmware dies | |
27 | * o Smart mode without RAID doesn't clear all the necessary identify | |
28 | * bits to reduce the command set to the one used | |
29 | * | |
30 | * This has a few impacts on the driver | |
31 | * - In pass through mode we do all the work you would expect | |
32 | * - In smart mode the clocking set up is done by the controller generally | |
33 | * but we must watch the other limits and filter. | |
34 | * - There are a few extra vendor commands that actually talk to the | |
35 | * controller but only work PIO with no IRQ. | |
36 | * | |
37 | * Vendor areas of the identify block in smart mode are used for the | |
38 | * timing and policy set up. Each HDD in raid mode also has a serial | |
39 | * block on the disk. The hardware extra commands are get/set chip status, | |
40 | * rebuild, get rebuild status. | |
41 | * | |
42 | * In Linux the driver supports pass through mode as if the device was | |
43 | * just another IDE controller. If the smart mode is running then | |
44 | * volumes are managed by the controller firmware and each IDE "disk" | |
45 | * is a raid volume. Even more cute - the controller can do automated | |
46 | * hotplug and rebuild. | |
47 | * | |
48 | * The pass through controller itself is a little demented. It has a | |
49 | * flaw that it has a single set of PIO/MWDMA timings per channel so | |
50 | * non UDMA devices restrict each others performance. It also has a | |
51 | * single clock source per channel so mixed UDMA100/133 performance | |
52 | * isn't perfect and we have to pick a clock. Thankfully none of this | |
53 | * matters in smart mode. ATAPI DMA is not currently supported. | |
54 | * | |
55 | * It seems the smart mode is a win for RAID1/RAID10 but otherwise not. | |
56 | * | |
57 | * TODO | |
58 | * - ATAPI UDMA is ok but not MWDMA it seems | |
59 | * - RAID configuration ioctls | |
60 | * - Move to libata once it grows up | |
61 | */ | |
62 | ||
da9091ee AC |
63 | #include <linux/types.h> |
64 | #include <linux/module.h> | |
65 | #include <linux/pci.h> | |
da9091ee AC |
66 | #include <linux/ide.h> |
67 | #include <linux/init.h> | |
68 | ||
ced3ec8a BZ |
69 | #define DRV_NAME "it821x" |
70 | ||
da9091ee AC |
71 | struct it821x_dev |
72 | { | |
73 | unsigned int smart:1, /* Are we in smart raid mode */ | |
74 | timing10:1; /* Rev 0x10 */ | |
75 | u8 clock_mode; /* 0, ATA_50 or ATA_66 */ | |
76 | u8 want[2][2]; /* Mode/Pri log for master slave */ | |
77 | /* We need these for switching the clock when DMA goes on/off | |
78 | The high byte is the 66Mhz timing */ | |
79 | u16 pio[2]; /* Cached PIO values */ | |
80 | u16 mwdma[2]; /* Cached MWDMA values */ | |
81 | u16 udma[2]; /* Cached UDMA values (per drive) */ | |
82 | }; | |
83 | ||
84 | #define ATA_66 0 | |
85 | #define ATA_50 1 | |
86 | #define ATA_ANY 2 | |
87 | ||
88 | #define UDMA_OFF 0 | |
89 | #define MWDMA_OFF 0 | |
90 | ||
91 | /* | |
92 | * We allow users to force the card into non raid mode without | |
3a4fa0a2 | 93 | * flashing the alternative BIOS. This is also necessary right now |
da9091ee AC |
94 | * for embedded platforms that cannot run a PC BIOS but are using this |
95 | * device. | |
96 | */ | |
97 | ||
98 | static int it8212_noraid; | |
99 | ||
100 | /** | |
101 | * it821x_program - program the PIO/MWDMA registers | |
102 | * @drive: drive to tune | |
0e9b4e53 | 103 | * @timing: timing info |
da9091ee AC |
104 | * |
105 | * Program the PIO/MWDMA timing for this channel according to the | |
106 | * current clock. | |
107 | */ | |
108 | ||
109 | static void it821x_program(ide_drive_t *drive, u16 timing) | |
110 | { | |
36501650 BZ |
111 | ide_hwif_t *hwif = drive->hwif; |
112 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
113 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
114 | int channel = hwif->channel; | |
115 | u8 conf; | |
116 | ||
117 | /* Program PIO/MWDMA timing bits */ | |
118 | if(itdev->clock_mode == ATA_66) | |
119 | conf = timing >> 8; | |
120 | else | |
121 | conf = timing & 0xFF; | |
36501650 BZ |
122 | |
123 | pci_write_config_byte(dev, 0x54 + 4 * channel, conf); | |
da9091ee AC |
124 | } |
125 | ||
126 | /** | |
127 | * it821x_program_udma - program the UDMA registers | |
128 | * @drive: drive to tune | |
0e9b4e53 | 129 | * @timing: timing info |
da9091ee AC |
130 | * |
131 | * Program the UDMA timing for this drive according to the | |
132 | * current clock. | |
133 | */ | |
134 | ||
135 | static void it821x_program_udma(ide_drive_t *drive, u16 timing) | |
136 | { | |
36501650 BZ |
137 | ide_hwif_t *hwif = drive->hwif; |
138 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
139 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
140 | int channel = hwif->channel; | |
141 | int unit = drive->select.b.unit; | |
142 | u8 conf; | |
143 | ||
144 | /* Program UDMA timing bits */ | |
145 | if(itdev->clock_mode == ATA_66) | |
146 | conf = timing >> 8; | |
147 | else | |
148 | conf = timing & 0xFF; | |
36501650 BZ |
149 | |
150 | if (itdev->timing10 == 0) | |
151 | pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf); | |
da9091ee | 152 | else { |
36501650 BZ |
153 | pci_write_config_byte(dev, 0x56 + 4 * channel, conf); |
154 | pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf); | |
da9091ee AC |
155 | } |
156 | } | |
157 | ||
da9091ee AC |
158 | /** |
159 | * it821x_clock_strategy | |
0e9b4e53 | 160 | * @drive: drive to set up |
da9091ee AC |
161 | * |
162 | * Select between the 50 and 66Mhz base clocks to get the best | |
163 | * results for this interface. | |
164 | */ | |
165 | ||
166 | static void it821x_clock_strategy(ide_drive_t *drive) | |
167 | { | |
168 | ide_hwif_t *hwif = drive->hwif; | |
36501650 | 169 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
da9091ee AC |
170 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
171 | ||
172 | u8 unit = drive->select.b.unit; | |
173 | ide_drive_t *pair = &hwif->drives[1-unit]; | |
174 | ||
175 | int clock, altclock; | |
176 | u8 v; | |
177 | int sel = 0; | |
178 | ||
179 | if(itdev->want[0][0] > itdev->want[1][0]) { | |
180 | clock = itdev->want[0][1]; | |
181 | altclock = itdev->want[1][1]; | |
182 | } else { | |
183 | clock = itdev->want[1][1]; | |
184 | altclock = itdev->want[0][1]; | |
185 | } | |
186 | ||
0e9b4e53 BZ |
187 | /* |
188 | * if both clocks can be used for the mode with the higher priority | |
189 | * use the clock needed by the mode with the lower priority | |
190 | */ | |
191 | if (clock == ATA_ANY) | |
da9091ee AC |
192 | clock = altclock; |
193 | ||
194 | /* Nobody cares - keep the same clock */ | |
195 | if(clock == ATA_ANY) | |
196 | return; | |
197 | /* No change */ | |
198 | if(clock == itdev->clock_mode) | |
199 | return; | |
200 | ||
201 | /* Load this into the controller ? */ | |
202 | if(clock == ATA_66) | |
203 | itdev->clock_mode = ATA_66; | |
204 | else { | |
205 | itdev->clock_mode = ATA_50; | |
206 | sel = 1; | |
207 | } | |
36501650 BZ |
208 | |
209 | pci_read_config_byte(dev, 0x50, &v); | |
da9091ee AC |
210 | v &= ~(1 << (1 + hwif->channel)); |
211 | v |= sel << (1 + hwif->channel); | |
36501650 | 212 | pci_write_config_byte(dev, 0x50, v); |
da9091ee AC |
213 | |
214 | /* | |
215 | * Reprogram the UDMA/PIO of the pair drive for the switch | |
216 | * MWDMA will be dealt with by the dma switcher | |
217 | */ | |
218 | if(pair && itdev->udma[1-unit] != UDMA_OFF) { | |
219 | it821x_program_udma(pair, itdev->udma[1-unit]); | |
220 | it821x_program(pair, itdev->pio[1-unit]); | |
221 | } | |
222 | /* | |
223 | * Reprogram the UDMA/PIO of our drive for the switch. | |
224 | * MWDMA will be dealt with by the dma switcher | |
225 | */ | |
226 | if(itdev->udma[unit] != UDMA_OFF) { | |
227 | it821x_program_udma(drive, itdev->udma[unit]); | |
228 | it821x_program(drive, itdev->pio[unit]); | |
229 | } | |
230 | } | |
231 | ||
da9091ee | 232 | /** |
88b2b32b BZ |
233 | * it821x_set_pio_mode - set host controller for PIO mode |
234 | * @drive: drive | |
235 | * @pio: PIO mode number | |
da9091ee | 236 | * |
88b2b32b BZ |
237 | * Tune the host to the desired PIO mode taking into the consideration |
238 | * the maximum PIO mode supported by the other device on the cable. | |
da9091ee AC |
239 | */ |
240 | ||
88b2b32b | 241 | static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio) |
da9091ee AC |
242 | { |
243 | ide_hwif_t *hwif = drive->hwif; | |
244 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); | |
245 | int unit = drive->select.b.unit; | |
0e9b4e53 | 246 | ide_drive_t *pair = &hwif->drives[1 - unit]; |
88b2b32b | 247 | u8 set_pio = pio; |
da9091ee AC |
248 | |
249 | /* Spec says 89 ref driver uses 88 */ | |
88b2b32b | 250 | static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; |
da9091ee AC |
251 | static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; |
252 | ||
0e9b4e53 BZ |
253 | /* |
254 | * Compute the best PIO mode we can for a given device. We must | |
255 | * pick a speed that does not cause problems with the other device | |
256 | * on the cable. | |
257 | */ | |
258 | if (pair) { | |
2134758d | 259 | u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); |
0e9b4e53 BZ |
260 | /* trim PIO to the slowest of the master/slave */ |
261 | if (pair_pio < set_pio) | |
262 | set_pio = pair_pio; | |
263 | } | |
264 | ||
da9091ee | 265 | /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ |
0e9b4e53 | 266 | itdev->want[unit][1] = pio_want[set_pio]; |
da9091ee | 267 | itdev->want[unit][0] = 1; /* PIO is lowest priority */ |
88b2b32b | 268 | itdev->pio[unit] = pio_timings[set_pio]; |
da9091ee AC |
269 | it821x_clock_strategy(drive); |
270 | it821x_program(drive, itdev->pio[unit]); | |
271 | } | |
272 | ||
273 | /** | |
274 | * it821x_tune_mwdma - tune a channel for MWDMA | |
275 | * @drive: drive to set up | |
276 | * @mode_wanted: the target operating mode | |
277 | * | |
278 | * Load the timing settings for this device mode into the | |
279 | * controller when doing MWDMA in pass through mode. The caller | |
280 | * must manage the whole lack of per device MWDMA/PIO timings and | |
281 | * the shared MWDMA/PIO timing register. | |
282 | */ | |
283 | ||
284 | static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted) | |
285 | { | |
36501650 BZ |
286 | ide_hwif_t *hwif = drive->hwif; |
287 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
288 | struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif); |
289 | int unit = drive->select.b.unit; | |
290 | int channel = hwif->channel; | |
291 | u8 conf; | |
292 | ||
293 | static u16 dma[] = { 0x8866, 0x3222, 0x3121 }; | |
294 | static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY }; | |
295 | ||
296 | itdev->want[unit][1] = mwdma_want[mode_wanted]; | |
297 | itdev->want[unit][0] = 2; /* MWDMA is low priority */ | |
298 | itdev->mwdma[unit] = dma[mode_wanted]; | |
299 | itdev->udma[unit] = UDMA_OFF; | |
300 | ||
301 | /* UDMA bits off - Revision 0x10 do them in pairs */ | |
36501650 BZ |
302 | pci_read_config_byte(dev, 0x50, &conf); |
303 | if (itdev->timing10) | |
da9091ee AC |
304 | conf |= channel ? 0x60: 0x18; |
305 | else | |
306 | conf |= 1 << (3 + 2 * channel + unit); | |
36501650 | 307 | pci_write_config_byte(dev, 0x50, conf); |
da9091ee AC |
308 | |
309 | it821x_clock_strategy(drive); | |
310 | /* FIXME: do we need to program this ? */ | |
311 | /* it821x_program(drive, itdev->mwdma[unit]); */ | |
312 | } | |
313 | ||
314 | /** | |
315 | * it821x_tune_udma - tune a channel for UDMA | |
316 | * @drive: drive to set up | |
317 | * @mode_wanted: the target operating mode | |
318 | * | |
319 | * Load the timing settings for this device mode into the | |
320 | * controller when doing UDMA modes in pass through. | |
321 | */ | |
322 | ||
323 | static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted) | |
324 | { | |
36501650 BZ |
325 | ide_hwif_t *hwif = drive->hwif; |
326 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
da9091ee AC |
327 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
328 | int unit = drive->select.b.unit; | |
329 | int channel = hwif->channel; | |
330 | u8 conf; | |
331 | ||
332 | static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 }; | |
333 | static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 }; | |
334 | ||
335 | itdev->want[unit][1] = udma_want[mode_wanted]; | |
336 | itdev->want[unit][0] = 3; /* UDMA is high priority */ | |
337 | itdev->mwdma[unit] = MWDMA_OFF; | |
338 | itdev->udma[unit] = udma[mode_wanted]; | |
339 | if(mode_wanted >= 5) | |
340 | itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */ | |
341 | ||
342 | /* UDMA on. Again revision 0x10 must do the pair */ | |
36501650 BZ |
343 | pci_read_config_byte(dev, 0x50, &conf); |
344 | if (itdev->timing10) | |
da9091ee AC |
345 | conf &= channel ? 0x9F: 0xE7; |
346 | else | |
347 | conf &= ~ (1 << (3 + 2 * channel + unit)); | |
36501650 | 348 | pci_write_config_byte(dev, 0x50, conf); |
da9091ee AC |
349 | |
350 | it821x_clock_strategy(drive); | |
351 | it821x_program_udma(drive, itdev->udma[unit]); | |
352 | ||
353 | } | |
354 | ||
da9091ee AC |
355 | /** |
356 | * it821x_dma_read - DMA hook | |
357 | * @drive: drive for DMA | |
358 | * | |
359 | * The IT821x has a single timing register for MWDMA and for PIO | |
360 | * operations. As we flip back and forth we have to reload the | |
361 | * clock. In addition the rev 0x10 device only works if the same | |
362 | * timing value is loaded into the master and slave UDMA clock | |
363 | * so we must also reload that. | |
364 | * | |
365 | * FIXME: we could figure out in advance if we need to do reloads | |
366 | */ | |
367 | ||
368 | static void it821x_dma_start(ide_drive_t *drive) | |
369 | { | |
370 | ide_hwif_t *hwif = drive->hwif; | |
371 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); | |
372 | int unit = drive->select.b.unit; | |
373 | if(itdev->mwdma[unit] != MWDMA_OFF) | |
374 | it821x_program(drive, itdev->mwdma[unit]); | |
375 | else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10) | |
376 | it821x_program_udma(drive, itdev->udma[unit]); | |
377 | ide_dma_start(drive); | |
378 | } | |
379 | ||
380 | /** | |
381 | * it821x_dma_write - DMA hook | |
382 | * @drive: drive for DMA stop | |
383 | * | |
384 | * The IT821x has a single timing register for MWDMA and for PIO | |
385 | * operations. As we flip back and forth we have to reload the | |
386 | * clock. | |
387 | */ | |
388 | ||
389 | static int it821x_dma_end(ide_drive_t *drive) | |
390 | { | |
391 | ide_hwif_t *hwif = drive->hwif; | |
392 | int unit = drive->select.b.unit; | |
393 | struct it821x_dev *itdev = ide_get_hwifdata(hwif); | |
394 | int ret = __ide_dma_end(drive); | |
395 | if(itdev->mwdma[unit] != MWDMA_OFF) | |
396 | it821x_program(drive, itdev->pio[unit]); | |
397 | return ret; | |
398 | } | |
399 | ||
da9091ee | 400 | /** |
88b2b32b BZ |
401 | * it821x_set_dma_mode - set host controller for DMA mode |
402 | * @drive: drive | |
403 | * @speed: DMA mode | |
da9091ee | 404 | * |
88b2b32b | 405 | * Tune the ITE chipset for the desired DMA mode. |
da9091ee AC |
406 | */ |
407 | ||
88b2b32b | 408 | static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed) |
da9091ee | 409 | { |
88b2b32b BZ |
410 | /* |
411 | * MWDMA tuning is really hard because our MWDMA and PIO | |
412 | * timings are kept in the same place. We can switch in the | |
413 | * host dma on/off callbacks. | |
414 | */ | |
415 | if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6) | |
416 | it821x_tune_udma(drive, speed - XFER_UDMA_0); | |
417 | else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) | |
418 | it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0); | |
da9091ee AC |
419 | } |
420 | ||
da9091ee | 421 | /** |
ac95beed | 422 | * it821x_cable_detect - cable detection |
da9091ee AC |
423 | * @hwif: interface to check |
424 | * | |
425 | * Check for the presence of an ATA66 capable cable on the | |
426 | * interface. Problematic as it seems some cards don't have | |
427 | * the needed logic onboard. | |
428 | */ | |
429 | ||
f454cbe8 | 430 | static u8 it821x_cable_detect(ide_hwif_t *hwif) |
da9091ee AC |
431 | { |
432 | /* The reference driver also only does disk side */ | |
49521f97 | 433 | return ATA_CBL_PATA80; |
da9091ee AC |
434 | } |
435 | ||
436 | /** | |
f01393e4 BZ |
437 | * it821x_quirkproc - post init callback |
438 | * @drive: drive | |
da9091ee | 439 | * |
f01393e4 | 440 | * This callback is run after the drive has been probed but |
da9091ee AC |
441 | * before anything gets attached. It allows drivers to do any |
442 | * final tuning that is needed, or fixups to work around bugs. | |
443 | */ | |
444 | ||
36de9948 | 445 | static void it821x_quirkproc(ide_drive_t *drive) |
da9091ee | 446 | { |
f01393e4 | 447 | struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif); |
4dde4492 | 448 | u16 *id = drive->id; |
da9091ee | 449 | |
f01393e4 | 450 | if (!itdev->smart) { |
da9091ee AC |
451 | /* |
452 | * If we are in pass through mode then not much | |
453 | * needs to be done, but we do bother to clear the | |
454 | * IRQ mask as we may well be in PIO (eg rev 0x10) | |
455 | * for now and we know unmasking is safe on this chipset. | |
456 | */ | |
f01393e4 BZ |
457 | drive->unmask = 1; |
458 | } else { | |
da9091ee AC |
459 | /* |
460 | * Perform fixups on smart mode. We need to "lose" some | |
461 | * capabilities the firmware lacks but does not filter, and | |
462 | * also patch up some capability bits that it forgets to set | |
463 | * in RAID mode. | |
464 | */ | |
465 | ||
da9091ee | 466 | /* Check for RAID v native */ |
4dde4492 BZ |
467 | if (strstr((char *)&id[ATA_ID_PROD], |
468 | "Integrated Technology Express")) { | |
da9091ee AC |
469 | /* In raid mode the ident block is slightly buggy |
470 | We need to set the bits so that the IDE layer knows | |
471 | LBA28. LBA48 and DMA ar valid */ | |
48fb2688 | 472 | id[ATA_ID_CAPABILITY] |= (3 << 8); /* LBA28, DMA */ |
4dde4492 BZ |
473 | id[ATA_ID_COMMAND_SET_2] |= 0x0400; /* LBA48 valid */ |
474 | id[ATA_ID_CFS_ENABLE_2] |= 0x0400; /* LBA48 on */ | |
da9091ee AC |
475 | /* Reporting logic */ |
476 | printk(KERN_INFO "%s: IT8212 %sRAID %d volume", | |
4dde4492 BZ |
477 | drive->name, id[147] ? "Bootable " : "", |
478 | id[ATA_ID_CSFO]); | |
479 | if (id[ATA_ID_CSFO] != 1) | |
480 | printk(KERN_CONT "(%dK stripe)", id[146]); | |
481 | printk(KERN_CONT ".\n"); | |
da9091ee AC |
482 | } else { |
483 | /* Non RAID volume. Fixups to stop the core code | |
484 | doing unsupported things */ | |
4dde4492 BZ |
485 | id[ATA_ID_FIELD_VALID] &= 3; |
486 | id[ATA_ID_QUEUE_DEPTH] = 0; | |
487 | id[ATA_ID_COMMAND_SET_1] = 0; | |
488 | id[ATA_ID_COMMAND_SET_2] &= 0xC400; | |
489 | id[ATA_ID_CFSSE] &= 0xC000; | |
490 | id[ATA_ID_CFS_ENABLE_1] = 0; | |
491 | id[ATA_ID_CFS_ENABLE_2] &= 0xC400; | |
492 | id[ATA_ID_CSF_DEFAULT] &= 0xC000; | |
493 | id[127] = 0; | |
494 | id[ATA_ID_DLF] = 0; | |
495 | id[ATA_ID_CSFO] = 0; | |
496 | id[ATA_ID_CFA_POWER] = 0; | |
da9091ee AC |
497 | printk(KERN_INFO "%s: Performing identify fixups.\n", |
498 | drive->name); | |
499 | } | |
0380dad4 BZ |
500 | |
501 | /* | |
502 | * Set MWDMA0 mode as enabled/support - just to tell | |
503 | * IDE core that DMA is supported (it821x hardware | |
504 | * takes care of DMA mode programming). | |
505 | */ | |
48fb2688 | 506 | if (ata_id_has_dma(id)) { |
4dde4492 | 507 | id[ATA_ID_MWDMA_MODES] |= 0x0101; |
0380dad4 BZ |
508 | drive->current_speed = XFER_MW_DMA_0; |
509 | } | |
da9091ee AC |
510 | } |
511 | ||
512 | } | |
513 | ||
5e37bdc0 | 514 | static struct ide_dma_ops it821x_pass_through_dma_ops = { |
84e0f3f6 DG |
515 | .dma_host_set = ide_dma_host_set, |
516 | .dma_setup = ide_dma_setup, | |
517 | .dma_exec_cmd = ide_dma_exec_cmd, | |
5e37bdc0 BZ |
518 | .dma_start = it821x_dma_start, |
519 | .dma_end = it821x_dma_end, | |
84e0f3f6 DG |
520 | .dma_test_irq = ide_dma_test_irq, |
521 | .dma_timeout = ide_dma_timeout, | |
522 | .dma_lost_irq = ide_dma_lost_irq, | |
5e37bdc0 BZ |
523 | }; |
524 | ||
da9091ee AC |
525 | /** |
526 | * init_hwif_it821x - set up hwif structs | |
527 | * @hwif: interface to set up | |
528 | * | |
529 | * We do the basic set up of the interface structure. The IT8212 | |
530 | * requires several custom handlers so we override the default | |
531 | * ide DMA handlers appropriately | |
532 | */ | |
533 | ||
534 | static void __devinit init_hwif_it821x(ide_hwif_t *hwif) | |
535 | { | |
36501650 | 536 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1d76d9dc BZ |
537 | struct ide_host *host = pci_get_drvdata(dev); |
538 | struct it821x_dev *itdevs = host->host_priv; | |
539 | struct it821x_dev *idev = itdevs + hwif->channel; | |
da9091ee AC |
540 | u8 conf; |
541 | ||
da9091ee AC |
542 | ide_set_hwifdata(hwif, idev); |
543 | ||
36501650 | 544 | pci_read_config_byte(dev, 0x50, &conf); |
33c1002e | 545 | if (conf & 1) { |
da9091ee | 546 | idev->smart = 1; |
33c1002e | 547 | hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
da9091ee AC |
548 | /* Long I/O's although allowed in LBA48 space cause the |
549 | onboard firmware to enter the twighlight zone */ | |
550 | hwif->rqsize = 256; | |
551 | } | |
552 | ||
553 | /* Pull the current clocks from 0x50 also */ | |
554 | if (conf & (1 << (1 + hwif->channel))) | |
555 | idev->clock_mode = ATA_50; | |
556 | else | |
557 | idev->clock_mode = ATA_66; | |
558 | ||
559 | idev->want[0][1] = ATA_ANY; | |
560 | idev->want[1][1] = ATA_ANY; | |
561 | ||
562 | /* | |
563 | * Not in the docs but according to the reference driver | |
3a4fa0a2 | 564 | * this is necessary. |
da9091ee AC |
565 | */ |
566 | ||
36501650 | 567 | pci_read_config_byte(dev, 0x08, &conf); |
33c1002e | 568 | if (conf == 0x10) { |
da9091ee | 569 | idev->timing10 = 1; |
33c1002e BZ |
570 | hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
571 | if (idev->smart == 0) | |
ced3ec8a | 572 | printk(KERN_WARNING DRV_NAME " %s: revision 0x10, " |
28cfd8af | 573 | "workarounds activated\n", pci_name(dev)); |
da9091ee AC |
574 | } |
575 | ||
88b2b32b | 576 | if (idev->smart == 0) { |
88b2b32b | 577 | /* MWDMA/PIO clock switching for pass through mode */ |
5e37bdc0 | 578 | hwif->dma_ops = &it821x_pass_through_dma_ops; |
88b2b32b BZ |
579 | } else |
580 | hwif->host_flags |= IDE_HFLAG_NO_SET_MODE; | |
da9091ee | 581 | |
9ff6f72f BZ |
582 | if (hwif->dma_base == 0) |
583 | return; | |
da9091ee | 584 | |
5f8b6c34 BZ |
585 | hwif->ultra_mask = ATA_UDMA6; |
586 | hwif->mwdma_mask = ATA_MWDMA2; | |
da9091ee AC |
587 | } |
588 | ||
feb22b7f | 589 | static void it8212_disable_raid(struct pci_dev *dev) |
da9091ee AC |
590 | { |
591 | /* Reset local CPU, and set BIOS not ready */ | |
592 | pci_write_config_byte(dev, 0x5E, 0x01); | |
593 | ||
594 | /* Set to bypass mode, and reset PCI bus */ | |
595 | pci_write_config_byte(dev, 0x50, 0x00); | |
596 | pci_write_config_word(dev, PCI_COMMAND, | |
597 | PCI_COMMAND_PARITY | PCI_COMMAND_IO | | |
598 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
599 | pci_write_config_word(dev, 0x40, 0xA0F3); | |
600 | ||
601 | pci_write_config_dword(dev,0x4C, 0x02040204); | |
602 | pci_write_config_byte(dev, 0x42, 0x36); | |
0c866b51 | 603 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); |
da9091ee AC |
604 | } |
605 | ||
feb22b7f | 606 | static unsigned int init_chipset_it821x(struct pci_dev *dev) |
da9091ee AC |
607 | { |
608 | u8 conf; | |
609 | static char *mode[2] = { "pass through", "smart" }; | |
610 | ||
611 | /* Force the card into bypass mode if so requested */ | |
612 | if (it8212_noraid) { | |
ced3ec8a | 613 | printk(KERN_INFO DRV_NAME " %s: forcing bypass mode\n", |
28cfd8af | 614 | pci_name(dev)); |
da9091ee AC |
615 | it8212_disable_raid(dev); |
616 | } | |
617 | pci_read_config_byte(dev, 0x50, &conf); | |
ced3ec8a | 618 | printk(KERN_INFO DRV_NAME " %s: controller in %s mode\n", |
28cfd8af | 619 | pci_name(dev), mode[conf & 1]); |
da9091ee AC |
620 | return 0; |
621 | } | |
622 | ||
ac95beed BZ |
623 | static const struct ide_port_ops it821x_port_ops = { |
624 | /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */ | |
625 | .set_pio_mode = it821x_set_pio_mode, | |
626 | .set_dma_mode = it821x_set_dma_mode, | |
627 | .quirkproc = it821x_quirkproc, | |
628 | .cable_detect = it821x_cable_detect, | |
629 | }; | |
da9091ee | 630 | |
04ba6e73 | 631 | static const struct ide_port_info it821x_chipset __devinitdata = { |
ced3ec8a | 632 | .name = DRV_NAME, |
04ba6e73 BZ |
633 | .init_chipset = init_chipset_it821x, |
634 | .init_hwif = init_hwif_it821x, | |
635 | .port_ops = &it821x_port_ops, | |
636 | .pio_mask = ATA_PIO4, | |
da9091ee AC |
637 | }; |
638 | ||
639 | /** | |
640 | * it821x_init_one - pci layer discovery entry | |
641 | * @dev: PCI device | |
642 | * @id: ident table entry | |
643 | * | |
644 | * Called by the PCI code when it finds an ITE821x controller. | |
645 | * We then use the IDE PCI generic helper to do most of the work. | |
646 | */ | |
647 | ||
648 | static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
649 | { | |
1d76d9dc BZ |
650 | struct it821x_dev *itdevs; |
651 | int rc; | |
eb7a07e8 | 652 | |
1d76d9dc BZ |
653 | itdevs = kzalloc(2 * sizeof(*itdevs), GFP_KERNEL); |
654 | if (itdevs == NULL) { | |
ced3ec8a | 655 | printk(KERN_ERR DRV_NAME " %s: out of memory\n", pci_name(dev)); |
1d76d9dc | 656 | return -ENOMEM; |
eb7a07e8 BZ |
657 | } |
658 | ||
04ba6e73 | 659 | rc = ide_pci_init_one(dev, &it821x_chipset, itdevs); |
1d76d9dc BZ |
660 | if (rc) |
661 | kfree(itdevs); | |
eb7a07e8 | 662 | |
1d76d9dc | 663 | return rc; |
da9091ee AC |
664 | } |
665 | ||
87d8b613 BZ |
666 | static void __devexit it821x_remove(struct pci_dev *dev) |
667 | { | |
668 | struct ide_host *host = pci_get_drvdata(dev); | |
669 | struct it821x_dev *itdevs = host->host_priv; | |
670 | ||
671 | ide_pci_remove(dev); | |
672 | kfree(itdevs); | |
673 | } | |
674 | ||
9cbcc5e3 BZ |
675 | static const struct pci_device_id it821x_pci_tbl[] = { |
676 | { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 }, | |
677 | { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 }, | |
da9091ee AC |
678 | { 0, }, |
679 | }; | |
680 | ||
681 | MODULE_DEVICE_TABLE(pci, it821x_pci_tbl); | |
682 | ||
683 | static struct pci_driver driver = { | |
684 | .name = "ITE821x IDE", | |
685 | .id_table = it821x_pci_tbl, | |
686 | .probe = it821x_init_one, | |
a69999e2 | 687 | .remove = __devexit_p(it821x_remove), |
feb22b7f BZ |
688 | .suspend = ide_pci_suspend, |
689 | .resume = ide_pci_resume, | |
da9091ee AC |
690 | }; |
691 | ||
692 | static int __init it821x_ide_init(void) | |
693 | { | |
694 | return ide_pci_register_driver(&driver); | |
695 | } | |
696 | ||
87d8b613 BZ |
697 | static void __exit it821x_ide_exit(void) |
698 | { | |
699 | pci_unregister_driver(&driver); | |
700 | } | |
701 | ||
da9091ee | 702 | module_init(it821x_ide_init); |
87d8b613 | 703 | module_exit(it821x_ide_exit); |
da9091ee AC |
704 | |
705 | module_param_named(noraid, it8212_noraid, int, S_IRUGO); | |
da195665 | 706 | MODULE_PARM_DESC(noraid, "Force card into bypass mode"); |
da9091ee AC |
707 | |
708 | MODULE_AUTHOR("Alan Cox"); | |
709 | MODULE_DESCRIPTION("PCI driver module for the ITE 821x"); | |
710 | MODULE_LICENSE("GPL"); |