[mirror_ubuntu-bionic-kernel.git] / drivers / ide / pci / ns87415.c

/*
 * linux/drivers/ide/pci/ns87415.c		Version 2.00  Sep. 10, 2002
 *
 * Copyright (C) 1997-1998	Mark Lord <mlord@pobox.com>
 * Copyright (C) 1998		Eddie C. Dost <ecd@skynet.be>
 * Copyright (C) 1999-2000	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2004		Grant Grundler <grundler at parisc-linux.org>
 *
 * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#ifdef CONFIG_SUPERIO
/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
 * which use the integrated NS87514 cell for CD-ROM support.
 * i.e we have to support for CD-ROM installs.
 * See drivers/parisc/superio.c for more gory details.
 */
#include <asm/superio.h>

static unsigned long superio_ide_status[2];
static unsigned long superio_ide_select[2];
static unsigned long superio_ide_dma_status[2];

#define SUPERIO_IDE_MAX_RETRIES 25

/* Because of a defect in Super I/O, all reads of the PCI DMA status 
 * registers, IDE status register and the IDE select register need to be 
 * retried
 */
static u8 superio_ide_inb (unsigned long port)
{
	if (port == superio_ide_status[0] ||
	    port == superio_ide_status[1] ||
	    port == superio_ide_select[0] ||
	    port == superio_ide_select[1] ||
	    port == superio_ide_dma_status[0] ||
	    port == superio_ide_dma_status[1]) {
		u8 tmp;
		int retries = SUPERIO_IDE_MAX_RETRIES;

		/* printk(" [ reading port 0x%x with retry ] ", port); */

		do {
			tmp = inb(port);
			if (tmp == 0)
				udelay(50);
		} while (tmp == 0 && retries-- > 0);

		return tmp;
	}

	return inb(port);
}

static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
{
	u32 base, dmabase;
	u8 tmp;
	struct pci_dev *pdev = hwif->pci_dev;
	u8 port = hwif->channel;

	base = pci_resource_start(pdev, port * 2) & ~3;
	dmabase = pci_resource_start(pdev, 4) & ~3;

	superio_ide_status[port] = base + IDE_STATUS_OFFSET;
	superio_ide_select[port] = base + IDE_SELECT_OFFSET;
	superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);

	/* Clear error/interrupt, enable dma */
	tmp = superio_ide_inb(superio_ide_dma_status[port]);
	outb(tmp | 0x66, superio_ide_dma_status[port]);

	/* We need to override inb to workaround a SuperIO errata */
	hwif->INB = superio_ide_inb;
}

static void __devinit init_iops_ns87415(ide_hwif_t *hwif)
{
	if (PCI_SLOT(hwif->pci_dev->devfn) == 0xE) {
		/* Built-in - assume it's under superio. */
		superio_ide_init_iops(hwif);
	}
}
#endif

static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };

/*
 * This routine either enables/disables (according to drive->present)
 * the IRQ associated with the port (HWIF(drive)),
 * and selects either PIO or DMA handshaking for the next I/O operation.
 */
static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
{
	ide_hwif_t *hwif = HWIF(drive);
	unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
	struct pci_dev *dev = hwif->pci_dev;
	unsigned long flags;

	local_irq_save(flags);
	new = *old;

	/* Adjust IRQ enable bit */
	bit = 1 << (8 + hwif->channel);
	new = drive->present ? (new & ~bit) : (new | bit);

	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
	bit   = 1 << (20 + drive->select.b.unit       + (hwif->channel << 1));
	other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
	new = use_dma ? ((new & ~other) | bit) : (new & ~bit);

	if (new != *old) {
		unsigned char stat;

		/*
		 * Don't change DMA engine settings while Write Buffers
		 * are busy.
		 */
		(void) pci_read_config_byte(dev, 0x43, &stat);
		while (stat & 0x03) {
			udelay(1);
			(void) pci_read_config_byte(dev, 0x43, &stat);
		}

		*old = new;
		(void) pci_write_config_dword(dev, 0x40, new);

		/*
		 * And let things settle...
		 */
		udelay(10);
	}

	local_irq_restore(flags);
}

static void ns87415_selectproc (ide_drive_t *drive)
{
	ns87415_prepare_drive (drive, drive->using_dma);
}

static int ns87415_ide_dma_end (ide_drive_t *drive)
{
	ide_hwif_t      *hwif = HWIF(drive);
	u8 dma_stat = 0, dma_cmd = 0;

	drive->waiting_for_dma = 0;
	dma_stat = hwif->INB(hwif->dma_status);
	/* get dma command mode */
	dma_cmd = hwif->INB(hwif->dma_command);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_command);
	/* from ERRATA: clear the INTR & ERROR bits */
	dma_cmd = hwif->INB(hwif->dma_command);
	outb(dma_cmd | 6, hwif->dma_command);
	/* and free any DMA resources */
	ide_destroy_dmatable(drive);
	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static int ns87415_ide_dma_setup(ide_drive_t *drive)
{
	/* select DMA xfer */
	ns87415_prepare_drive(drive, 1);
	if (!ide_dma_setup(drive))
		return 0;
	/* DMA failed: select PIO xfer */
	ns87415_prepare_drive(drive, 0);
	return 1;
}

static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
{
	struct pci_dev *dev = hwif->pci_dev;
	unsigned int ctrl, using_inta;
	u8 progif;
#ifdef __sparc_v9__
	int timeout;
	u8 stat;
#endif

	hwif->selectproc = &ns87415_selectproc;

	/*
	 * We cannot probe for IRQ: both ports share common IRQ on INTA.
	 * Also, leave IRQ masked during drive probing, to prevent infinite
	 * interrupts from a potentially floating INTA..
	 *
	 * IRQs get unmasked in selectproc when drive is first used.
	 */
	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	(void) pci_read_config_byte(dev, 0x09, &progif);
	/* is irq in "native" mode? */
	using_inta = progif & (1 << (hwif->channel << 1));
	if (!using_inta)
		using_inta = ctrl & (1 << (4 + hwif->channel));
	if (hwif->mate) {
		hwif->select_data = hwif->mate->select_data;
	} else {
		hwif->select_data = (unsigned long)
					&ns87415_control[ns87415_count++];
		ctrl |= (1 << 8) | (1 << 9);	/* mask both IRQs */
		if (using_inta)
			ctrl &= ~(1 << 6);	/* unmask INTA */
		*((unsigned int *)hwif->select_data) = ctrl;
		(void) pci_write_config_dword(dev, 0x40, ctrl);

		/*
		 * Set prefetch size to 512 bytes for both ports,
		 * but don't turn on/off prefetching here.
		 */
		pci_write_config_byte(dev, 0x55, 0xee);

#ifdef __sparc_v9__
		/*
		 * XXX: Reset the device, if we don't it will not respond
		 *      to SELECT_DRIVE() properly during first probe_hwif().
		 */
		timeout = 10000;
		outb(12, hwif->io_ports[IDE_CONTROL_OFFSET]);
		udelay(10);
		outb(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
		do {
			udelay(50);
			stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
                	if (stat == 0xff)
                        	break;
        	} while ((stat & BUSY_STAT) && --timeout);
#endif
	}

	if (!using_inta)
		hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]);
	else if (!hwif->irq && hwif->mate && hwif->mate->irq)
		hwif->irq = hwif->mate->irq;	/* share IRQ with mate */

	if (!hwif->dma_base)
		return;

	outb(0x60, hwif->dma_status);
	hwif->dma_setup = &ns87415_ide_dma_setup;
	hwif->ide_dma_end = &ns87415_ide_dma_end;
}

static struct ide_port_info ns87415_chipset __devinitdata = {
	.name		= "NS87415",
#ifdef CONFIG_SUPERIO
	.init_iops	= init_iops_ns87415,
#endif
	.init_hwif	= init_hwif_ns87415,
	.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA |
			  IDE_HFLAG_NO_ATAPI_DMA |
			  IDE_HFLAG_BOOTABLE,
};

static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &ns87415_chipset);
}

static const struct pci_device_id ns87415_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);

static struct pci_driver driver = {
	.name		= "NS87415_IDE",
	.id_table	= ns87415_pci_tbl,
	.probe		= ns87415_init_one,
};

static int __init ns87415_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(ns87415_ide_init);

MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/ide/pci/ns87415.c Version 2.00 Sep. 10, 2002
	3	*
	4	* Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
	5	* Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
	6	* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
	7	* Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
	8	*
	9	* Inspired by an earlier effort from David S. Miller <davem@redhat.com>
	10	*/
	11
1da177e4 LT	12	#include <linux/module.h>
	13	#include <linux/types.h>
	14	#include <linux/kernel.h>
	15	#include <linux/timer.h>
	16	#include <linux/mm.h>
	17	#include <linux/ioport.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/blkdev.h>
	20	#include <linux/hdreg.h>
	21	#include <linux/pci.h>
	22	#include <linux/delay.h>
	23	#include <linux/ide.h>
	24	#include <linux/init.h>
	25
	26	#include <asm/io.h>
	27
	28	#ifdef CONFIG_SUPERIO
	29	/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
	30	* Unfortunately, it's built-in on all Astro-based PA-RISC workstations
	31	* which use the integrated NS87514 cell for CD-ROM support.
	32	* i.e we have to support for CD-ROM installs.
	33	* See drivers/parisc/superio.c for more gory details.
	34	*/
	35	#include <asm/superio.h>
	36
	37	static unsigned long superio_ide_status[2];
	38	static unsigned long superio_ide_select[2];
	39	static unsigned long superio_ide_dma_status[2];
	40
	41	#define SUPERIO_IDE_MAX_RETRIES 25
	42
	43	/* Because of a defect in Super I/O, all reads of the PCI DMA status
	44	* registers, IDE status register and the IDE select register need to be
	45	* retried
	46	*/
	47	static u8 superio_ide_inb (unsigned long port)
	48	{
	49	if (port == superio_ide_status[0] \|\|
	50	port == superio_ide_status[1] \|\|
	51	port == superio_ide_select[0] \|\|
	52	port == superio_ide_select[1] \|\|
	53	port == superio_ide_dma_status[0] \|\|
	54	port == superio_ide_dma_status[1]) {
	55	u8 tmp;
	56	int retries = SUPERIO_IDE_MAX_RETRIES;
	57
	58	/* printk(" [ reading port 0x%x with retry ] ", port); */
	59
	60	do {
	61	tmp = inb(port);
	62	if (tmp == 0)
	63	udelay(50);
	64	} while (tmp == 0 && retries-- > 0);
	65
	66	return tmp;
	67	}
	68
	69	return inb(port);
	70	}
	71
	72	static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
	73	{
	74	u32 base, dmabase;
	75	u8 tmp;
76	struct pci_dev *pdev = hwif->pci_dev;
77	u8 port = hwif->channel;
78
79	base = pci_resource_start(pdev, port * 2) & ~3;
80	dmabase = pci_resource_start(pdev, 4) & ~3;
81
82	superio_ide_status[port] = base + IDE_STATUS_OFFSET;
83	superio_ide_select[port] = base + IDE_SELECT_OFFSET;
84	superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);
85
86	/* Clear error/interrupt, enable dma */
87	tmp = superio_ide_inb(superio_ide_dma_status[port]);
88	outb(tmp \| 0x66, superio_ide_dma_status[port]);
89
90	/* We need to override inb to workaround a SuperIO errata */
91	hwif->INB = superio_ide_inb;
92	}
93
94	static void __devinit init_iops_ns87415(ide_hwif_t *hwif)
95	{
96	if (PCI_SLOT(hwif->pci_dev->devfn) == 0xE) {
97	/* Built-in - assume it's under superio. */
98	superio_ide_init_iops(hwif);
99	}
100	}
101	#endif
102
103	static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
104
105	/*
106	* This routine either enables/disables (according to drive->present)
107	* the IRQ associated with the port (HWIF(drive)),
108	* and selects either PIO or DMA handshaking for the next I/O operation.
109	*/
110	static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
111	{
112	ide_hwif_t *hwif = HWIF(drive);
113	unsigned int bit, other, new, old = (unsigned int ) hwif->select_data;
114	struct pci_dev *dev = hwif->pci_dev;
115	unsigned long flags;
116
117	local_irq_save(flags);
118	new = *old;
119
120	/* Adjust IRQ enable bit */
121	bit = 1 << (8 + hwif->channel);
122	new = drive->present ? (new & ~bit) : (new \| bit);
123
124	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
125	bit = 1 << (20 + drive->select.b.unit + (hwif->channel << 1));
126	other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
127	new = use_dma ? ((new & ~other) \| bit) : (new & ~bit);
128
129	if (new != *old) {
130	unsigned char stat;
131
132	/*
133	* Don't change DMA engine settings while Write Buffers
134	* are busy.
135	*/
136	(void) pci_read_config_byte(dev, 0x43, &stat);
137	while (stat & 0x03) {
138	udelay(1);
139	(void) pci_read_config_byte(dev, 0x43, &stat);
140	}
141
142	*old = new;
143	(void) pci_write_config_dword(dev, 0x40, new);
144
145	/*
146	* And let things settle...
147	*/
148	udelay(10);
149	}
150
151	local_irq_restore(flags);
152	}
153
154	static void ns87415_selectproc (ide_drive_t *drive)
155	{
156	ns87415_prepare_drive (drive, drive->using_dma);
157	}
158
159	static int ns87415_ide_dma_end (ide_drive_t *drive)
160	{
161	ide_hwif_t *hwif = HWIF(drive);
162	u8 dma_stat = 0, dma_cmd = 0;
163
164	drive->waiting_for_dma = 0;
165	dma_stat = hwif->INB(hwif->dma_status);
166	/* get dma command mode */
167	dma_cmd = hwif->INB(hwif->dma_command);
168	/* stop DMA */
0ecdca26	169	outb(dma_cmd & ~1, hwif->dma_command);
1da177e4 LT	170	/* from ERRATA: clear the INTR & ERROR bits */
1da177e4 LT	171	dma_cmd = hwif->INB(hwif->dma_command);
0ecdca26	172	outb(dma_cmd \| 6, hwif->dma_command);
1da177e4 LT	173	/* and free any DMA resources */
	174	ide_destroy_dmatable(drive);
	175	/* verify good DMA status */
	176	return (dma_stat & 7) != 4;
	177	}
	178
	179	static int ns87415_ide_dma_setup(ide_drive_t *drive)
	180	{
	181	/* select DMA xfer */
	182	ns87415_prepare_drive(drive, 1);
	183	if (!ide_dma_setup(drive))
	184	return 0;
	185	/* DMA failed: select PIO xfer */
	186	ns87415_prepare_drive(drive, 0);
	187	return 1;
	188	}
	189
c20530ed	190	static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
1da177e4 LT	191	{
	192	struct pci_dev *dev = hwif->pci_dev;
	193	unsigned int ctrl, using_inta;
	194	u8 progif;
	195	#ifdef __sparc_v9__
	196	int timeout;
	197	u8 stat;
	198	#endif
	199
1da177e4 LT	200	hwif->selectproc = &ns87415_selectproc;
	201
	202	/*
	203	* We cannot probe for IRQ: both ports share common IRQ on INTA.
	204	* Also, leave IRQ masked during drive probing, to prevent infinite
	205	* interrupts from a potentially floating INTA..
	206	*
	207	* IRQs get unmasked in selectproc when drive is first used.
	208	*/
	209	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	210	(void) pci_read_config_byte(dev, 0x09, &progif);
	211	/* is irq in "native" mode? */
	212	using_inta = progif & (1 << (hwif->channel << 1));
	213	if (!using_inta)
	214	using_inta = ctrl & (1 << (4 + hwif->channel));
	215	if (hwif->mate) {
	216	hwif->select_data = hwif->mate->select_data;
	217	} else {
	218	hwif->select_data = (unsigned long)
	219	&ns87415_control[ns87415_count++];
	220	ctrl \|= (1 << 8) \| (1 << 9); /* mask both IRQs */
	221	if (using_inta)
	222	ctrl &= ~(1 << 6); /* unmask INTA */
	223	((unsigned int )hwif->select_data) = ctrl;
	224	(void) pci_write_config_dword(dev, 0x40, ctrl);
	225
	226	/*
	227	* Set prefetch size to 512 bytes for both ports,
	228	* but don't turn on/off prefetching here.
	229	*/
	230	pci_write_config_byte(dev, 0x55, 0xee);
	231
	232	#ifdef __sparc_v9__
	233	/*
	234	* XXX: Reset the device, if we don't it will not respond
	235	* to SELECT_DRIVE() properly during first probe_hwif().
	236	*/
	237	timeout = 10000;
0ecdca26	238	outb(12, hwif->io_ports[IDE_CONTROL_OFFSET]);
1da177e4	239	udelay(10);
0ecdca26	240	outb(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
1da177e4 LT	241	do {
	242	udelay(50);
	243	stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
	244	if (stat == 0xff)
	245	break;
	246	} while ((stat & BUSY_STAT) && --timeout);
	247	#endif
	248	}
	249
	250	if (!using_inta)
	251	hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]);
	252	else if (!hwif->irq && hwif->mate && hwif->mate->irq)
	253	hwif->irq = hwif->mate->irq; /* share IRQ with mate */
	254
	255	if (!hwif->dma_base)
	256	return;
	257
0ecdca26	258	outb(0x60, hwif->dma_status);
1da177e4	259	hwif->dma_setup = &ns87415_ide_dma_setup;
1da177e4	260	hwif->ide_dma_end = &ns87415_ide_dma_end;
1da177e4 LT	261	}
1da177e4 LT	262
039788e1	263	static struct ide_port_info ns87415_chipset __devinitdata = {
1da177e4 LT	264	.name = "NS87415",
	265	#ifdef CONFIG_SUPERIO
	266	.init_iops = init_iops_ns87415,
	267	#endif
	268	.init_hwif = init_hwif_ns87415,
33c1002e	269	.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA \|
7cab14a7 BZ	270	IDE_HFLAG_NO_ATAPI_DMA \|
7cab14a7 BZ	271	IDE_HFLAG_BOOTABLE,
1da177e4 LT	272	};
	273
	274	static int __devinit ns87415_init_one(struct pci_dev dev, const struct pci_device_id id)
	275	{
	276	return ide_setup_pci_device(dev, &ns87415_chipset);
	277	}
	278
9cbcc5e3 BZ	279	static const struct pci_device_id ns87415_pci_tbl[] = {
9cbcc5e3 BZ	280	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
1da177e4 LT	281	{ 0, },
	282	};
	283	MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
	284
	285	static struct pci_driver driver = {
	286	.name = "NS87415_IDE",
	287	.id_table = ns87415_pci_tbl,
	288	.probe = ns87415_init_one,
	289	};
	290
82ab1eec	291	static int __init ns87415_ide_init(void)
1da177e4 LT	292	{
	293	return ide_pci_register_driver(&driver);
	294	}
	295
	296	module_init(ns87415_ide_init);
	297
	298	MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
	299	MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
	300	MODULE_LICENSE("GPL");