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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com> |
3 | * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be> | |
4 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org> | |
6 | * | |
7 | * Inspired by an earlier effort from David S. Miller <davem@redhat.com> | |
8 | */ | |
9 | ||
1da177e4 LT |
10 | #include <linux/module.h> |
11 | #include <linux/types.h> | |
12 | #include <linux/kernel.h> | |
1da177e4 | 13 | #include <linux/interrupt.h> |
1da177e4 LT |
14 | #include <linux/hdreg.h> |
15 | #include <linux/pci.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ide.h> | |
18 | #include <linux/init.h> | |
19 | ||
20 | #include <asm/io.h> | |
21 | ||
22 | #ifdef CONFIG_SUPERIO | |
23 | /* SUPERIO 87560 is a PoS chip that NatSem denies exists. | |
24 | * Unfortunately, it's built-in on all Astro-based PA-RISC workstations | |
25 | * which use the integrated NS87514 cell for CD-ROM support. | |
26 | * i.e we have to support for CD-ROM installs. | |
27 | * See drivers/parisc/superio.c for more gory details. | |
28 | */ | |
29 | #include <asm/superio.h> | |
30 | ||
31 | static unsigned long superio_ide_status[2]; | |
32 | static unsigned long superio_ide_select[2]; | |
33 | static unsigned long superio_ide_dma_status[2]; | |
34 | ||
35 | #define SUPERIO_IDE_MAX_RETRIES 25 | |
36 | ||
37 | /* Because of a defect in Super I/O, all reads of the PCI DMA status | |
38 | * registers, IDE status register and the IDE select register need to be | |
39 | * retried | |
40 | */ | |
41 | static u8 superio_ide_inb (unsigned long port) | |
42 | { | |
43 | if (port == superio_ide_status[0] || | |
44 | port == superio_ide_status[1] || | |
45 | port == superio_ide_select[0] || | |
46 | port == superio_ide_select[1] || | |
47 | port == superio_ide_dma_status[0] || | |
48 | port == superio_ide_dma_status[1]) { | |
49 | u8 tmp; | |
50 | int retries = SUPERIO_IDE_MAX_RETRIES; | |
51 | ||
52 | /* printk(" [ reading port 0x%x with retry ] ", port); */ | |
53 | ||
54 | do { | |
55 | tmp = inb(port); | |
56 | if (tmp == 0) | |
57 | udelay(50); | |
58 | } while (tmp == 0 && retries-- > 0); | |
59 | ||
60 | return tmp; | |
61 | } | |
62 | ||
63 | return inb(port); | |
64 | } | |
65 | ||
66 | static void __devinit superio_ide_init_iops (struct hwif_s *hwif) | |
67 | { | |
36501650 | 68 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
1da177e4 | 69 | u32 base, dmabase; |
36501650 | 70 | u8 port = hwif->channel, tmp; |
1da177e4 LT |
71 | |
72 | base = pci_resource_start(pdev, port * 2) & ~3; | |
73 | dmabase = pci_resource_start(pdev, 4) & ~3; | |
74 | ||
75 | superio_ide_status[port] = base + IDE_STATUS_OFFSET; | |
76 | superio_ide_select[port] = base + IDE_SELECT_OFFSET; | |
77 | superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa); | |
78 | ||
79 | /* Clear error/interrupt, enable dma */ | |
80 | tmp = superio_ide_inb(superio_ide_dma_status[port]); | |
81 | outb(tmp | 0x66, superio_ide_dma_status[port]); | |
82 | ||
83 | /* We need to override inb to workaround a SuperIO errata */ | |
84 | hwif->INB = superio_ide_inb; | |
85 | } | |
86 | ||
87 | static void __devinit init_iops_ns87415(ide_hwif_t *hwif) | |
88 | { | |
36501650 BZ |
89 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
90 | ||
91 | if (PCI_SLOT(dev->devfn) == 0xE) | |
1da177e4 LT |
92 | /* Built-in - assume it's under superio. */ |
93 | superio_ide_init_iops(hwif); | |
1da177e4 LT |
94 | } |
95 | #endif | |
96 | ||
97 | static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 }; | |
98 | ||
99 | /* | |
100 | * This routine either enables/disables (according to drive->present) | |
101 | * the IRQ associated with the port (HWIF(drive)), | |
102 | * and selects either PIO or DMA handshaking for the next I/O operation. | |
103 | */ | |
104 | static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma) | |
105 | { | |
106 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 107 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 108 | unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data; |
1da177e4 LT |
109 | unsigned long flags; |
110 | ||
111 | local_irq_save(flags); | |
112 | new = *old; | |
113 | ||
114 | /* Adjust IRQ enable bit */ | |
115 | bit = 1 << (8 + hwif->channel); | |
116 | new = drive->present ? (new & ~bit) : (new | bit); | |
117 | ||
118 | /* Select PIO or DMA, DMA may only be selected for one drive/channel. */ | |
119 | bit = 1 << (20 + drive->select.b.unit + (hwif->channel << 1)); | |
120 | other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1)); | |
121 | new = use_dma ? ((new & ~other) | bit) : (new & ~bit); | |
122 | ||
123 | if (new != *old) { | |
124 | unsigned char stat; | |
125 | ||
126 | /* | |
127 | * Don't change DMA engine settings while Write Buffers | |
128 | * are busy. | |
129 | */ | |
130 | (void) pci_read_config_byte(dev, 0x43, &stat); | |
131 | while (stat & 0x03) { | |
132 | udelay(1); | |
133 | (void) pci_read_config_byte(dev, 0x43, &stat); | |
134 | } | |
135 | ||
136 | *old = new; | |
137 | (void) pci_write_config_dword(dev, 0x40, new); | |
138 | ||
139 | /* | |
140 | * And let things settle... | |
141 | */ | |
142 | udelay(10); | |
143 | } | |
144 | ||
145 | local_irq_restore(flags); | |
146 | } | |
147 | ||
148 | static void ns87415_selectproc (ide_drive_t *drive) | |
149 | { | |
150 | ns87415_prepare_drive (drive, drive->using_dma); | |
151 | } | |
152 | ||
153 | static int ns87415_ide_dma_end (ide_drive_t *drive) | |
154 | { | |
155 | ide_hwif_t *hwif = HWIF(drive); | |
156 | u8 dma_stat = 0, dma_cmd = 0; | |
157 | ||
158 | drive->waiting_for_dma = 0; | |
159 | dma_stat = hwif->INB(hwif->dma_status); | |
160 | /* get dma command mode */ | |
161 | dma_cmd = hwif->INB(hwif->dma_command); | |
162 | /* stop DMA */ | |
0ecdca26 | 163 | outb(dma_cmd & ~1, hwif->dma_command); |
1da177e4 LT |
164 | /* from ERRATA: clear the INTR & ERROR bits */ |
165 | dma_cmd = hwif->INB(hwif->dma_command); | |
0ecdca26 | 166 | outb(dma_cmd | 6, hwif->dma_command); |
1da177e4 LT |
167 | /* and free any DMA resources */ |
168 | ide_destroy_dmatable(drive); | |
169 | /* verify good DMA status */ | |
170 | return (dma_stat & 7) != 4; | |
171 | } | |
172 | ||
173 | static int ns87415_ide_dma_setup(ide_drive_t *drive) | |
174 | { | |
175 | /* select DMA xfer */ | |
176 | ns87415_prepare_drive(drive, 1); | |
177 | if (!ide_dma_setup(drive)) | |
178 | return 0; | |
179 | /* DMA failed: select PIO xfer */ | |
180 | ns87415_prepare_drive(drive, 0); | |
181 | return 1; | |
182 | } | |
183 | ||
0e33555f BZ |
184 | #ifndef ide_default_irq |
185 | #define ide_default_irq(irq) 0 | |
186 | #endif | |
187 | ||
c20530ed | 188 | static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif) |
1da177e4 | 189 | { |
36501650 | 190 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
191 | unsigned int ctrl, using_inta; |
192 | u8 progif; | |
193 | #ifdef __sparc_v9__ | |
194 | int timeout; | |
195 | u8 stat; | |
196 | #endif | |
197 | ||
1da177e4 LT |
198 | hwif->selectproc = &ns87415_selectproc; |
199 | ||
200 | /* | |
201 | * We cannot probe for IRQ: both ports share common IRQ on INTA. | |
202 | * Also, leave IRQ masked during drive probing, to prevent infinite | |
203 | * interrupts from a potentially floating INTA.. | |
204 | * | |
205 | * IRQs get unmasked in selectproc when drive is first used. | |
206 | */ | |
207 | (void) pci_read_config_dword(dev, 0x40, &ctrl); | |
208 | (void) pci_read_config_byte(dev, 0x09, &progif); | |
209 | /* is irq in "native" mode? */ | |
210 | using_inta = progif & (1 << (hwif->channel << 1)); | |
211 | if (!using_inta) | |
212 | using_inta = ctrl & (1 << (4 + hwif->channel)); | |
213 | if (hwif->mate) { | |
214 | hwif->select_data = hwif->mate->select_data; | |
215 | } else { | |
216 | hwif->select_data = (unsigned long) | |
217 | &ns87415_control[ns87415_count++]; | |
218 | ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */ | |
219 | if (using_inta) | |
220 | ctrl &= ~(1 << 6); /* unmask INTA */ | |
221 | *((unsigned int *)hwif->select_data) = ctrl; | |
222 | (void) pci_write_config_dword(dev, 0x40, ctrl); | |
223 | ||
224 | /* | |
225 | * Set prefetch size to 512 bytes for both ports, | |
226 | * but don't turn on/off prefetching here. | |
227 | */ | |
228 | pci_write_config_byte(dev, 0x55, 0xee); | |
229 | ||
230 | #ifdef __sparc_v9__ | |
231 | /* | |
9d501529 BZ |
232 | * XXX: Reset the device, if we don't it will not respond to |
233 | * SELECT_DRIVE() properly during first ide_probe_port(). | |
1da177e4 LT |
234 | */ |
235 | timeout = 10000; | |
0ecdca26 | 236 | outb(12, hwif->io_ports[IDE_CONTROL_OFFSET]); |
1da177e4 | 237 | udelay(10); |
0ecdca26 | 238 | outb(8, hwif->io_ports[IDE_CONTROL_OFFSET]); |
1da177e4 LT |
239 | do { |
240 | udelay(50); | |
241 | stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); | |
242 | if (stat == 0xff) | |
243 | break; | |
244 | } while ((stat & BUSY_STAT) && --timeout); | |
245 | #endif | |
246 | } | |
247 | ||
248 | if (!using_inta) | |
249 | hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]); | |
250 | else if (!hwif->irq && hwif->mate && hwif->mate->irq) | |
251 | hwif->irq = hwif->mate->irq; /* share IRQ with mate */ | |
252 | ||
253 | if (!hwif->dma_base) | |
254 | return; | |
255 | ||
0ecdca26 | 256 | outb(0x60, hwif->dma_status); |
1da177e4 | 257 | hwif->dma_setup = &ns87415_ide_dma_setup; |
1da177e4 | 258 | hwif->ide_dma_end = &ns87415_ide_dma_end; |
1da177e4 LT |
259 | } |
260 | ||
85620436 | 261 | static const struct ide_port_info ns87415_chipset __devinitdata = { |
1da177e4 LT |
262 | .name = "NS87415", |
263 | #ifdef CONFIG_SUPERIO | |
264 | .init_iops = init_iops_ns87415, | |
265 | #endif | |
266 | .init_hwif = init_hwif_ns87415, | |
33c1002e | 267 | .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA | |
5e71d9c5 | 268 | IDE_HFLAG_NO_ATAPI_DMA, |
1da177e4 LT |
269 | }; |
270 | ||
271 | static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
272 | { | |
273 | return ide_setup_pci_device(dev, &ns87415_chipset); | |
274 | } | |
275 | ||
9cbcc5e3 BZ |
276 | static const struct pci_device_id ns87415_pci_tbl[] = { |
277 | { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 }, | |
1da177e4 LT |
278 | { 0, }, |
279 | }; | |
280 | MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl); | |
281 | ||
282 | static struct pci_driver driver = { | |
283 | .name = "NS87415_IDE", | |
284 | .id_table = ns87415_pci_tbl, | |
285 | .probe = ns87415_init_one, | |
286 | }; | |
287 | ||
82ab1eec | 288 | static int __init ns87415_ide_init(void) |
1da177e4 LT |
289 | { |
290 | return ide_pci_register_driver(&driver); | |
291 | } | |
292 | ||
293 | module_init(ns87415_ide_init); | |
294 | ||
295 | MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick"); | |
296 | MODULE_DESCRIPTION("PCI driver module for NS87415 IDE"); | |
297 | MODULE_LICENSE("GPL"); |