[mirror_ubuntu-jammy-kernel.git] / drivers / ide / pci / opti621.c

/*
 *  Copyright (C) 1996-1998  Linus Torvalds & authors (see below)
 */

/*
 * Authors:
 * Jaromir Koutek <miri@punknet.cz>,
 * Jan Harkes <jaharkes@cwi.nl>,
 * Mark Lord <mlord@pobox.com>
 * Some parts of code are from ali14xx.c and from rz1000.c.
 *
 * OPTi is trademark of OPTi, Octek is trademark of Octek.
 *
 * I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
 * and disassembled/traced setupvic.exe (DOS program).
 * It increases kernel code about 2 kB.
 * I don't have this card no more, but I hope I can get some in case
 * of needed development.
 * My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
 * It has a place for a secondary connector in circuit, but nothing
 * is there. Also BIOS says no address for
 * secondary controller (see bellow in ide_init_opti621).
 * I've only tested this on my system, which only has one disk.
 * It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
 * is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
 * lockups). I tried the OCTEK double speed CD-ROM and
 * it does not work! But I can't boot DOS also, so it's probably
 * hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
 * problems) and Seagate 1GB (as slave, WD as master). My experiences
 * with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
 * it slows to about 100kB/s! I don't know why and I have
 * not this drive now, so I can't try it again.
 * I write this driver because I lost the paper ("manual") with
 * settings of jumpers on the card and I have to boot Linux with
 * Loadlin except LILO, cause I have to run the setupvic.exe program
 * already or I get disk errors (my test: rpm -Vf
 * /usr/X11R6/bin/XF86_SVGA - or any big file).
 * Some numbers from hdparm -t /dev/hda:
 * Timing buffer-cache reads:   32 MB in  3.02 seconds =10.60 MB/sec
 * Timing buffered disk reads:  16 MB in  5.52 seconds = 2.90 MB/sec
 * I have 4 Megs/s before, but I don't know why (maybe changes
 * in hdparm test).
 * After release of 0.1, I got some successful reports, so it might work.
 *
 * The main problem with OPTi is that some timings for master
 * and slave must be the same. For example, if you have master
 * PIO 3 and slave PIO 0, driver have to set some timings of
 * master for PIO 0. Second problem is that opti621_set_pio_mode
 * got only one drive to set, but have to set both drives.
 * This is solved in compute_pios. If you don't set
 * the second drive, compute_pios use ide_get_best_pio_mode
 * for autoselect mode (you can change it to PIO 0, if you want).
 * If you then set the second drive to another PIO, the old value
 * (automatically selected) will be overrided by yours.
 * There is a 25/33MHz switch in configuration
 * register, but driver is written for use at any frequency which get
 * (use idebus=xx to select PCI bus speed).
 *
 * Version 0.1, Nov 8, 1996
 * by Jaromir Koutek, for 2.1.8.
 * Initial version of driver.
 *
 * Version 0.2
 * Number 0.2 skipped.
 *
 * Version 0.3, Nov 29, 1997
 * by Mark Lord (probably), for 2.1.68
 * Updates for use with new IDE block driver.
 *
 * Version 0.4, Dec 14, 1997
 * by Jan Harkes
 * Fixed some errors and cleaned the code.
 *
 * Version 0.5, Jan 2, 1998
 * by Jaromir Koutek
 * Updates for use with (again) new IDE block driver.
 * Update of documentation.
 *
 * Version 0.6, Jan 2, 1999
 * by Jaromir Koutek
 * Reversed to version 0.3 of the driver, because
 * 0.5 doesn't work.
 */

#define OPTI621_DEBUG		/* define for debug messages */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>

#include <asm/io.h>

//#define OPTI621_MAX_PIO 3
/* In fact, I do not have any PIO 4 drive
 * (address: 25 ns, data: 70 ns, recovery: 35 ns),
 * but OPTi 82C621 is programmable and it can do (minimal values):
 * on 40MHz PCI bus (pulse 25 ns):
 *  address: 25 ns, data: 25 ns, recovery: 50 ns;
 * on 20MHz PCI bus (pulse 50 ns):
 *  address: 50 ns, data: 50 ns, recovery: 100 ns.
 */

/* #define READ_PREFETCH 0 */
/* Uncomment for disable read prefetch.
 * There is some readprefetch capatibility in hdparm,
 * but when I type hdparm -P 1 /dev/hda, I got errors
 * and till reset drive is inaccessible.
 * This (hw) read prefetch is safe on my drive.
 */

#ifndef READ_PREFETCH
#define READ_PREFETCH 0x40 /* read prefetch is enabled */
#endif /* else read prefetch is disabled */

#define READ_REG 0	/* index of Read cycle timing register */
#define WRITE_REG 1	/* index of Write cycle timing register */
#define CNTRL_REG 3	/* index of Control register */
#define STRAP_REG 5	/* index of Strap register */
#define MISC_REG 6	/* index of Miscellaneous register */

static int reg_base;

#define PIO_NOT_EXIST 254
#define PIO_DONT_KNOW 255

static DEFINE_SPINLOCK(opti621_lock);

/* there are stored pio numbers from other calls of opti621_set_pio_mode */
static void compute_pios(ide_drive_t *drive, const u8 pio)
/* Store values into drive->drive_data
 *	second_contr - 0 for primary controller, 1 for secondary
 *	slave_drive - 0 -> pio is for master, 1 -> pio is for slave
 *	pio - PIO mode for selected drive (for other we don't know)
 */
{
	int d;
	ide_hwif_t *hwif = HWIF(drive);

	drive->drive_data = pio;

	for (d = 0; d < 2; ++d) {
		drive = &hwif->drives[d];
		if (drive->present) {
			if (drive->drive_data == PIO_DONT_KNOW)
				drive->drive_data = ide_get_best_pio_mode(drive, 255, 3);
#ifdef OPTI621_DEBUG
			printk("%s: Selected PIO mode %d\n",
				drive->name, drive->drive_data);
#endif
		} else {
			drive->drive_data = PIO_NOT_EXIST;
		}
	}
}

static int cmpt_clk(int time, int bus_speed)
/* Returns (rounded up) time in clocks for time in ns,
 * with bus_speed in MHz.
 * Example: bus_speed = 40 MHz, time = 80 ns
 * 1000/40 = 25 ns (clk value),
 * 80/25 = 3.2, rounded up to 4 (I hope ;-)).
 * Use idebus=xx to select right frequency.
 */
{
	return ((time*bus_speed+999)/1000);
}

/* Write value to register reg, base of register
 * is at reg_base (0x1f0 primary, 0x170 secondary,
 * if not changed by PCI configuration).
 * This is from setupvic.exe program.
 */
static void write_reg(u8 value, int reg)
{
	inw(reg_base + 1);
	inw(reg_base + 1);
	outb(3, reg_base + 2);
	outb(value, reg_base + reg);
	outb(0x83, reg_base + 2);
}

/* Read value from register reg, base of register
 * is at reg_base (0x1f0 primary, 0x170 secondary,
 * if not changed by PCI configuration).
 * This is from setupvic.exe program.
 */
static u8 read_reg(int reg)
{
	u8 ret = 0;

	inw(reg_base + 1);
	inw(reg_base + 1);
	outb(3, reg_base + 2);
	ret = inb(reg_base + reg);
	outb(0x83, reg_base + 2);

	return ret;
}

typedef struct pio_clocks_s {
	int	address_time;	/* Address setup (clocks) */
	int	data_time;	/* Active/data pulse (clocks) */
	int	recovery_time;	/* Recovery time (clocks) */
} pio_clocks_t;

static void compute_clocks(int pio, pio_clocks_t *clks)
{
	if (pio != PIO_NOT_EXIST) {
		int adr_setup, data_pls;
		int bus_speed = system_bus_clock();

		adr_setup = ide_pio_timings[pio].setup_time;
		data_pls = ide_pio_timings[pio].active_time;
		clks->address_time = cmpt_clk(adr_setup, bus_speed);
		clks->data_time = cmpt_clk(data_pls, bus_speed);
		clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
			- adr_setup-data_pls, bus_speed);
		if (clks->address_time < 1)
			clks->address_time = 1;
		if (clks->address_time > 4)
			clks->address_time = 4;
		if (clks->data_time < 1)
			clks->data_time = 1;
		if (clks->data_time > 16)
			clks->data_time = 16;
		if (clks->recovery_time < 2)
			clks->recovery_time = 2;
		if (clks->recovery_time > 17)
			clks->recovery_time = 17;
	} else {
		clks->address_time = 1;
		clks->data_time = 1;
		clks->recovery_time = 2;
		/* minimal values */
	}
}

static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	/* primary and secondary drives share some registers,
	 * so we have to program both drives
	 */
	unsigned long flags;
	u8 pio1 = 0, pio2 = 0;
	pio_clocks_t first, second;
	int ax, drdy;
	u8 cycle1, cycle2, misc;
	ide_hwif_t *hwif = HWIF(drive);

	/* sets drive->drive_data for both drives */
	compute_pios(drive, pio);
	pio1 = hwif->drives[0].drive_data;
	pio2 = hwif->drives[1].drive_data;

	compute_clocks(pio1, &first);
	compute_clocks(pio2, &second);

	/* ax = max(a1,a2) */
	ax = (first.address_time < second.address_time) ? second.address_time : first.address_time;

	drdy = 2; /* DRDY is default 2 (by OPTi Databook) */

	cycle1 = ((first.data_time-1)<<4)  | (first.recovery_time-2);
	cycle2 = ((second.data_time-1)<<4) | (second.recovery_time-2);
	misc = READ_PREFETCH | ((ax-1)<<4) | ((drdy-2)<<1);

#ifdef OPTI621_DEBUG
	printk("%s: master: address: %d, data: %d, "
		"recovery: %d, drdy: %d [clk]\n",
		hwif->name, ax, first.data_time,
		first.recovery_time, drdy);
	printk("%s: slave:  address: %d, data: %d, "
		"recovery: %d, drdy: %d [clk]\n",
		hwif->name, ax, second.data_time,
		second.recovery_time, drdy);
#endif

	spin_lock_irqsave(&opti621_lock, flags);

	reg_base = hwif->io_ports[IDE_DATA_OFFSET];

	/* allow Register-B */
	outb(0xc0, reg_base + CNTRL_REG);
	/* hmm, setupvic.exe does this ;-) */
	outb(0xff, reg_base + 5);
	/* if reads 0xff, adapter not exist? */
	(void)inb(reg_base + CNTRL_REG);
	/* if reads 0xc0, no interface exist? */
	read_reg(CNTRL_REG);
	/* read version, probably 0 */
	read_reg(STRAP_REG);

	/* program primary drive */
	/* select Index-0 for Register-A */
	write_reg(0, MISC_REG);
	/* set read cycle timings */
	write_reg(cycle1, READ_REG);
	/* set write cycle timings */
	write_reg(cycle1, WRITE_REG);

	/* program secondary drive */
	/* select Index-1 for Register-B */
	write_reg(1, MISC_REG);
	/* set read cycle timings */
	write_reg(cycle2, READ_REG);
	/* set write cycle timings */
	write_reg(cycle2, WRITE_REG);

	/* use Register-A for drive 0 */
	/* use Register-B for drive 1 */
	write_reg(0x85, CNTRL_REG);

	/* set address setup, DRDY timings,   */
	/*  and read prefetch for both drives */
	write_reg(misc, MISC_REG);

	spin_unlock_irqrestore(&opti621_lock, flags);
}

static void __devinit opti621_port_init_devs(ide_hwif_t *hwif)
{
	hwif->drives[0].drive_data = PIO_DONT_KNOW;
	hwif->drives[1].drive_data = PIO_DONT_KNOW;
}

/*
 * init_hwif_opti621() is called once for each hwif found at boot.
 */
static void __devinit init_hwif_opti621(ide_hwif_t *hwif)
{
	hwif->port_init_devs = opti621_port_init_devs;
	hwif->set_pio_mode = &opti621_set_pio_mode;
}

static const struct ide_port_info opti621_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "OPTI621",
		.init_hwif	= init_hwif_opti621,
		.enablebits	= { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
		.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA,
		.pio_mask	= ATA_PIO3,
		.swdma_mask	= ATA_SWDMA2,
		.mwdma_mask	= ATA_MWDMA2,
	}, {	/* 1 */
		.name		= "OPTI621X",
		.init_hwif	= init_hwif_opti621,
		.enablebits	= { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
		.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA,
		.pio_mask	= ATA_PIO3,
		.swdma_mask	= ATA_SWDMA2,
		.mwdma_mask	= ATA_MWDMA2,
	}
};

static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]);
}

static const struct pci_device_id opti621_pci_tbl[] = {
	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);

static struct pci_driver driver = {
	.name		= "Opti621_IDE",
	.id_table	= opti621_pci_tbl,
	.probe		= opti621_init_one,
};

static int __init opti621_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(opti621_ide_init);

MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
	3	*/
	4
	5	/*
	6	* Authors:
	7	* Jaromir Koutek <miri@punknet.cz>,
	8	* Jan Harkes <jaharkes@cwi.nl>,
	9	* Mark Lord <mlord@pobox.com>
	10	* Some parts of code are from ali14xx.c and from rz1000.c.
	11	*
	12	* OPTi is trademark of OPTi, Octek is trademark of Octek.
	13	*
	14	* I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
	15	* and disassembled/traced setupvic.exe (DOS program).
	16	* It increases kernel code about 2 kB.
	17	* I don't have this card no more, but I hope I can get some in case
	18	* of needed development.
	19	* My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
	20	* It has a place for a secondary connector in circuit, but nothing
	21	* is there. Also BIOS says no address for
	22	* secondary controller (see bellow in ide_init_opti621).
	23	* I've only tested this on my system, which only has one disk.
	24	* It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
	25	* is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
	26	* lockups). I tried the OCTEK double speed CD-ROM and
	27	* it does not work! But I can't boot DOS also, so it's probably
	28	* hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
	29	* problems) and Seagate 1GB (as slave, WD as master). My experiences
	30	* with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
	31	* it slows to about 100kB/s! I don't know why and I have
	32	* not this drive now, so I can't try it again.
	33	* I write this driver because I lost the paper ("manual") with
	34	* settings of jumpers on the card and I have to boot Linux with
	35	* Loadlin except LILO, cause I have to run the setupvic.exe program
	36	* already or I get disk errors (my test: rpm -Vf
	37	* /usr/X11R6/bin/XF86_SVGA - or any big file).
	38	* Some numbers from hdparm -t /dev/hda:
	39	* Timing buffer-cache reads: 32 MB in 3.02 seconds =10.60 MB/sec
	40	* Timing buffered disk reads: 16 MB in 5.52 seconds = 2.90 MB/sec
	41	* I have 4 Megs/s before, but I don't know why (maybe changes
	42	* in hdparm test).
	43	* After release of 0.1, I got some successful reports, so it might work.
	44	*
	45	* The main problem with OPTi is that some timings for master
	46	* and slave must be the same. For example, if you have master
	47	* PIO 3 and slave PIO 0, driver have to set some timings of
26bcb879	48	* master for PIO 0. Second problem is that opti621_set_pio_mode
1da177e4 LT	49	* got only one drive to set, but have to set both drives.
	50	* This is solved in compute_pios. If you don't set
	51	* the second drive, compute_pios use ide_get_best_pio_mode
	52	* for autoselect mode (you can change it to PIO 0, if you want).
	53	* If you then set the second drive to another PIO, the old value
	54	* (automatically selected) will be overrided by yours.
	55	* There is a 25/33MHz switch in configuration
	56	* register, but driver is written for use at any frequency which get
	57	* (use idebus=xx to select PCI bus speed).
1da177e4 LT	58	*
1da177e4 LT	59	* Version 0.1, Nov 8, 1996
4eb68a25	60	* by Jaromir Koutek, for 2.1.8.
1da177e4	61	* Initial version of driver.
4eb68a25	62	*
1da177e4 LT	63	* Version 0.2
	64	* Number 0.2 skipped.
	65	*
	66	* Version 0.3, Nov 29, 1997
	67	* by Mark Lord (probably), for 2.1.68
	68	* Updates for use with new IDE block driver.
	69	*
	70	* Version 0.4, Dec 14, 1997
	71	* by Jan Harkes
	72	* Fixed some errors and cleaned the code.
	73	*
	74	* Version 0.5, Jan 2, 1998
	75	* by Jaromir Koutek
	76	* Updates for use with (again) new IDE block driver.
	77	* Update of documentation.
4eb68a25	78	*
1da177e4 LT	79	* Version 0.6, Jan 2, 1999
	80	* by Jaromir Koutek
	81	* Reversed to version 0.3 of the driver, because
	82	* 0.5 doesn't work.
	83	*/
	84
1da177e4 LT	85	#define OPTI621_DEBUG /* define for debug messages */
	86
	87	#include <linux/types.h>
	88	#include <linux/module.h>
	89	#include <linux/kernel.h>
1da177e4 LT	90	#include <linux/pci.h>
	91	#include <linux/hdreg.h>
	92	#include <linux/ide.h>
	93
	94	#include <asm/io.h>
	95
26bcb879	96	//#define OPTI621_MAX_PIO 3
1da177e4 LT	97	/* In fact, I do not have any PIO 4 drive
	98	* (address: 25 ns, data: 70 ns, recovery: 35 ns),
	99	* but OPTi 82C621 is programmable and it can do (minimal values):
	100	* on 40MHz PCI bus (pulse 25 ns):
	101	* address: 25 ns, data: 25 ns, recovery: 50 ns;
	102	* on 20MHz PCI bus (pulse 50 ns):
	103	* address: 50 ns, data: 50 ns, recovery: 100 ns.
	104	*/
	105
	106	/* #define READ_PREFETCH 0 */
	107	/* Uncomment for disable read prefetch.
	108	* There is some readprefetch capatibility in hdparm,
	109	* but when I type hdparm -P 1 /dev/hda, I got errors
	110	* and till reset drive is inaccessible.
	111	* This (hw) read prefetch is safe on my drive.
	112	*/
	113
	114	#ifndef READ_PREFETCH
	115	#define READ_PREFETCH 0x40 /* read prefetch is enabled */
	116	#endif /* else read prefetch is disabled */
	117
	118	#define READ_REG 0 /* index of Read cycle timing register */
	119	#define WRITE_REG 1 /* index of Write cycle timing register */
	120	#define CNTRL_REG 3 /* index of Control register */
	121	#define STRAP_REG 5 /* index of Strap register */
	122	#define MISC_REG 6 /* index of Miscellaneous register */
	123
	124	static int reg_base;
	125
	126	#define PIO_NOT_EXIST 254
	127	#define PIO_DONT_KNOW 255
	128
e65dde71 BZ	129	static DEFINE_SPINLOCK(opti621_lock);
e65dde71 BZ	130
26bcb879 BZ	131	/* there are stored pio numbers from other calls of opti621_set_pio_mode */
26bcb879 BZ	132	static void compute_pios(ide_drive_t *drive, const u8 pio)
1da177e4 LT	133	/* Store values into drive->drive_data
	134	* second_contr - 0 for primary controller, 1 for secondary
	135	* slave_drive - 0 -> pio is for master, 1 -> pio is for slave
	136	* pio - PIO mode for selected drive (for other we don't know)
	137	*/
	138	{
	139	int d;
	140	ide_hwif_t *hwif = HWIF(drive);
	141
26bcb879 BZ	142	drive->drive_data = pio;
26bcb879 BZ	143
1da177e4 LT	144	for (d = 0; d < 2; ++d) {
	145	drive = &hwif->drives[d];
	146	if (drive->present) {
	147	if (drive->drive_data == PIO_DONT_KNOW)
26bcb879	148	drive->drive_data = ide_get_best_pio_mode(drive, 255, 3);
1da177e4 LT	149	#ifdef OPTI621_DEBUG
	150	printk("%s: Selected PIO mode %d\n",
	151	drive->name, drive->drive_data);
	152	#endif
	153	} else {
	154	drive->drive_data = PIO_NOT_EXIST;
	155	}
	156	}
	157	}
	158
	159	static int cmpt_clk(int time, int bus_speed)
	160	/* Returns (rounded up) time in clocks for time in ns,
	161	* with bus_speed in MHz.
	162	* Example: bus_speed = 40 MHz, time = 80 ns
	163	* 1000/40 = 25 ns (clk value),
	164	* 80/25 = 3.2, rounded up to 4 (I hope ;-)).
	165	* Use idebus=xx to select right frequency.
	166	*/
	167	{
	168	return ((time*bus_speed+999)/1000);
	169	}
	170
1da177e4 LT	171	/* Write value to register reg, base of register
	172	* is at reg_base (0x1f0 primary, 0x170 secondary,
	173	* if not changed by PCI configuration).
	174	* This is from setupvic.exe program.
	175	*/
0ecdca26	176	static void write_reg(u8 value, int reg)
1da177e4	177	{
0ecdca26 BZ	178	inw(reg_base + 1);
	179	inw(reg_base + 1);
	180	outb(3, reg_base + 2);
	181	outb(value, reg_base + reg);
	182	outb(0x83, reg_base + 2);
1da177e4 LT	183	}
1da177e4 LT	184
1da177e4 LT	185	/* Read value from register reg, base of register
	186	* is at reg_base (0x1f0 primary, 0x170 secondary,
	187	* if not changed by PCI configuration).
	188	* This is from setupvic.exe program.
	189	*/
0ecdca26	190	static u8 read_reg(int reg)
1da177e4 LT	191	{
	192	u8 ret = 0;
	193
0ecdca26 BZ	194	inw(reg_base + 1);
	195	inw(reg_base + 1);
	196	outb(3, reg_base + 2);
	197	ret = inb(reg_base + reg);
	198	outb(0x83, reg_base + 2);
	199
1da177e4 LT	200	return ret;
	201	}
	202
	203	typedef struct pio_clocks_s {
	204	int address_time; /* Address setup (clocks) */
	205	int data_time; /* Active/data pulse (clocks) */
	206	int recovery_time; /* Recovery time (clocks) */
	207	} pio_clocks_t;
	208
	209	static void compute_clocks(int pio, pio_clocks_t *clks)
	210	{
4eb68a25 PC	211	if (pio != PIO_NOT_EXIST) {
4eb68a25 PC	212	int adr_setup, data_pls;
1da177e4 LT	213	int bus_speed = system_bus_clock();
1da177e4 LT	214
4eb68a25 PC	215	adr_setup = ide_pio_timings[pio].setup_time;
	216	data_pls = ide_pio_timings[pio].active_time;
	217	clks->address_time = cmpt_clk(adr_setup, bus_speed);
	218	clks->data_time = cmpt_clk(data_pls, bus_speed);
	219	clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
	220	- adr_setup-data_pls, bus_speed);
	221	if (clks->address_time < 1)
	222	clks->address_time = 1;
	223	if (clks->address_time > 4)
	224	clks->address_time = 4;
	225	if (clks->data_time < 1)
	226	clks->data_time = 1;
	227	if (clks->data_time > 16)
	228	clks->data_time = 16;
	229	if (clks->recovery_time < 2)
	230	clks->recovery_time = 2;
	231	if (clks->recovery_time > 17)
	232	clks->recovery_time = 17;
1da177e4 LT	233	} else {
	234	clks->address_time = 1;
	235	clks->data_time = 1;
	236	clks->recovery_time = 2;
	237	/* minimal values */
	238	}
1da177e4 LT	239	}
1da177e4 LT	240
26bcb879	241	static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	242	{
	243	/* primary and secondary drives share some registers,
	244	* so we have to program both drives
	245	*/
	246	unsigned long flags;
	247	u8 pio1 = 0, pio2 = 0;
	248	pio_clocks_t first, second;
	249	int ax, drdy;
	250	u8 cycle1, cycle2, misc;
	251	ide_hwif_t *hwif = HWIF(drive);
	252
	253	/* sets drive->drive_data for both drives */
	254	compute_pios(drive, pio);
4eb68a25 PC	255	pio1 = hwif->drives[0].drive_data;
4eb68a25 PC	256	pio2 = hwif->drives[1].drive_data;
1da177e4 LT	257
	258	compute_clocks(pio1, &first);
	259	compute_clocks(pio2, &second);
	260
	261	/* ax = max(a1,a2) */
	262	ax = (first.address_time < second.address_time) ? second.address_time : first.address_time;
	263
	264	drdy = 2; /* DRDY is default 2 (by OPTi Databook) */
	265
	266	cycle1 = ((first.data_time-1)<<4) \| (first.recovery_time-2);
	267	cycle2 = ((second.data_time-1)<<4) \| (second.recovery_time-2);
	268	misc = READ_PREFETCH \| ((ax-1)<<4) \| ((drdy-2)<<1);
	269
	270	#ifdef OPTI621_DEBUG
	271	printk("%s: master: address: %d, data: %d, "
	272	"recovery: %d, drdy: %d [clk]\n",
	273	hwif->name, ax, first.data_time,
	274	first.recovery_time, drdy);
	275	printk("%s: slave: address: %d, data: %d, "
	276	"recovery: %d, drdy: %d [clk]\n",
	277	hwif->name, ax, second.data_time,
	278	second.recovery_time, drdy);
	279	#endif
	280
e65dde71	281	spin_lock_irqsave(&opti621_lock, flags);
1da177e4	282
4eb68a25	283	reg_base = hwif->io_ports[IDE_DATA_OFFSET];
1da177e4 LT	284
1da177e4 LT	285	/* allow Register-B */
0ecdca26	286	outb(0xc0, reg_base + CNTRL_REG);
1da177e4	287	/* hmm, setupvic.exe does this ;-) */
0ecdca26	288	outb(0xff, reg_base + 5);
1da177e4	289	/* if reads 0xff, adapter not exist? */
0ecdca26	290	(void)inb(reg_base + CNTRL_REG);
1da177e4	291	/* if reads 0xc0, no interface exist? */
0ecdca26	292	read_reg(CNTRL_REG);
1da177e4	293	/* read version, probably 0 */
0ecdca26	294	read_reg(STRAP_REG);
1da177e4 LT	295
1da177e4 LT	296	/* program primary drive */
0ecdca26 BZ	297	/* select Index-0 for Register-A */
	298	write_reg(0, MISC_REG);
	299	/* set read cycle timings */
	300	write_reg(cycle1, READ_REG);
	301	/* set write cycle timings */
	302	write_reg(cycle1, WRITE_REG);
1da177e4 LT	303
1da177e4 LT	304	/* program secondary drive */
0ecdca26 BZ	305	/* select Index-1 for Register-B */
	306	write_reg(1, MISC_REG);
	307	/* set read cycle timings */
	308	write_reg(cycle2, READ_REG);
	309	/* set write cycle timings */
	310	write_reg(cycle2, WRITE_REG);
1da177e4 LT	311
	312	/* use Register-A for drive 0 */
	313	/* use Register-B for drive 1 */
0ecdca26	314	write_reg(0x85, CNTRL_REG);
1da177e4 LT	315
	316	/* set address setup, DRDY timings, */
	317	/* and read prefetch for both drives */
0ecdca26	318	write_reg(misc, MISC_REG);
1da177e4	319
e65dde71	320	spin_unlock_irqrestore(&opti621_lock, flags);
1da177e4 LT	321	}
1da177e4 LT	322
1f2cf8b0 BZ	323	static void __devinit opti621_port_init_devs(ide_hwif_t *hwif)
	324	{
	325	hwif->drives[0].drive_data = PIO_DONT_KNOW;
	326	hwif->drives[1].drive_data = PIO_DONT_KNOW;
	327	}
	328
1da177e4 LT	329	/*
	330	* init_hwif_opti621() is called once for each hwif found at boot.
	331	*/
4eb68a25	332	static void __devinit init_hwif_opti621(ide_hwif_t *hwif)
1da177e4	333	{
1f2cf8b0	334	hwif->port_init_devs = opti621_port_init_devs;
26bcb879	335	hwif->set_pio_mode = &opti621_set_pio_mode;
1da177e4 LT	336	}
1da177e4 LT	337
85620436	338	static const struct ide_port_info opti621_chipsets[] __devinitdata = {
1da177e4 LT	339	{ /* 0 */
	340	.name = "OPTI621",
	341	.init_hwif = init_hwif_opti621,
4eb68a25	342	.enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
5e71d9c5	343	.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
4099d143	344	.pio_mask = ATA_PIO3,
5f8b6c34 BZ	345	.swdma_mask = ATA_SWDMA2,
5f8b6c34 BZ	346	.mwdma_mask = ATA_MWDMA2,
4eb68a25	347	}, { /* 1 */
1da177e4 LT	348	.name = "OPTI621X",
1da177e4 LT	349	.init_hwif = init_hwif_opti621,
4eb68a25	350	.enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
5e71d9c5	351	.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
4099d143	352	.pio_mask = ATA_PIO3,
5f8b6c34 BZ	353	.swdma_mask = ATA_SWDMA2,
5f8b6c34 BZ	354	.mwdma_mask = ATA_MWDMA2,
1da177e4 LT	355	}
	356	};
	357
	358	static int __devinit opti621_init_one(struct pci_dev dev, const struct pci_device_id id)
	359	{
	360	return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]);
	361	}
	362
9cbcc5e3 BZ	363	static const struct pci_device_id opti621_pci_tbl[] = {
	364	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
	365	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 },
1da177e4 LT	366	{ 0, },
	367	};
	368	MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
	369
	370	static struct pci_driver driver = {
	371	.name = "Opti621_IDE",
	372	.id_table = opti621_pci_tbl,
	373	.probe = opti621_init_one,
	374	};
	375
82ab1eec	376	static int __init opti621_ide_init(void)
1da177e4 LT	377	{
	378	return ide_pci_register_driver(&driver);
	379	}
	380
	381	module_init(opti621_ide_init);
	382
	383	MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
	384	MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
	385	MODULE_LICENSE("GPL");