[mirror_ubuntu-bionic-kernel.git] / drivers / ide / pci / opti621.c

/*
 *  Copyright (C) 1996-1998  Linus Torvalds & authors (see below)
 */

/*
 * Authors:
 * Jaromir Koutek <miri@punknet.cz>,
 * Jan Harkes <jaharkes@cwi.nl>,
 * Mark Lord <mlord@pobox.com>
 * Some parts of code are from ali14xx.c and from rz1000.c.
 *
 * OPTi is trademark of OPTi, Octek is trademark of Octek.
 *
 * I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
 * and disassembled/traced setupvic.exe (DOS program).
 * It increases kernel code about 2 kB.
 * I don't have this card no more, but I hope I can get some in case
 * of needed development.
 * My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
 * It has a place for a secondary connector in circuit, but nothing
 * is there. Also BIOS says no address for
 * secondary controller (see bellow in ide_init_opti621).
 * I've only tested this on my system, which only has one disk.
 * It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
 * is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
 * lockups). I tried the OCTEK double speed CD-ROM and
 * it does not work! But I can't boot DOS also, so it's probably
 * hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
 * problems) and Seagate 1GB (as slave, WD as master). My experiences
 * with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
 * it slows to about 100kB/s! I don't know why and I have
 * not this drive now, so I can't try it again.
 * I write this driver because I lost the paper ("manual") with
 * settings of jumpers on the card and I have to boot Linux with
 * Loadlin except LILO, cause I have to run the setupvic.exe program
 * already or I get disk errors (my test: rpm -Vf
 * /usr/X11R6/bin/XF86_SVGA - or any big file).
 * Some numbers from hdparm -t /dev/hda:
 * Timing buffer-cache reads:   32 MB in  3.02 seconds =10.60 MB/sec
 * Timing buffered disk reads:  16 MB in  5.52 seconds = 2.90 MB/sec
 * I have 4 Megs/s before, but I don't know why (maybe changes
 * in hdparm test).
 * After release of 0.1, I got some successful reports, so it might work.
 *
 * The main problem with OPTi is that some timings for master
 * and slave must be the same. For example, if you have master
 * PIO 3 and slave PIO 0, driver have to set some timings of
 * master for PIO 0. Second problem is that opti621_set_pio_mode
 * got only one drive to set, but have to set both drives.
 * This is solved in compute_pios. If you don't set
 * the second drive, compute_pios use ide_get_best_pio_mode
 * for autoselect mode (you can change it to PIO 0, if you want).
 * If you then set the second drive to another PIO, the old value
 * (automatically selected) will be overrided by yours.
 * There is a 25/33MHz switch in configuration
 * register, but driver is written for use at any frequency.
 *
 * Version 0.1, Nov 8, 1996
 * by Jaromir Koutek, for 2.1.8.
 * Initial version of driver.
 *
 * Version 0.2
 * Number 0.2 skipped.
 *
 * Version 0.3, Nov 29, 1997
 * by Mark Lord (probably), for 2.1.68
 * Updates for use with new IDE block driver.
 *
 * Version 0.4, Dec 14, 1997
 * by Jan Harkes
 * Fixed some errors and cleaned the code.
 *
 * Version 0.5, Jan 2, 1998
 * by Jaromir Koutek
 * Updates for use with (again) new IDE block driver.
 * Update of documentation.
 *
 * Version 0.6, Jan 2, 1999
 * by Jaromir Koutek
 * Reversed to version 0.3 of the driver, because
 * 0.5 doesn't work.
 */

#define OPTI621_DEBUG		/* define for debug messages */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>

#include <asm/io.h>

//#define OPTI621_MAX_PIO 3
/* In fact, I do not have any PIO 4 drive
 * (address: 25 ns, data: 70 ns, recovery: 35 ns),
 * but OPTi 82C621 is programmable and it can do (minimal values):
 * on 40MHz PCI bus (pulse 25 ns):
 *  address: 25 ns, data: 25 ns, recovery: 50 ns;
 * on 20MHz PCI bus (pulse 50 ns):
 *  address: 50 ns, data: 50 ns, recovery: 100 ns.
 */

#define READ_REG 0	/* index of Read cycle timing register */
#define WRITE_REG 1	/* index of Write cycle timing register */
#define CNTRL_REG 3	/* index of Control register */
#define STRAP_REG 5	/* index of Strap register */
#define MISC_REG 6	/* index of Miscellaneous register */

static int reg_base;

#define PIO_NOT_EXIST 254
#define PIO_DONT_KNOW 255

static DEFINE_SPINLOCK(opti621_lock);

static int cmpt_clk(int time, int bus_speed)
/* Returns (rounded up) time in clocks for time in ns,
 * with bus_speed in MHz.
 * Example: bus_speed = 40 MHz, time = 80 ns
 * 1000/40 = 25 ns (clk value),
 * 80/25 = 3.2, rounded up to 4 (I hope ;-)).
 * Use idebus=xx to select right frequency.
 */
{
	return ((time*bus_speed+999)/1000);
}

/* Write value to register reg, base of register
 * is at reg_base (0x1f0 primary, 0x170 secondary,
 * if not changed by PCI configuration).
 * This is from setupvic.exe program.
 */
static void write_reg(u8 value, int reg)
{
	inw(reg_base + 1);
	inw(reg_base + 1);
	outb(3, reg_base + 2);
	outb(value, reg_base + reg);
	outb(0x83, reg_base + 2);
}

/* Read value from register reg, base of register
 * is at reg_base (0x1f0 primary, 0x170 secondary,
 * if not changed by PCI configuration).
 * This is from setupvic.exe program.
 */
static u8 read_reg(int reg)
{
	u8 ret = 0;

	inw(reg_base + 1);
	inw(reg_base + 1);
	outb(3, reg_base + 2);
	ret = inb(reg_base + reg);
	outb(0x83, reg_base + 2);

	return ret;
}

typedef struct pio_clocks_s {
	int	address_time;	/* Address setup (clocks) */
	int	data_time;	/* Active/data pulse (clocks) */
	int	recovery_time;	/* Recovery time (clocks) */
} pio_clocks_t;

static void compute_clocks(int pio, pio_clocks_t *clks, int bus_speed)
{
	if (pio != PIO_NOT_EXIST) {
		int adr_setup, data_pls;

		adr_setup = ide_pio_timings[pio].setup_time;
		data_pls = ide_pio_timings[pio].active_time;
		clks->address_time = cmpt_clk(adr_setup, bus_speed);
		clks->data_time = cmpt_clk(data_pls, bus_speed);
		clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
			- adr_setup-data_pls, bus_speed);
		if (clks->address_time < 1)
			clks->address_time = 1;
		if (clks->address_time > 4)
			clks->address_time = 4;
		if (clks->data_time < 1)
			clks->data_time = 1;
		if (clks->data_time > 16)
			clks->data_time = 16;
		if (clks->recovery_time < 2)
			clks->recovery_time = 2;
		if (clks->recovery_time > 17)
			clks->recovery_time = 17;
	} else {
		clks->address_time = 1;
		clks->data_time = 1;
		clks->recovery_time = 2;
		/* minimal values */
	}
}

static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif = drive->hwif;
	ide_drive_t *pair = ide_get_paired_drive(drive);
	unsigned long flags;
	pio_clocks_t first, second;
	int ax, drdy;
	u8 cycle1, misc, clk, addr_pio = pio;

	drive->drive_data = XFER_PIO_0 + pio;

	if (pair->present) {
		if (pair->drive_data && pair->drive_data < drive->drive_data)
			addr_pio = pair->drive_data - XFER_PIO_0;
	}

	spin_lock_irqsave(&opti621_lock, flags);

	reg_base = hwif->io_ports.data_addr;

	/* allow Register-B */
	outb(0xc0, reg_base + CNTRL_REG);
	/* hmm, setupvic.exe does this ;-) */
	outb(0xff, reg_base + 5);
	/* if reads 0xff, adapter not exist? */
	(void)inb(reg_base + CNTRL_REG);
	/* if reads 0xc0, no interface exist? */
	read_reg(CNTRL_REG);

	/* check CLK speed */
	clk = read_reg(STRAP_REG) & 1;

	printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33);

	compute_clocks(pio, &first, clk ? 25 : 33);
	compute_clocks(addr_pio, &second, clk ? 25 : 33);

	/* ax = max(a1,a2) */
	ax = (first.address_time < second.address_time) ? second.address_time : first.address_time;

	drdy = 2; /* DRDY is default 2 (by OPTi Databook) */

	cycle1 = ((first.data_time-1)<<4)  | (first.recovery_time-2);

	misc = ((ax - 1) << 4) | ((drdy - 2) << 1);

#ifdef OPTI621_DEBUG
	printk("%s: address: %d, data: %d, "
		"recovery: %d, drdy: %d [clk]\n",
		drive->name, ax, first.data_time,
		first.recovery_time, drdy);
#endif

	/* select Index-0/1 for Register-A/B */
	write_reg(drive->select.b.unit, MISC_REG);
	/* set read cycle timings */
	write_reg(cycle1, READ_REG);
	/* set write cycle timings */
	write_reg(cycle1, WRITE_REG);

	/* use Register-A for drive 0 */
	/* use Register-B for drive 1 */
	write_reg(0x85, CNTRL_REG);

	/* set address setup, DRDY timings,   */
	/*  and read prefetch for both drives */
	write_reg(misc, MISC_REG);

	spin_unlock_irqrestore(&opti621_lock, flags);
}

static const struct ide_port_ops opti621_port_ops = {
	.set_pio_mode		= opti621_set_pio_mode,
};

static const struct ide_port_info opti621_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "OPTI621",
		.enablebits	= { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
		.port_ops	= &opti621_port_ops,
		.host_flags	= IDE_HFLAG_NO_DMA,
		.pio_mask	= ATA_PIO3,
	}, {	/* 1 */
		.name		= "OPTI621X",
		.enablebits	= { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
		.port_ops	= &opti621_port_ops,
		.host_flags	= IDE_HFLAG_NO_DMA,
		.pio_mask	= ATA_PIO3,
	}
};

static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]);
}

static const struct pci_device_id opti621_pci_tbl[] = {
	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);

static struct pci_driver driver = {
	.name		= "Opti621_IDE",
	.id_table	= opti621_pci_tbl,
	.probe		= opti621_init_one,
};

static int __init opti621_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(opti621_ide_init);

MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
	3	*/
	4
	5	/*
	6	* Authors:
	7	* Jaromir Koutek <miri@punknet.cz>,
	8	* Jan Harkes <jaharkes@cwi.nl>,
	9	* Mark Lord <mlord@pobox.com>
	10	* Some parts of code are from ali14xx.c and from rz1000.c.
	11	*
	12	* OPTi is trademark of OPTi, Octek is trademark of Octek.
	13	*
	14	* I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
	15	* and disassembled/traced setupvic.exe (DOS program).
	16	* It increases kernel code about 2 kB.
	17	* I don't have this card no more, but I hope I can get some in case
	18	* of needed development.
	19	* My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
	20	* It has a place for a secondary connector in circuit, but nothing
	21	* is there. Also BIOS says no address for
	22	* secondary controller (see bellow in ide_init_opti621).
	23	* I've only tested this on my system, which only has one disk.
	24	* It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
	25	* is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
	26	* lockups). I tried the OCTEK double speed CD-ROM and
	27	* it does not work! But I can't boot DOS also, so it's probably
	28	* hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
	29	* problems) and Seagate 1GB (as slave, WD as master). My experiences
	30	* with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
	31	* it slows to about 100kB/s! I don't know why and I have
	32	* not this drive now, so I can't try it again.
	33	* I write this driver because I lost the paper ("manual") with
	34	* settings of jumpers on the card and I have to boot Linux with
	35	* Loadlin except LILO, cause I have to run the setupvic.exe program
	36	* already or I get disk errors (my test: rpm -Vf
	37	* /usr/X11R6/bin/XF86_SVGA - or any big file).
	38	* Some numbers from hdparm -t /dev/hda:
	39	* Timing buffer-cache reads: 32 MB in 3.02 seconds =10.60 MB/sec
	40	* Timing buffered disk reads: 16 MB in 5.52 seconds = 2.90 MB/sec
	41	* I have 4 Megs/s before, but I don't know why (maybe changes
	42	* in hdparm test).
	43	* After release of 0.1, I got some successful reports, so it might work.
	44	*
	45	* The main problem with OPTi is that some timings for master
	46	* and slave must be the same. For example, if you have master
	47	* PIO 3 and slave PIO 0, driver have to set some timings of
26bcb879	48	* master for PIO 0. Second problem is that opti621_set_pio_mode
1da177e4 LT	49	* got only one drive to set, but have to set both drives.
	50	* This is solved in compute_pios. If you don't set
	51	* the second drive, compute_pios use ide_get_best_pio_mode
	52	* for autoselect mode (you can change it to PIO 0, if you want).
	53	* If you then set the second drive to another PIO, the old value
	54	* (automatically selected) will be overrided by yours.
	55	* There is a 25/33MHz switch in configuration
73f1ad86	56	* register, but driver is written for use at any frequency.
1da177e4 LT	57	*
1da177e4 LT	58	* Version 0.1, Nov 8, 1996
4eb68a25	59	* by Jaromir Koutek, for 2.1.8.
1da177e4	60	* Initial version of driver.
4eb68a25	61	*
1da177e4 LT	62	* Version 0.2
	63	* Number 0.2 skipped.
	64	*
	65	* Version 0.3, Nov 29, 1997
	66	* by Mark Lord (probably), for 2.1.68
	67	* Updates for use with new IDE block driver.
	68	*
	69	* Version 0.4, Dec 14, 1997
	70	* by Jan Harkes
	71	* Fixed some errors and cleaned the code.
	72	*
	73	* Version 0.5, Jan 2, 1998
	74	* by Jaromir Koutek
	75	* Updates for use with (again) new IDE block driver.
	76	* Update of documentation.
4eb68a25	77	*
1da177e4 LT	78	* Version 0.6, Jan 2, 1999
	79	* by Jaromir Koutek
	80	* Reversed to version 0.3 of the driver, because
	81	* 0.5 doesn't work.
	82	*/
	83
1da177e4 LT	84	#define OPTI621_DEBUG /* define for debug messages */
	85
	86	#include <linux/types.h>
	87	#include <linux/module.h>
	88	#include <linux/kernel.h>
1da177e4 LT	89	#include <linux/pci.h>
	90	#include <linux/hdreg.h>
	91	#include <linux/ide.h>
	92
	93	#include <asm/io.h>
	94
26bcb879	95	//#define OPTI621_MAX_PIO 3
1da177e4 LT	96	/* In fact, I do not have any PIO 4 drive
	97	* (address: 25 ns, data: 70 ns, recovery: 35 ns),
	98	* but OPTi 82C621 is programmable and it can do (minimal values):
	99	* on 40MHz PCI bus (pulse 25 ns):
	100	* address: 25 ns, data: 25 ns, recovery: 50 ns;
	101	* on 20MHz PCI bus (pulse 50 ns):
	102	* address: 50 ns, data: 50 ns, recovery: 100 ns.
	103	*/
	104
1da177e4 LT	105	#define READ_REG 0 /* index of Read cycle timing register */
	106	#define WRITE_REG 1 /* index of Write cycle timing register */
	107	#define CNTRL_REG 3 /* index of Control register */
	108	#define STRAP_REG 5 /* index of Strap register */
	109	#define MISC_REG 6 /* index of Miscellaneous register */
	110
	111	static int reg_base;
	112
	113	#define PIO_NOT_EXIST 254
	114	#define PIO_DONT_KNOW 255
	115
e65dde71 BZ	116	static DEFINE_SPINLOCK(opti621_lock);
e65dde71 BZ	117
1da177e4 LT	118	static int cmpt_clk(int time, int bus_speed)
	119	/* Returns (rounded up) time in clocks for time in ns,
	120	* with bus_speed in MHz.
	121	* Example: bus_speed = 40 MHz, time = 80 ns
	122	* 1000/40 = 25 ns (clk value),
	123	* 80/25 = 3.2, rounded up to 4 (I hope ;-)).
	124	* Use idebus=xx to select right frequency.
	125	*/
	126	{
	127	return ((time*bus_speed+999)/1000);
	128	}
	129
1da177e4 LT	130	/* Write value to register reg, base of register
	131	* is at reg_base (0x1f0 primary, 0x170 secondary,
	132	* if not changed by PCI configuration).
	133	* This is from setupvic.exe program.
	134	*/
0ecdca26	135	static void write_reg(u8 value, int reg)
1da177e4	136	{
0ecdca26 BZ	137	inw(reg_base + 1);
	138	inw(reg_base + 1);
	139	outb(3, reg_base + 2);
	140	outb(value, reg_base + reg);
	141	outb(0x83, reg_base + 2);
1da177e4 LT	142	}
1da177e4 LT	143
1da177e4 LT	144	/* Read value from register reg, base of register
	145	* is at reg_base (0x1f0 primary, 0x170 secondary,
	146	* if not changed by PCI configuration).
	147	* This is from setupvic.exe program.
	148	*/
0ecdca26	149	static u8 read_reg(int reg)
1da177e4 LT	150	{
	151	u8 ret = 0;
	152
0ecdca26 BZ	153	inw(reg_base + 1);
	154	inw(reg_base + 1);
	155	outb(3, reg_base + 2);
	156	ret = inb(reg_base + reg);
	157	outb(0x83, reg_base + 2);
	158
1da177e4 LT	159	return ret;
	160	}
	161
	162	typedef struct pio_clocks_s {
	163	int address_time; /* Address setup (clocks) */
	164	int data_time; /* Active/data pulse (clocks) */
	165	int recovery_time; /* Recovery time (clocks) */
	166	} pio_clocks_t;
	167
21bd33a6	168	static void compute_clocks(int pio, pio_clocks_t *clks, int bus_speed)
1da177e4	169	{
4eb68a25 PC	170	if (pio != PIO_NOT_EXIST) {
4eb68a25 PC	171	int adr_setup, data_pls;
1da177e4	172
4eb68a25 PC	173	adr_setup = ide_pio_timings[pio].setup_time;
	174	data_pls = ide_pio_timings[pio].active_time;
	175	clks->address_time = cmpt_clk(adr_setup, bus_speed);
	176	clks->data_time = cmpt_clk(data_pls, bus_speed);
	177	clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
	178	- adr_setup-data_pls, bus_speed);
	179	if (clks->address_time < 1)
	180	clks->address_time = 1;
	181	if (clks->address_time > 4)
	182	clks->address_time = 4;
	183	if (clks->data_time < 1)
	184	clks->data_time = 1;
	185	if (clks->data_time > 16)
	186	clks->data_time = 16;
	187	if (clks->recovery_time < 2)
	188	clks->recovery_time = 2;
	189	if (clks->recovery_time > 17)
	190	clks->recovery_time = 17;
1da177e4 LT	191	} else {
	192	clks->address_time = 1;
	193	clks->data_time = 1;
	194	clks->recovery_time = 2;
	195	/* minimal values */
	196	}
1da177e4 LT	197	}
1da177e4 LT	198
26bcb879	199	static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	200	{
6c987183 BZ	201	ide_hwif_t *hwif = drive->hwif;
6c987183 BZ	202	ide_drive_t *pair = ide_get_paired_drive(drive);
1da177e4	203	unsigned long flags;
1da177e4 LT	204	pio_clocks_t first, second;
1da177e4 LT	205	int ax, drdy;
6c987183	206	u8 cycle1, misc, clk, addr_pio = pio;
1da177e4	207
6c987183 BZ	208	drive->drive_data = XFER_PIO_0 + pio;
	209
	210	if (pair->present) {
	211	if (pair->drive_data && pair->drive_data < drive->drive_data)
	212	addr_pio = pair->drive_data - XFER_PIO_0;
	213	}
1da177e4	214
21bd33a6 BZ	215	spin_lock_irqsave(&opti621_lock, flags);
	216
	217	reg_base = hwif->io_ports.data_addr;
	218
	219	/* allow Register-B */
	220	outb(0xc0, reg_base + CNTRL_REG);
	221	/* hmm, setupvic.exe does this ;-) */
	222	outb(0xff, reg_base + 5);
	223	/* if reads 0xff, adapter not exist? */
	224	(void)inb(reg_base + CNTRL_REG);
	225	/* if reads 0xc0, no interface exist? */
	226	read_reg(CNTRL_REG);
	227
	228	/* check CLK speed */
	229	clk = read_reg(STRAP_REG) & 1;
	230
	231	printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33);
	232
6c987183 BZ	233	compute_clocks(pio, &first, clk ? 25 : 33);
6c987183 BZ	234	compute_clocks(addr_pio, &second, clk ? 25 : 33);
1da177e4 LT	235
	236	/* ax = max(a1,a2) */
	237	ax = (first.address_time < second.address_time) ? second.address_time : first.address_time;
	238
	239	drdy = 2; /* DRDY is default 2 (by OPTi Databook) */
	240
	241	cycle1 = ((first.data_time-1)<<4) \| (first.recovery_time-2);
62128b2c BZ	242
62128b2c BZ	243	misc = ((ax - 1) << 4) \| ((drdy - 2) << 1);
1da177e4 LT	244
1da177e4 LT	245	#ifdef OPTI621_DEBUG
6c987183	246	printk("%s: address: %d, data: %d, "
1da177e4	247	"recovery: %d, drdy: %d [clk]\n",
6c987183	248	drive->name, ax, first.data_time,
1da177e4	249	first.recovery_time, drdy);
1da177e4 LT	250	#endif
1da177e4 LT	251
6c987183 BZ	252	/* select Index-0/1 for Register-A/B */
6c987183 BZ	253	write_reg(drive->select.b.unit, MISC_REG);
0ecdca26 BZ	254	/* set read cycle timings */
	255	write_reg(cycle1, READ_REG);
	256	/* set write cycle timings */
	257	write_reg(cycle1, WRITE_REG);
1da177e4	258
1da177e4 LT	259	/* use Register-A for drive 0 */
1da177e4 LT	260	/* use Register-B for drive 1 */
0ecdca26	261	write_reg(0x85, CNTRL_REG);
1da177e4 LT	262
	263	/* set address setup, DRDY timings, */
	264	/* and read prefetch for both drives */
0ecdca26	265	write_reg(misc, MISC_REG);
1da177e4	266
e65dde71	267	spin_unlock_irqrestore(&opti621_lock, flags);
1da177e4 LT	268	}
1da177e4 LT	269
ac95beed	270	static const struct ide_port_ops opti621_port_ops = {
ac95beed BZ	271	.set_pio_mode = opti621_set_pio_mode,
ac95beed BZ	272	};
1da177e4	273
85620436	274	static const struct ide_port_info opti621_chipsets[] __devinitdata = {
1da177e4 LT	275	{ /* 0 */
1da177e4 LT	276	.name = "OPTI621",
4eb68a25	277	.enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
ac95beed	278	.port_ops = &opti621_port_ops,
f3610376	279	.host_flags = IDE_HFLAG_NO_DMA,
4099d143	280	.pio_mask = ATA_PIO3,
4eb68a25	281	}, { /* 1 */
1da177e4	282	.name = "OPTI621X",
4eb68a25	283	.enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
ac95beed	284	.port_ops = &opti621_port_ops,
f3610376	285	.host_flags = IDE_HFLAG_NO_DMA,
4099d143	286	.pio_mask = ATA_PIO3,
1da177e4 LT	287	}
	288	};
	289
	290	static int __devinit opti621_init_one(struct pci_dev dev, const struct pci_device_id id)
	291	{
	292	return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]);
	293	}
	294
9cbcc5e3 BZ	295	static const struct pci_device_id opti621_pci_tbl[] = {
	296	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
	297	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 },
1da177e4 LT	298	{ 0, },
	299	};
	300	MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
	301
	302	static struct pci_driver driver = {
	303	.name = "Opti621_IDE",
	304	.id_table = opti621_pci_tbl,
	305	.probe = opti621_init_one,
	306	};
	307
82ab1eec	308	static int __init opti621_ide_init(void)
1da177e4 LT	309	{
	310	return ide_pci_register_driver(&driver);
	311	}
	312
	313	module_init(opti621_ide_init);
	314
	315	MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
	316	MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
	317	MODULE_LICENSE("GPL");