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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Promise TX2/TX4/TX2000/133 IDE driver | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Split from: | |
10 | * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002 | |
11 | * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> | |
35198234 | 12 | * Copyright (C) 2005-2007 MontaVista Software, Inc. |
1da177e4 LT |
13 | * Portions Copyright (C) 1999 Promise Technology, Inc. |
14 | * Author: Frank Tiernan (frankt@promise.com) | |
15 | * Released under terms of General Public License | |
16 | */ | |
17 | ||
1da177e4 LT |
18 | #include <linux/module.h> |
19 | #include <linux/types.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/delay.h> | |
1da177e4 | 22 | #include <linux/hdreg.h> |
1da177e4 LT |
23 | #include <linux/pci.h> |
24 | #include <linux/init.h> | |
25 | #include <linux/ide.h> | |
26 | ||
27 | #include <asm/io.h> | |
1da177e4 LT |
28 | |
29 | #ifdef CONFIG_PPC_PMAC | |
30 | #include <asm/prom.h> | |
31 | #include <asm/pci-bridge.h> | |
32 | #endif | |
33 | ||
ced3ec8a BZ |
34 | #define DRV_NAME "pdc202xx_new" |
35 | ||
47694bb8 SS |
36 | #undef DEBUG |
37 | ||
38 | #ifdef DEBUG | |
eb63963a | 39 | #define DBG(fmt, args...) printk("%s: " fmt, __func__, ## args) |
47694bb8 SS |
40 | #else |
41 | #define DBG(fmt, args...) | |
42 | #endif | |
43 | ||
3c6bee1d | 44 | static const char *pdc_quirk_drives[] = { |
1da177e4 LT |
45 | "QUANTUM FIREBALLlct08 08", |
46 | "QUANTUM FIREBALLP KA6.4", | |
47 | "QUANTUM FIREBALLP KA9.1", | |
48 | "QUANTUM FIREBALLP LM20.4", | |
49 | "QUANTUM FIREBALLP KX13.6", | |
50 | "QUANTUM FIREBALLP KX20.5", | |
51 | "QUANTUM FIREBALLP KX27.3", | |
52 | "QUANTUM FIREBALLP LM20.5", | |
53 | NULL | |
54 | }; | |
55 | ||
47694bb8 | 56 | static u8 max_dma_rate(struct pci_dev *pdev) |
1da177e4 LT |
57 | { |
58 | u8 mode; | |
59 | ||
47694bb8 | 60 | switch(pdev->device) { |
1da177e4 LT |
61 | case PCI_DEVICE_ID_PROMISE_20277: |
62 | case PCI_DEVICE_ID_PROMISE_20276: | |
63 | case PCI_DEVICE_ID_PROMISE_20275: | |
64 | case PCI_DEVICE_ID_PROMISE_20271: | |
65 | case PCI_DEVICE_ID_PROMISE_20269: | |
66 | mode = 4; | |
67 | break; | |
68 | case PCI_DEVICE_ID_PROMISE_20270: | |
69 | case PCI_DEVICE_ID_PROMISE_20268: | |
70 | mode = 3; | |
71 | break; | |
72 | default: | |
73 | return 0; | |
74 | } | |
47694bb8 | 75 | |
1da177e4 LT |
76 | return mode; |
77 | } | |
78 | ||
47694bb8 SS |
79 | /** |
80 | * get_indexed_reg - Get indexed register | |
81 | * @hwif: for the port address | |
82 | * @index: index of the indexed register | |
83 | */ | |
84 | static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index) | |
85 | { | |
86 | u8 value; | |
87 | ||
41051a14 BZ |
88 | outb(index, hwif->dma_base + 1); |
89 | value = inb(hwif->dma_base + 3); | |
47694bb8 SS |
90 | |
91 | DBG("index[%02X] value[%02X]\n", index, value); | |
92 | return value; | |
93 | } | |
94 | ||
95 | /** | |
96 | * set_indexed_reg - Set indexed register | |
97 | * @hwif: for the port address | |
98 | * @index: index of the indexed register | |
99 | */ | |
100 | static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value) | |
101 | { | |
41051a14 BZ |
102 | outb(index, hwif->dma_base + 1); |
103 | outb(value, hwif->dma_base + 3); | |
47694bb8 SS |
104 | DBG("index[%02X] value[%02X]\n", index, value); |
105 | } | |
106 | ||
107 | /* | |
108 | * ATA Timing Tables based on 133 MHz PLL output clock. | |
109 | * | |
110 | * If the PLL outputs 100 MHz clock, the ASIC hardware will set | |
111 | * the timing registers automatically when "set features" command is | |
112 | * issued to the device. However, if the PLL output clock is 133 MHz, | |
113 | * the following tables must be used. | |
114 | */ | |
115 | static struct pio_timing { | |
116 | u8 reg0c, reg0d, reg13; | |
117 | } pio_timings [] = { | |
118 | { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */ | |
119 | { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */ | |
120 | { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */ | |
121 | { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */ | |
122 | { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ | |
123 | }; | |
124 | ||
125 | static struct mwdma_timing { | |
126 | u8 reg0e, reg0f; | |
127 | } mwdma_timings [] = { | |
128 | { 0xdf, 0x5f }, /* MWDMA mode 0 */ | |
129 | { 0x6b, 0x27 }, /* MWDMA mode 1 */ | |
130 | { 0x69, 0x25 }, /* MWDMA mode 2 */ | |
131 | }; | |
132 | ||
133 | static struct udma_timing { | |
134 | u8 reg10, reg11, reg12; | |
135 | } udma_timings [] = { | |
136 | { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ | |
137 | { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */ | |
138 | { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */ | |
139 | { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */ | |
140 | { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */ | |
141 | { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */ | |
142 | { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ | |
143 | }; | |
144 | ||
ad4ba7dc | 145 | static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
146 | { |
147 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 148 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
47694bb8 | 149 | u8 adj = (drive->dn & 1) ? 0x08 : 0x00; |
1da177e4 | 150 | |
47694bb8 | 151 | /* |
88b2b32b BZ |
152 | * IDE core issues SETFEATURES_XFER to the drive first (thanks to |
153 | * IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will | |
47694bb8 | 154 | * automatically set the timing registers based on 100 MHz PLL output. |
88b2b32b | 155 | * |
47694bb8 SS |
156 | * As we set up the PLL to output 133 MHz for UltraDMA/133 capable |
157 | * chips, we must override the default register settings... | |
158 | */ | |
36501650 | 159 | if (max_dma_rate(dev) == 4) { |
47694bb8 SS |
160 | u8 mode = speed & 0x07; |
161 | ||
4db90a14 BZ |
162 | if (speed >= XFER_UDMA_0) { |
163 | set_indexed_reg(hwif, 0x10 + adj, | |
164 | udma_timings[mode].reg10); | |
165 | set_indexed_reg(hwif, 0x11 + adj, | |
166 | udma_timings[mode].reg11); | |
167 | set_indexed_reg(hwif, 0x12 + adj, | |
168 | udma_timings[mode].reg12); | |
169 | } else { | |
170 | set_indexed_reg(hwif, 0x0e + adj, | |
171 | mwdma_timings[mode].reg0e); | |
172 | set_indexed_reg(hwif, 0x0f + adj, | |
173 | mwdma_timings[mode].reg0f); | |
47694bb8 SS |
174 | } |
175 | } else if (speed == XFER_UDMA_2) { | |
176 | /* Set tHOLD bit to 0 if using UDMA mode 2 */ | |
177 | u8 tmp = get_indexed_reg(hwif, 0x10 + adj); | |
178 | ||
179 | set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f); | |
180 | } | |
1da177e4 LT |
181 | } |
182 | ||
26bcb879 | 183 | static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 184 | { |
ad4ba7dc | 185 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 186 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
ad4ba7dc BZ |
187 | u8 adj = (drive->dn & 1) ? 0x08 : 0x00; |
188 | ||
36501650 | 189 | if (max_dma_rate(dev) == 4) { |
ad4ba7dc BZ |
190 | set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c); |
191 | set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d); | |
192 | set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13); | |
193 | } | |
1da177e4 LT |
194 | } |
195 | ||
f454cbe8 | 196 | static u8 pdcnew_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 197 | { |
49521f97 BZ |
198 | if (get_indexed_reg(hwif, 0x0b) & 0x04) |
199 | return ATA_CBL_PATA40; | |
200 | else | |
201 | return ATA_CBL_PATA80; | |
1da177e4 | 202 | } |
47694bb8 | 203 | |
f01393e4 | 204 | static void pdcnew_quirkproc(ide_drive_t *drive) |
1da177e4 | 205 | { |
d24ec426 SS |
206 | const char **list, *model = drive->id->model; |
207 | ||
208 | for (list = pdc_quirk_drives; *list != NULL; list++) | |
f01393e4 BZ |
209 | if (strstr(model, *list) != NULL) { |
210 | drive->quirk_list = 2; | |
211 | return; | |
212 | } | |
213 | ||
214 | drive->quirk_list = 0; | |
1da177e4 LT |
215 | } |
216 | ||
47694bb8 | 217 | static void pdcnew_reset(ide_drive_t *drive) |
1da177e4 LT |
218 | { |
219 | /* | |
220 | * Deleted this because it is redundant from the caller. | |
221 | */ | |
47694bb8 | 222 | printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n", |
1da177e4 LT |
223 | HWIF(drive)->channel ? "Secondary" : "Primary"); |
224 | } | |
225 | ||
47694bb8 SS |
226 | /** |
227 | * read_counter - Read the byte count registers | |
228 | * @dma_base: for the port address | |
229 | */ | |
230 | static long __devinit read_counter(u32 dma_base) | |
231 | { | |
232 | u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08; | |
233 | u8 cnt0, cnt1, cnt2, cnt3; | |
234 | long count = 0, last; | |
235 | int retry = 3; | |
236 | ||
237 | do { | |
238 | last = count; | |
239 | ||
240 | /* Read the current count */ | |
241 | outb(0x20, pri_dma_base + 0x01); | |
242 | cnt0 = inb(pri_dma_base + 0x03); | |
243 | outb(0x21, pri_dma_base + 0x01); | |
244 | cnt1 = inb(pri_dma_base + 0x03); | |
245 | outb(0x20, sec_dma_base + 0x01); | |
246 | cnt2 = inb(sec_dma_base + 0x03); | |
247 | outb(0x21, sec_dma_base + 0x01); | |
248 | cnt3 = inb(sec_dma_base + 0x03); | |
249 | ||
250 | count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0; | |
251 | ||
252 | /* | |
253 | * The 30-bit decrementing counter is read in 4 pieces. | |
254 | * Incorrect value may be read when the most significant bytes | |
255 | * are changing... | |
256 | */ | |
257 | } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count)); | |
258 | ||
259 | DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n", | |
260 | cnt0, cnt1, cnt2, cnt3); | |
261 | ||
262 | return count; | |
263 | } | |
264 | ||
265 | /** | |
266 | * detect_pll_input_clock - Detect the PLL input clock in Hz. | |
267 | * @dma_base: for the port address | |
268 | * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock. | |
269 | */ | |
270 | static long __devinit detect_pll_input_clock(unsigned long dma_base) | |
271 | { | |
8006bf56 | 272 | struct timeval start_time, end_time; |
47694bb8 | 273 | long start_count, end_count; |
8006bf56 | 274 | long pll_input, usec_elapsed; |
47694bb8 SS |
275 | u8 scr1; |
276 | ||
277 | start_count = read_counter(dma_base); | |
8006bf56 | 278 | do_gettimeofday(&start_time); |
47694bb8 SS |
279 | |
280 | /* Start the test mode */ | |
281 | outb(0x01, dma_base + 0x01); | |
282 | scr1 = inb(dma_base + 0x03); | |
283 | DBG("scr1[%02X]\n", scr1); | |
284 | outb(scr1 | 0x40, dma_base + 0x03); | |
285 | ||
286 | /* Let the counter run for 10 ms. */ | |
287 | mdelay(10); | |
288 | ||
289 | end_count = read_counter(dma_base); | |
8006bf56 | 290 | do_gettimeofday(&end_time); |
47694bb8 SS |
291 | |
292 | /* Stop the test mode */ | |
293 | outb(0x01, dma_base + 0x01); | |
294 | scr1 = inb(dma_base + 0x03); | |
295 | DBG("scr1[%02X]\n", scr1); | |
296 | outb(scr1 & ~0x40, dma_base + 0x03); | |
297 | ||
298 | /* | |
299 | * Calculate the input clock in Hz | |
300 | * (the clock counter is 30 bit wide and counts down) | |
301 | */ | |
8006bf56 AL |
302 | usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 + |
303 | (end_time.tv_usec - start_time.tv_usec); | |
56fe23d5 | 304 | pll_input = ((start_count - end_count) & 0x3fffffff) / 10 * |
8006bf56 | 305 | (10000000 / usec_elapsed); |
47694bb8 SS |
306 | |
307 | DBG("start[%ld] end[%ld]\n", start_count, end_count); | |
308 | ||
309 | return pll_input; | |
310 | } | |
311 | ||
1da177e4 LT |
312 | #ifdef CONFIG_PPC_PMAC |
313 | static void __devinit apple_kiwi_init(struct pci_dev *pdev) | |
314 | { | |
315 | struct device_node *np = pci_device_to_OF_node(pdev); | |
1da177e4 LT |
316 | u8 conf; |
317 | ||
55b61fec | 318 | if (np == NULL || !of_device_is_compatible(np, "kiwi-root")) |
1da177e4 LT |
319 | return; |
320 | ||
fc212bb1 | 321 | if (pdev->revision >= 0x03) { |
1da177e4 | 322 | /* Setup chip magic config stuff (from darwin) */ |
47694bb8 SS |
323 | pci_read_config_byte (pdev, 0x40, &conf); |
324 | pci_write_config_byte(pdev, 0x40, (conf | 0x01)); | |
1da177e4 | 325 | } |
1da177e4 LT |
326 | } |
327 | #endif /* CONFIG_PPC_PMAC */ | |
328 | ||
a326b02b | 329 | static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev) |
1da177e4 | 330 | { |
a326b02b | 331 | const char *name = DRV_NAME; |
47694bb8 SS |
332 | unsigned long dma_base = pci_resource_start(dev, 4); |
333 | unsigned long sec_dma_base = dma_base + 0x08; | |
334 | long pll_input, pll_output, ratio; | |
335 | int f, r; | |
336 | u8 pll_ctl0, pll_ctl1; | |
337 | ||
01cc643a BZ |
338 | if (dma_base == 0) |
339 | return -EFAULT; | |
340 | ||
1da177e4 LT |
341 | #ifdef CONFIG_PPC_PMAC |
342 | apple_kiwi_init(dev); | |
343 | #endif | |
344 | ||
47694bb8 SS |
345 | /* Calculate the required PLL output frequency */ |
346 | switch(max_dma_rate(dev)) { | |
347 | case 4: /* it's 133 MHz for Ultra133 chips */ | |
348 | pll_output = 133333333; | |
349 | break; | |
350 | case 3: /* and 100 MHz for Ultra100 chips */ | |
351 | default: | |
352 | pll_output = 100000000; | |
353 | break; | |
354 | } | |
355 | ||
356 | /* | |
357 | * Detect PLL input clock. | |
358 | * On some systems, where PCI bus is running at non-standard clock rate | |
359 | * (e.g. 25 or 40 MHz), we have to adjust the cycle time. | |
360 | * PDC20268 and newer chips employ PLL circuit to help correct timing | |
361 | * registers setting. | |
362 | */ | |
363 | pll_input = detect_pll_input_clock(dma_base); | |
28cfd8af BZ |
364 | printk(KERN_INFO "%s %s: PLL input clock is %ld kHz\n", |
365 | name, pci_name(dev), pll_input / 1000); | |
47694bb8 SS |
366 | |
367 | /* Sanity check */ | |
368 | if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) { | |
28cfd8af BZ |
369 | printk(KERN_ERR "%s %s: Bad PLL input clock %ld Hz, giving up!" |
370 | "\n", name, pci_name(dev), pll_input); | |
47694bb8 SS |
371 | goto out; |
372 | } | |
373 | ||
374 | #ifdef DEBUG | |
375 | DBG("pll_output is %ld Hz\n", pll_output); | |
376 | ||
377 | /* Show the current clock value of PLL control register | |
378 | * (maybe already configured by the BIOS) | |
379 | */ | |
380 | outb(0x02, sec_dma_base + 0x01); | |
381 | pll_ctl0 = inb(sec_dma_base + 0x03); | |
382 | outb(0x03, sec_dma_base + 0x01); | |
383 | pll_ctl1 = inb(sec_dma_base + 0x03); | |
384 | ||
385 | DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1); | |
386 | #endif | |
387 | ||
388 | /* | |
389 | * Calculate the ratio of F, R and NO | |
390 | * POUT = (F + 2) / (( R + 2) * NO) | |
391 | */ | |
392 | ratio = pll_output / (pll_input / 1000); | |
393 | if (ratio < 8600L) { /* 8.6x */ | |
394 | /* Using NO = 0x01, R = 0x0d */ | |
395 | r = 0x0d; | |
396 | } else if (ratio < 12900L) { /* 12.9x */ | |
397 | /* Using NO = 0x01, R = 0x08 */ | |
398 | r = 0x08; | |
399 | } else if (ratio < 16100L) { /* 16.1x */ | |
400 | /* Using NO = 0x01, R = 0x06 */ | |
401 | r = 0x06; | |
402 | } else if (ratio < 64000L) { /* 64x */ | |
403 | r = 0x00; | |
404 | } else { | |
405 | /* Invalid ratio */ | |
28cfd8af BZ |
406 | printk(KERN_ERR "%s %s: Bad ratio %ld, giving up!\n", |
407 | name, pci_name(dev), ratio); | |
47694bb8 SS |
408 | goto out; |
409 | } | |
410 | ||
411 | f = (ratio * (r + 2)) / 1000 - 2; | |
412 | ||
413 | DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio); | |
414 | ||
415 | if (unlikely(f < 0 || f > 127)) { | |
416 | /* Invalid F */ | |
28cfd8af BZ |
417 | printk(KERN_ERR "%s %s: F[%d] invalid!\n", |
418 | name, pci_name(dev), f); | |
47694bb8 SS |
419 | goto out; |
420 | } | |
421 | ||
422 | pll_ctl0 = (u8) f; | |
423 | pll_ctl1 = (u8) r; | |
424 | ||
425 | DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1); | |
426 | ||
427 | outb(0x02, sec_dma_base + 0x01); | |
428 | outb(pll_ctl0, sec_dma_base + 0x03); | |
429 | outb(0x03, sec_dma_base + 0x01); | |
430 | outb(pll_ctl1, sec_dma_base + 0x03); | |
431 | ||
432 | /* Wait the PLL circuit to be stable */ | |
433 | mdelay(30); | |
434 | ||
435 | #ifdef DEBUG | |
436 | /* | |
437 | * Show the current clock value of PLL control register | |
438 | */ | |
439 | outb(0x02, sec_dma_base + 0x01); | |
440 | pll_ctl0 = inb(sec_dma_base + 0x03); | |
441 | outb(0x03, sec_dma_base + 0x01); | |
442 | pll_ctl1 = inb(sec_dma_base + 0x03); | |
443 | ||
444 | DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1); | |
445 | #endif | |
446 | ||
447 | out: | |
1da177e4 LT |
448 | return dev->irq; |
449 | } | |
450 | ||
099b1f42 | 451 | static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev) |
1da177e4 | 452 | { |
099b1f42 BZ |
453 | struct pci_dev *dev2; |
454 | ||
eadb6ecf | 455 | dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1, |
099b1f42 | 456 | PCI_FUNC(dev->devfn))); |
eadb6ecf | 457 | |
099b1f42 BZ |
458 | if (dev2 && |
459 | dev2->vendor == dev->vendor && | |
460 | dev2->device == dev->device) { | |
461 | ||
462 | if (dev2->irq != dev->irq) { | |
463 | dev2->irq = dev->irq; | |
ced3ec8a | 464 | printk(KERN_INFO DRV_NAME " %s: PCI config space " |
28cfd8af | 465 | "interrupt fixed\n", pci_name(dev)); |
1da177e4 | 466 | } |
07047935 | 467 | |
099b1f42 | 468 | return dev2; |
1da177e4 | 469 | } |
099b1f42 BZ |
470 | |
471 | return NULL; | |
1da177e4 LT |
472 | } |
473 | ||
ac95beed BZ |
474 | static const struct ide_port_ops pdcnew_port_ops = { |
475 | .set_pio_mode = pdcnew_set_pio_mode, | |
476 | .set_dma_mode = pdcnew_set_dma_mode, | |
477 | .quirkproc = pdcnew_quirkproc, | |
478 | .resetproc = pdcnew_reset, | |
479 | .cable_detect = pdcnew_cable_detect, | |
480 | }; | |
481 | ||
ced3ec8a | 482 | #define DECLARE_PDCNEW_DEV(udma) \ |
05d7e6cb | 483 | { \ |
ced3ec8a | 484 | .name = DRV_NAME, \ |
05d7e6cb | 485 | .init_chipset = init_chipset_pdcnew, \ |
ac95beed | 486 | .port_ops = &pdcnew_port_ops, \ |
05d7e6cb | 487 | .host_flags = IDE_HFLAG_POST_SET_MODE | \ |
ed67b923 | 488 | IDE_HFLAG_ERROR_STOPS_FIFO | \ |
05d7e6cb BZ |
489 | IDE_HFLAG_OFF_BOARD, \ |
490 | .pio_mask = ATA_PIO4, \ | |
491 | .mwdma_mask = ATA_MWDMA2, \ | |
492 | .udma_mask = udma, \ | |
1da177e4 | 493 | } |
05d7e6cb | 494 | |
85620436 | 495 | static const struct ide_port_info pdcnew_chipsets[] __devinitdata = { |
ced3ec8a BZ |
496 | /* 0: PDC202{68,70} */ DECLARE_PDCNEW_DEV(ATA_UDMA5), |
497 | /* 1: PDC202{69,71,75,76,77} */ DECLARE_PDCNEW_DEV(ATA_UDMA6), | |
1da177e4 LT |
498 | }; |
499 | ||
500 | /** | |
501 | * pdc202new_init_one - called when a pdc202xx is found | |
502 | * @dev: the pdc202new device | |
503 | * @id: the matching pci id | |
504 | * | |
505 | * Called when the PCI registration layer (or the IDE initialization) | |
506 | * finds a device matching our IDE device tables. | |
507 | */ | |
508 | ||
509 | static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
510 | { | |
ced3ec8a | 511 | const struct ide_port_info *d = &pdcnew_chipsets[id->driver_data]; |
099b1f42 | 512 | struct pci_dev *bridge = dev->bus->self; |
099b1f42 | 513 | |
ced3ec8a | 514 | if (dev->device == PCI_DEVICE_ID_PROMISE_20270 && bridge && |
099b1f42 BZ |
515 | bridge->vendor == PCI_VENDOR_ID_DEC && |
516 | bridge->device == PCI_DEVICE_ID_DEC_21150) { | |
517 | struct pci_dev *dev2; | |
518 | ||
519 | if (PCI_SLOT(dev->devfn) & 2) | |
520 | return -ENODEV; | |
1da177e4 | 521 | |
099b1f42 BZ |
522 | dev2 = pdc20270_get_dev2(dev); |
523 | ||
524 | if (dev2) { | |
6cdf6eb3 | 525 | int ret = ide_pci_init_two(dev, dev2, d, NULL); |
099b1f42 BZ |
526 | if (ret < 0) |
527 | pci_dev_put(dev2); | |
528 | return ret; | |
529 | } | |
530 | } | |
531 | ||
ced3ec8a | 532 | if (dev->device == PCI_DEVICE_ID_PROMISE_20276 && bridge && |
099b1f42 BZ |
533 | bridge->vendor == PCI_VENDOR_ID_INTEL && |
534 | (bridge->device == PCI_DEVICE_ID_INTEL_I960 || | |
535 | bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) { | |
ced3ec8a | 536 | printk(KERN_INFO DRV_NAME " %s: attached to I2O RAID controller," |
28cfd8af | 537 | " skipping\n", pci_name(dev)); |
099b1f42 BZ |
538 | return -ENODEV; |
539 | } | |
540 | ||
6cdf6eb3 | 541 | return ide_pci_init_one(dev, d, NULL); |
1da177e4 LT |
542 | } |
543 | ||
d69c8f8c BZ |
544 | static void __devexit pdc202new_remove(struct pci_dev *dev) |
545 | { | |
546 | struct ide_host *host = pci_get_drvdata(dev); | |
547 | struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL; | |
548 | ||
549 | ide_pci_remove(dev); | |
550 | pci_dev_put(dev2); | |
551 | } | |
552 | ||
9cbcc5e3 BZ |
553 | static const struct pci_device_id pdc202new_pci_tbl[] = { |
554 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 }, | |
555 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 }, | |
ced3ec8a BZ |
556 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 0 }, |
557 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 1 }, | |
558 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 1 }, | |
559 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 1 }, | |
560 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 1 }, | |
1da177e4 LT |
561 | { 0, }, |
562 | }; | |
563 | MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl); | |
564 | ||
565 | static struct pci_driver driver = { | |
566 | .name = "Promise_IDE", | |
567 | .id_table = pdc202new_pci_tbl, | |
568 | .probe = pdc202new_init_one, | |
d69c8f8c | 569 | .remove = pdc202new_remove, |
1da177e4 LT |
570 | }; |
571 | ||
82ab1eec | 572 | static int __init pdc202new_ide_init(void) |
1da177e4 LT |
573 | { |
574 | return ide_pci_register_driver(&driver); | |
575 | } | |
576 | ||
d69c8f8c BZ |
577 | static void __exit pdc202new_ide_exit(void) |
578 | { | |
579 | pci_unregister_driver(&driver); | |
580 | } | |
581 | ||
1da177e4 | 582 | module_init(pdc202new_ide_init); |
d69c8f8c | 583 | module_exit(pdc202new_ide_exit); |
1da177e4 LT |
584 | |
585 | MODULE_AUTHOR("Andre Hedrick, Frank Tiernan"); | |
586 | MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher"); | |
587 | MODULE_LICENSE("GPL"); |