[mirror_ubuntu-bionic-kernel.git] / drivers / ide / pci / pdc202xx_old.c

/*
 *  linux/drivers/ide/pci/pdc202xx_old.c	Version 0.51	Jul 27, 2007
 *
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007		MontaVista Software, Inc.
 *  Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
 *  compiled into the kernel if you have more than one card installed.
 *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
 *  safe chipset tuning, including this support is harmless
 *
 *  Promise Ultra66 cards with BIOS v1.11 this
 *  compiled into the kernel if you have more than one card installed.
 *
 *  Promise Ultra100 cards.
 *
 *  The latest chipset code will support the following ::
 *  Three Ultra33 controllers and 12 drives.
 *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
 *  The 8/4 ratio is a BIOS code limit by promise.
 *
 *  UNLESS you enable "CONFIG_PDC202XX_BURST"
 *
 */

/*
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/irq.h>

#define PDC202XX_DEBUG_DRIVE_INFO	0

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static void pdc_old_disable_66MHz_clock(ide_hwif_t *);

static int pdc202xx_tune_chipset(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 drive_pci		= 0x60 + (drive->dn << 2);

	u8			AP = 0, BP = 0, CP = 0;
	u8			TA = 0, TB = 0, TC = 0;

#if PDC202XX_DEBUG_DRIVE_INFO
	u32			drive_conf = 0;
	pci_read_config_dword(dev, drive_pci, &drive_conf);
#endif

	/*
	 * TODO: do this once per channel
	 */
	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
		pdc_old_disable_66MHz_clock(hwif);

	pci_read_config_byte(dev, drive_pci,     &AP);
	pci_read_config_byte(dev, drive_pci + 1, &BP);
	pci_read_config_byte(dev, drive_pci + 2, &CP);

	switch(speed) {
		case XFER_UDMA_5:
		case XFER_UDMA_4:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_2:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_3:
		case XFER_UDMA_1:	TB = 0x40; TC = 0x02; break;
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:	TB = 0x60; TC = 0x03; break;
		case XFER_MW_DMA_1:	TB = 0x60; TC = 0x04; break;
		case XFER_MW_DMA_0:	TB = 0xE0; TC = 0x0F; break;
		case XFER_SW_DMA_2:	TB = 0x60; TC = 0x05; break;
		case XFER_SW_DMA_1:	TB = 0x80; TC = 0x06; break;
		case XFER_SW_DMA_0:	TB = 0xC0; TC = 0x0B; break;
		case XFER_PIO_4:	TA = 0x01; TB = 0x04; break;
		case XFER_PIO_3:	TA = 0x02; TB = 0x06; break;
		case XFER_PIO_2:	TA = 0x03; TB = 0x08; break;
		case XFER_PIO_1:	TA = 0x05; TB = 0x0C; break;
		case XFER_PIO_0:
		default:		TA = 0x09; TB = 0x13; break;
	}

	if (speed < XFER_SW_DMA_0) {
		/*
		 * preserve SYNC_INT / ERDDY_EN bits while clearing
		 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
		 */
		AP &= ~0x3f;
		if (drive->id->capability & 4)
			AP |= 0x20;	/* set IORDY_EN bit */
		if (drive->media == ide_disk)
			AP |= 0x10;	/* set Prefetch_EN bit */
		/* clear PB[4:0] bits of register B */
		BP &= ~0x1f;
		pci_write_config_byte(dev, drive_pci,     AP | TA);
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
	} else {
		/* clear MB[2:0] bits of register B */
		BP &= ~0xe0;
		/* clear MC[3:0] bits of register C */
		CP &= ~0x0f;
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
		pci_write_config_byte(dev, drive_pci + 2, CP | TC);
	}

#if PDC202XX_DEBUG_DRIVE_INFO
	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
		drive->name, ide_xfer_verbose(speed),
		drive->dn, drive_conf);
	pci_read_config_dword(dev, drive_pci, &drive_conf);
	printk("0x%08x\n", drive_conf);
#endif

	return ide_config_drive_speed(drive, speed);
}

static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
}

static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
{
	u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);

	pci_read_config_word(hwif->pci_dev, 0x50, &CIS);

	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

/*
 * Set the control register to use the 66MHz system
 * clock for UDMA 3/4/5 mode operation when necessary.
 *
 * FIXME: this register is shared by both channels, some locking is needed
 *
 * It may also be possible to leave the 66MHz clock on
 * and readjust the timing parameters.
 */
static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->dma_master + 0x11;
	u8 clock = inb(clock_reg);

	outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->dma_master + 0x11;
	u8 clock = inb(clock_reg);

	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
}

static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
{
	drive->init_speed = 0;

	if (ide_tune_dma(drive))
		return 0;

	if (ide_use_fast_pio(drive))
		ide_set_max_pio(drive);

	return -1;
}

static int pdc202xx_quirkproc (ide_drive_t *drive)
{
	const char **list, *model = drive->id->model;

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(model, *list) != NULL)
			return 2;
	return 0;
}

static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
{
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_enable_66MHz_clock(drive->hwif);
	if (drive->media != ide_disk || drive->addressing == 1) {
		struct request *rq	= HWGROUP(drive)->rq;
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16   = hwif->dma_master;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u32 word_count	= 0;
		u8 clock = inb(high_16 + 0x11);

		outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
		word_count = (rq->nr_sectors << 8);
		word_count = (rq_data_dir(rq) == READ) ?
					word_count | 0x05000000 :
					word_count | 0x06000000;
		outl(word_count, atapi_reg);
	}
	ide_dma_start(drive);
}

static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
{
	if (drive->media != ide_disk || drive->addressing == 1) {
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16	= hwif->dma_master;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u8 clock		= 0;

		outl(0, atapi_reg); /* zero out extra */
		clock = inb(high_16 + 0x11);
		outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
	}
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_disable_66MHz_clock(drive->hwif);
	return __ide_dma_end(drive);
}

static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	unsigned long high_16	= hwif->dma_master;
	u8 dma_stat		= inb(hwif->dma_status);
	u8 sc1d			= inb(high_16 + 0x001d);

	if (hwif->channel) {
		/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
		if ((sc1d & 0x50) == 0x50)
			goto somebody_else;
		else if ((sc1d & 0x40) == 0x40)
			return (dma_stat & 4) == 4;
	} else {
		/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
		if ((sc1d & 0x05) == 0x05)
			goto somebody_else;
		else if ((sc1d & 0x04) == 0x04)
			return (dma_stat & 4) == 4;
	}
somebody_else:
	return (dma_stat & 4) == 4;	/* return 1 if INTR asserted */
}

static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);

	if (hwif->resetproc != NULL)
		hwif->resetproc(drive);

	ide_dma_lost_irq(drive);
}

static void pdc202xx_dma_timeout(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);

	if (hwif->resetproc != NULL)
		hwif->resetproc(drive);

	ide_dma_timeout(drive);
}

static void pdc202xx_reset_host (ide_hwif_t *hwif)
{
	unsigned long high_16	= hwif->dma_master;
	u8 udma_speed_flag	= inb(high_16 | 0x001f);

	outb(udma_speed_flag | 0x10, high_16 | 0x001f);
	mdelay(100);
	outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
	mdelay(2000);	/* 2 seconds ?! */

	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
		hwif->channel ? "Secondary" : "Primary");
}

static void pdc202xx_reset (ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	ide_hwif_t *mate	= hwif->mate;

	pdc202xx_reset_host(hwif);
	pdc202xx_reset_host(mate);

	ide_set_max_pio(drive);
}

static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
							const char *name)
{
	return dev->irq;
}

static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
{
	struct pci_dev *dev = hwif->pci_dev;

	/* PDC20265 has problems with large LBA48 requests */
	if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
	    (dev->device == PCI_DEVICE_ID_PROMISE_20265))
		hwif->rqsize = 256;

	hwif->autodma = 0;

	hwif->set_pio_mode = &pdc202xx_set_pio_mode;

	hwif->quirkproc = &pdc202xx_quirkproc;

	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
		hwif->resetproc = &pdc202xx_reset;

	hwif->speedproc = &pdc202xx_tune_chipset;

	hwif->err_stops_fifo = 1;

	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;

	if (hwif->dma_base == 0)
		return;

	hwif->ultra_mask = hwif->cds->udma_mask;
	hwif->mwdma_mask = 0x07;
	hwif->swdma_mask = 0x07;
	hwif->atapi_dma = 1;

	hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
	hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
	hwif->dma_timeout = &pdc202xx_dma_timeout;

	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
		if (hwif->cbl != ATA_CBL_PATA40_SHORT)
			hwif->cbl = pdc202xx_old_cable_detect(hwif);

		hwif->dma_start = &pdc202xx_old_ide_dma_start;
		hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
	} 
	hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
}

static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
{
	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;

	if (hwif->channel) {
		ide_setup_dma(hwif, dmabase, 8);
		return;
	}

	udma_speed_flag	= inb(dmabase | 0x1f);
	primary_mode	= inb(dmabase | 0x1a);
	secondary_mode	= inb(dmabase | 0x1b);
	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
		"Primary %s Mode " \
		"Secondary %s Mode.\n", hwif->cds->name,
		(udma_speed_flag & 1) ? "EN" : "DIS",
		(primary_mode & 1) ? "MASTER" : "PCI",
		(secondary_mode & 1) ? "MASTER" : "PCI" );

#ifdef CONFIG_PDC202XX_BURST
	if (!(udma_speed_flag & 1)) {
		printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
			hwif->cds->name, udma_speed_flag,
			(udma_speed_flag|1));
		outb(udma_speed_flag | 1, dmabase | 0x1f);
		printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
	}
#endif /* CONFIG_PDC202XX_BURST */

	ide_setup_dma(hwif, dmabase, 8);
}

static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
					   ide_pci_device_t *d)
{
	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
		u8 irq = 0, irq2 = 0;
		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
		/* 0xbc */
		pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
		if (irq != irq2) {
			pci_write_config_byte(dev,
				(PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
			printk(KERN_INFO "%s: pci-config space interrupt "
				"mirror fixed.\n", d->name);
		}
	}
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_pdc20265(struct pci_dev *dev,
					 ide_pci_device_t *d)
{
	if ((dev->bus->self) &&
	    (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
	    ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
	     (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
		printk(KERN_INFO "ide: Skipping Promise PDC20265 "
			"attached to I2O RAID controller.\n");
		return -ENODEV;
	}
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
					 ide_pci_device_t *d)
{
	return ide_setup_pci_device(dev, d);
}

static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "PDC20246",
		.init_setup	= init_setup_pdc202ata4,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.extra		= 16,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x07, /* udma0-2 */
	},{	/* 1 */
		.name		= "PDC20262",
		.init_setup	= init_setup_pdc202ata4,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.extra		= 48,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x1f, /* udma0-4 */
	},{	/* 2 */
		.name		= "PDC20263",
		.init_setup	= init_setup_pdc202ata4,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.extra		= 48,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x1f, /* udma0-4 */
	},{	/* 3 */
		.name		= "PDC20265",
		.init_setup	= init_setup_pdc20265,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.extra		= 48,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x3f, /* udma0-5 */
	},{	/* 4 */
		.name		= "PDC20267",
		.init_setup	= init_setup_pdc202xx,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.extra		= 48,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= 0x3f, /* udma0-5 */
	}
};

/**
 *	pdc202xx_init_one	-	called when a PDC202xx is found
 *	@dev: the pdc202xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];

	return d->init_setup(dev, d);
}

static struct pci_device_id pdc202xx_pci_tbl[] = {
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "Promise_Old_IDE",
	.id_table	= pdc202xx_pci_tbl,
	.probe		= pdc202xx_init_one,
};

static int __init pdc202xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(pdc202xx_ide_init);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
e98d6e50	2	* linux/drivers/ide/pci/pdc202xx_old.c Version 0.51 Jul 27, 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
fed21641	5	* Copyright (C) 2006-2007 MontaVista Software, Inc.
4fce3164	6	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	7	*
	8	* Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
	9	* compiled into the kernel if you have more than one card installed.
	10	* Note that BIOS v1.29 is reported to fix the problem. Since this is
	11	* safe chipset tuning, including this support is harmless
	12	*
	13	* Promise Ultra66 cards with BIOS v1.11 this
	14	* compiled into the kernel if you have more than one card installed.
	15	*
	16	* Promise Ultra100 cards.
	17	*
	18	* The latest chipset code will support the following ::
	19	* Three Ultra33 controllers and 12 drives.
	20	* 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
	21	* The 8/4 ratio is a BIOS code limit by promise.
	22	*
	23	* UNLESS you enable "CONFIG_PDC202XX_BURST"
	24	*
	25	*/
	26
	27	/*
	28	* Portions Copyright (C) 1999 Promise Technology, Inc.
	29	* Author: Frank Tiernan (frankt@promise.com)
	30	* Released under terms of General Public License
	31	*/
	32
1da177e4 LT	33	#include <linux/types.h>
	34	#include <linux/module.h>
	35	#include <linux/kernel.h>
	36	#include <linux/delay.h>
	37	#include <linux/timer.h>
	38	#include <linux/mm.h>
	39	#include <linux/ioport.h>
	40	#include <linux/blkdev.h>
	41	#include <linux/hdreg.h>
	42	#include <linux/interrupt.h>
	43	#include <linux/pci.h>
	44	#include <linux/init.h>
	45	#include <linux/ide.h>
	46
	47	#include <asm/io.h>
	48	#include <asm/irq.h>
	49
1da177e4 LT	50	#define PDC202XX_DEBUG_DRIVE_INFO 0
	51
	52	static const char *pdc_quirk_drives[] = {
	53	"QUANTUM FIREBALLlct08 08",
	54	"QUANTUM FIREBALLP KA6.4",
	55	"QUANTUM FIREBALLP KA9.1",
	56	"QUANTUM FIREBALLP LM20.4",
	57	"QUANTUM FIREBALLP KX13.6",
	58	"QUANTUM FIREBALLP KX20.5",
	59	"QUANTUM FIREBALLP KX27.3",
	60	"QUANTUM FIREBALLP LM20.5",
	61	NULL
	62	};
	63
4fce3164	64	static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
1da177e4	65
f212ff28	66	static int pdc202xx_tune_chipset(ide_drive_t *drive, const u8 speed)
1da177e4 LT	67	{
	68	ide_hwif_t *hwif = HWIF(drive);
	69	struct pci_dev *dev = hwif->pci_dev;
	70	u8 drive_pci = 0x60 + (drive->dn << 2);
1da177e4	71
4fce3164	72	u8 AP = 0, BP = 0, CP = 0;
1da177e4 LT	73	u8 TA = 0, TB = 0, TC = 0;
1da177e4 LT	74
4fce3164 BZ	75	#if PDC202XX_DEBUG_DRIVE_INFO
4fce3164 BZ	76	u32 drive_conf = 0;
1da177e4	77	pci_read_config_dword(dev, drive_pci, &drive_conf);
4fce3164	78	#endif
1da177e4	79
4fce3164 BZ	80	/*
	81	* TODO: do this once per channel
	82	*/
	83	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
	84	pdc_old_disable_66MHz_clock(hwif);
1da177e4	85
4fce3164 BZ	86	pci_read_config_byte(dev, drive_pci, &AP);
	87	pci_read_config_byte(dev, drive_pci + 1, &BP);
	88	pci_read_config_byte(dev, drive_pci + 2, &CP);
1da177e4 LT	89
1da177e4 LT	90	switch(speed) {
1da177e4 LT	91	case XFER_UDMA_5:
	92	case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
	93	case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
	94	case XFER_UDMA_3:
	95	case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
	96	case XFER_UDMA_0:
	97	case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
	98	case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
4fce3164	99	case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
1da177e4 LT	100	case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
	101	case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
	102	case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
	103	case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
	104	case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
	105	case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
	106	case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
	107	case XFER_PIO_0:
	108	default: TA = 0x09; TB = 0x13; break;
	109	}
	110
	111	if (speed < XFER_SW_DMA_0) {
4fce3164 BZ	112	/*
	113	* preserve SYNC_INT / ERDDY_EN bits while clearing
	114	* Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
	115	*/
	116	AP &= ~0x3f;
	117	if (drive->id->capability & 4)
	118	AP \|= 0x20; /* set IORDY_EN bit */
	119	if (drive->media == ide_disk)
	120	AP \|= 0x10; /* set Prefetch_EN bit */
	121	/* clear PB[4:0] bits of register B */
	122	BP &= ~0x1f;
	123	pci_write_config_byte(dev, drive_pci, AP \| TA);
	124	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
1da177e4	125	} else {
4fce3164 BZ	126	/* clear MB[2:0] bits of register B */
	127	BP &= ~0xe0;
	128	/* clear MC[3:0] bits of register C */
	129	CP &= ~0x0f;
	130	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
	131	pci_write_config_byte(dev, drive_pci + 2, CP \| TC);
1da177e4 LT	132	}
	133
	134	#if PDC202XX_DEBUG_DRIVE_INFO
	135	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
	136	drive->name, ide_xfer_verbose(speed),
	137	drive->dn, drive_conf);
4fce3164	138	pci_read_config_dword(dev, drive_pci, &drive_conf);
1da177e4	139	printk("0x%08x\n", drive_conf);
4fce3164	140	#endif
1da177e4	141
4fce3164	142	return ide_config_drive_speed(drive, speed);
1da177e4 LT	143	}
1da177e4 LT	144
26bcb879	145	static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	146	{
fed21641	147	pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
1da177e4 LT	148	}
	149
	150	static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
	151	{
	152	u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
49521f97	153
1da177e4	154	pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
49521f97 BZ	155
49521f97 BZ	156	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4 LT	157	}
	158
	159	/*
	160	* Set the control register to use the 66MHz system
	161	* clock for UDMA 3/4/5 mode operation when necessary.
	162	*
4fce3164 BZ	163	* FIXME: this register is shared by both channels, some locking is needed
4fce3164 BZ	164	*
1da177e4 LT	165	* It may also be possible to leave the 66MHz clock on
	166	* and readjust the timing parameters.
	167	*/
	168	static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
	169	{
	170	unsigned long clock_reg = hwif->dma_master + 0x11;
0ecdca26	171	u8 clock = inb(clock_reg);
1da177e4	172
0ecdca26	173	outb(clock \| (hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	174	}
	175
	176	static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
	177	{
	178	unsigned long clock_reg = hwif->dma_master + 0x11;
0ecdca26	179	u8 clock = inb(clock_reg);
1da177e4	180
0ecdca26	181	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	182	}
1da177e4 LT	183
1da177e4 LT	184	static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
1da177e4 LT	185	{
1da177e4 LT	186	drive->init_speed = 0;
1da177e4 LT	187
bd203b57	188	if (ide_tune_dma(drive))
3608b5d7	189	return 0;
1da177e4	190
d8f4469d	191	if (ide_use_fast_pio(drive))
26bcb879	192	ide_set_max_pio(drive);
d8f4469d	193
3608b5d7	194	return -1;
1da177e4 LT	195	}
	196
	197	static int pdc202xx_quirkproc (ide_drive_t *drive)
	198	{
d24ec426 SS	199	const char *list, model = drive->id->model;
	200
	201	for (list = pdc_quirk_drives; *list != NULL; list++)
	202	if (strstr(model, *list) != NULL)
	203	return 2;
	204	return 0;
1da177e4 LT	205	}
	206
	207	static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
	208	{
	209	if (drive->current_speed > XFER_UDMA_2)
	210	pdc_old_enable_66MHz_clock(drive->hwif);
f3d5b34c	211	if (drive->media != ide_disk \|\| drive->addressing == 1) {
1da177e4 LT	212	struct request *rq = HWGROUP(drive)->rq;
1da177e4 LT	213	ide_hwif_t *hwif = HWIF(drive);
1da177e4 LT	214	unsigned long high_16 = hwif->dma_master;
	215	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	216	u32 word_count = 0;
0ecdca26	217	u8 clock = inb(high_16 + 0x11);
1da177e4	218
0ecdca26	219	outb(clock \| (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
1da177e4 LT	220	word_count = (rq->nr_sectors << 8);
	221	word_count = (rq_data_dir(rq) == READ) ?
	222	word_count \| 0x05000000 :
	223	word_count \| 0x06000000;
0ecdca26	224	outl(word_count, atapi_reg);
1da177e4 LT	225	}
	226	ide_dma_start(drive);
	227	}
	228
	229	static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
	230	{
f3d5b34c	231	if (drive->media != ide_disk \|\| drive->addressing == 1) {
1da177e4	232	ide_hwif_t *hwif = HWIF(drive);
1da177e4 LT	233	unsigned long high_16 = hwif->dma_master;
	234	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	235	u8 clock = 0;
	236
0ecdca26 BZ	237	outl(0, atapi_reg); /* zero out extra */
	238	clock = inb(high_16 + 0x11);
	239	outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
1da177e4 LT	240	}
	241	if (drive->current_speed > XFER_UDMA_2)
	242	pdc_old_disable_66MHz_clock(drive->hwif);
	243	return __ide_dma_end(drive);
	244	}
	245
	246	static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
	247	{
	248	ide_hwif_t *hwif = HWIF(drive);
1da177e4	249	unsigned long high_16 = hwif->dma_master;
0ecdca26 BZ	250	u8 dma_stat = inb(hwif->dma_status);
0ecdca26 BZ	251	u8 sc1d = inb(high_16 + 0x001d);
1da177e4 LT	252
	253	if (hwif->channel) {
	254	/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
	255	if ((sc1d & 0x50) == 0x50)
	256	goto somebody_else;
	257	else if ((sc1d & 0x40) == 0x40)
	258	return (dma_stat & 4) == 4;
	259	} else {
	260	/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
	261	if ((sc1d & 0x05) == 0x05)
	262	goto somebody_else;
	263	else if ((sc1d & 0x04) == 0x04)
	264	return (dma_stat & 4) == 4;
	265	}
	266	somebody_else:
	267	return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
	268	}
	269
841d2a9b	270	static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
1da177e4	271	{
841d2a9b SS	272	ide_hwif_t *hwif = HWIF(drive);
	273
	274	if (hwif->resetproc != NULL)
	275	hwif->resetproc(drive);
	276
	277	ide_dma_lost_irq(drive);
1da177e4 LT	278	}
1da177e4 LT	279
c283f5db	280	static void pdc202xx_dma_timeout(ide_drive_t *drive)
1da177e4	281	{
c283f5db SS	282	ide_hwif_t *hwif = HWIF(drive);
	283
	284	if (hwif->resetproc != NULL)
	285	hwif->resetproc(drive);
	286
	287	ide_dma_timeout(drive);
1da177e4 LT	288	}
	289
	290	static void pdc202xx_reset_host (ide_hwif_t *hwif)
	291	{
1da177e4	292	unsigned long high_16 = hwif->dma_master;
0ecdca26	293	u8 udma_speed_flag = inb(high_16 \| 0x001f);
1da177e4	294
0ecdca26	295	outb(udma_speed_flag \| 0x10, high_16 \| 0x001f);
1da177e4	296	mdelay(100);
0ecdca26	297	outb(udma_speed_flag & ~0x10, high_16 \| 0x001f);
1da177e4 LT	298	mdelay(2000); /* 2 seconds ?! */
	299
	300	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
	301	hwif->channel ? "Secondary" : "Primary");
	302	}
	303
	304	static void pdc202xx_reset (ide_drive_t *drive)
	305	{
	306	ide_hwif_t *hwif = HWIF(drive);
	307	ide_hwif_t *mate = hwif->mate;
26bcb879	308
1da177e4 LT	309	pdc202xx_reset_host(hwif);
1da177e4 LT	310	pdc202xx_reset_host(mate);
26bcb879 BZ	311
26bcb879 BZ	312	ide_set_max_pio(drive);
1da177e4 LT	313	}
1da177e4 LT	314
57e834e2 AC	315	static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
57e834e2 AC	316	const char *name)
1da177e4	317	{
1da177e4 LT	318	return dev->irq;
	319	}
	320
	321	static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
	322	{
	323	struct pci_dev *dev = hwif->pci_dev;
	324
	325	/* PDC20265 has problems with large LBA48 requests */
	326	if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) \|\|
	327	(dev->device == PCI_DEVICE_ID_PROMISE_20265))
	328	hwif->rqsize = 256;
	329
	330	hwif->autodma = 0;
26bcb879 BZ	331
	332	hwif->set_pio_mode = &pdc202xx_set_pio_mode;
	333
1da177e4 LT	334	hwif->quirkproc = &pdc202xx_quirkproc;
1da177e4 LT	335
8b6ebe01	336	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
1da177e4	337	hwif->resetproc = &pdc202xx_reset;
1da177e4 LT	338
	339	hwif->speedproc = &pdc202xx_tune_chipset;
	340
e98d6e50 BZ	341	hwif->err_stops_fifo = 1;
e98d6e50 BZ	342
1da177e4 LT	343	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1da177e4 LT	344
e98d6e50 BZ	345	if (hwif->dma_base == 0)
	346	return;
	347
18137207	348	hwif->ultra_mask = hwif->cds->udma_mask;
1da177e4 LT	349	hwif->mwdma_mask = 0x07;
1da177e4 LT	350	hwif->swdma_mask = 0x07;
f3d5b34c	351	hwif->atapi_dma = 1;
1da177e4 LT	352
1da177e4 LT	353	hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
841d2a9b	354	hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
c283f5db	355	hwif->dma_timeout = &pdc202xx_dma_timeout;
1da177e4 LT	356
1da177e4 LT	357	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
49521f97 BZ	358	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
	359	hwif->cbl = pdc202xx_old_cable_detect(hwif);
	360
1da177e4 LT	361	hwif->dma_start = &pdc202xx_old_ide_dma_start;
	362	hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
	363	}
	364	hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
	365
	366	if (!noautodma)
	367	hwif->autodma = 1;
	368	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1da177e4 LT	369	}
	370
	371	static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
	372	{
	373	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
	374
	375	if (hwif->channel) {
	376	ide_setup_dma(hwif, dmabase, 8);
	377	return;
	378	}
	379
0ecdca26 BZ	380	udma_speed_flag = inb(dmabase \| 0x1f);
	381	primary_mode = inb(dmabase \| 0x1a);
	382	secondary_mode = inb(dmabase \| 0x1b);
1da177e4 LT	383	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
	384	"Primary %s Mode " \
	385	"Secondary %s Mode.\n", hwif->cds->name,
	386	(udma_speed_flag & 1) ? "EN" : "DIS",
	387	(primary_mode & 1) ? "MASTER" : "PCI",
	388	(secondary_mode & 1) ? "MASTER" : "PCI" );
	389
	390	#ifdef CONFIG_PDC202XX_BURST
	391	if (!(udma_speed_flag & 1)) {
	392	printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
	393	hwif->cds->name, udma_speed_flag,
	394	(udma_speed_flag\|1));
0ecdca26 BZ	395	outb(udma_speed_flag \| 1, dmabase \| 0x1f);
0ecdca26 BZ	396	printk("%sACTIVE\n", (inb(dmabase \| 0x1f) & 1) ? "" : "IN");
1da177e4 LT	397	}
1da177e4 LT	398	#endif /* CONFIG_PDC202XX_BURST */
1da177e4 LT	399
	400	ide_setup_dma(hwif, dmabase, 8);
	401	}
	402
	403	static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
	404	ide_pci_device_t *d)
	405	{
	406	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
	407	u8 irq = 0, irq2 = 0;
	408	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	409	/* 0xbc */
	410	pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)\|0x80, &irq2);
	411	if (irq != irq2) {
	412	pci_write_config_byte(dev,
	413	(PCI_INTERRUPT_LINE)\|0x80, irq); /* 0xbc */
	414	printk(KERN_INFO "%s: pci-config space interrupt "
	415	"mirror fixed.\n", d->name);
	416	}
	417	}
1da177e4 LT	418	return ide_setup_pci_device(dev, d);
	419	}
	420
	421	static int __devinit init_setup_pdc20265(struct pci_dev *dev,
	422	ide_pci_device_t *d)
	423	{
	424	if ((dev->bus->self) &&
	425	(dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
	426	((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) \|\|
	427	(dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
	428	printk(KERN_INFO "ide: Skipping Promise PDC20265 "
	429	"attached to I2O RAID controller.\n");
	430	return -ENODEV;
	431	}
1da177e4 LT	432	return ide_setup_pci_device(dev, d);
	433	}
	434
	435	static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
	436	ide_pci_device_t *d)
	437	{
	438	return ide_setup_pci_device(dev, d);
	439	}
	440
	441	static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
	442	{ /* 0 */
	443	.name = "PDC20246",
	444	.init_setup = init_setup_pdc202ata4,
	445	.init_chipset = init_chipset_pdc202xx,
	446	.init_hwif = init_hwif_pdc202xx,
	447	.init_dma = init_dma_pdc202xx,
1da177e4	448	.autodma = AUTODMA,
1da177e4 LT	449	.bootable = OFF_BOARD,
1da177e4 LT	450	.extra = 16,
4099d143	451	.pio_mask = ATA_PIO4,
18137207	452	.udma_mask = 0x07, /* udma0-2 */
1da177e4 LT	453	},{ /* 1 */
	454	.name = "PDC20262",
	455	.init_setup = init_setup_pdc202ata4,
	456	.init_chipset = init_chipset_pdc202xx,
	457	.init_hwif = init_hwif_pdc202xx,
	458	.init_dma = init_dma_pdc202xx,
1da177e4	459	.autodma = AUTODMA,
1da177e4 LT	460	.bootable = OFF_BOARD,
1da177e4 LT	461	.extra = 48,
4099d143	462	.pio_mask = ATA_PIO4,
18137207	463	.udma_mask = 0x1f, /* udma0-4 */
1da177e4 LT	464	},{ /* 2 */
	465	.name = "PDC20263",
	466	.init_setup = init_setup_pdc202ata4,
	467	.init_chipset = init_chipset_pdc202xx,
	468	.init_hwif = init_hwif_pdc202xx,
	469	.init_dma = init_dma_pdc202xx,
1da177e4	470	.autodma = AUTODMA,
1da177e4 LT	471	.bootable = OFF_BOARD,
1da177e4 LT	472	.extra = 48,
4099d143	473	.pio_mask = ATA_PIO4,
18137207	474	.udma_mask = 0x1f, /* udma0-4 */
1da177e4 LT	475	},{ /* 3 */
	476	.name = "PDC20265",
	477	.init_setup = init_setup_pdc20265,
	478	.init_chipset = init_chipset_pdc202xx,
	479	.init_hwif = init_hwif_pdc202xx,
	480	.init_dma = init_dma_pdc202xx,
1da177e4	481	.autodma = AUTODMA,
1da177e4 LT	482	.bootable = OFF_BOARD,
1da177e4 LT	483	.extra = 48,
4099d143	484	.pio_mask = ATA_PIO4,
18137207	485	.udma_mask = 0x3f, /* udma0-5 */
1da177e4 LT	486	},{ /* 4 */
	487	.name = "PDC20267",
	488	.init_setup = init_setup_pdc202xx,
	489	.init_chipset = init_chipset_pdc202xx,
	490	.init_hwif = init_hwif_pdc202xx,
	491	.init_dma = init_dma_pdc202xx,
1da177e4	492	.autodma = AUTODMA,
1da177e4 LT	493	.bootable = OFF_BOARD,
1da177e4 LT	494	.extra = 48,
4099d143	495	.pio_mask = ATA_PIO4,
18137207	496	.udma_mask = 0x3f, /* udma0-5 */
1da177e4 LT	497	}
	498	};
	499
	500	/**
	501	* pdc202xx_init_one - called when a PDC202xx is found
	502	* @dev: the pdc202xx device
	503	* @id: the matching pci id
	504	*
	505	* Called when the PCI registration layer (or the IDE initialization)
	506	* finds a device matching our IDE device tables.
	507	*/
	508
	509	static int __devinit pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
	510	{
	511	ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
	512
	513	return d->init_setup(dev, d);
	514	}
	515
	516	static struct pci_device_id pdc202xx_pci_tbl[] = {
	517	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	518	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	519	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
	520	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
	521	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
	522	{ 0, },
	523	};
	524	MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
	525
	526	static struct pci_driver driver = {
	527	.name = "Promise_Old_IDE",
	528	.id_table = pdc202xx_pci_tbl,
	529	.probe = pdc202xx_init_one,
	530	};
	531
82ab1eec	532	static int __init pdc202xx_ide_init(void)
1da177e4 LT	533	{
	534	return ide_pci_register_driver(&driver);
	535	}
	536
	537	module_init(pdc202xx_ide_init);
	538
	539	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	540	MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
	541	MODULE_LICENSE("GPL");