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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer |
3 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
4 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
07af4276 | 5 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 LT |
6 | * |
7 | * May be copied or modified under the terms of the GNU General Public License | |
8 | * | |
2be564b0 | 9 | * Documentation: |
1da177e4 | 10 | * |
1da177e4 LT |
11 | * Publically available from Intel web site. Errata documentation |
12 | * is also publically available. As an aide to anyone hacking on this | |
13 | * driver the list of errata that are relevant is below.going back to | |
14 | * PIIX4. Older device documentation is now a bit tricky to find. | |
15 | * | |
16 | * Errata of note: | |
17 | * | |
18 | * Unfixable | |
19 | * PIIX4 errata #9 - Only on ultra obscure hw | |
20 | * ICH3 errata #13 - Not observed to affect real hw | |
21 | * by Intel | |
22 | * | |
23 | * Things we must deal with | |
24 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
25 | * (must stop/start dma to recover) | |
26 | * 440MX errata #15 - As PIIX4 errata #10 | |
27 | * PIIX4 errata #15 - Must not read control registers | |
28 | * during a PIO transfer | |
29 | * 440MX errata #13 - As PIIX4 errata #15 | |
30 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
31 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
32 | * ICH2 spec c #9 - Extra operations needed to handle | |
33 | * drive hotswap [NOT YET SUPPORTED] | |
34 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
35 | * and must be dword aligned | |
36 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
37 | * | |
38 | * Should have been BIOS fixed: | |
39 | * 450NX: errata #19 - DMA hangs on old 450NX | |
40 | * 450NX: errata #20 - DMA hangs on old 450NX | |
41 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
42 | * ICH3 errata #15 - IDE deadlock under high load | |
43 | * (BIOS must set dev 31 fn 0 bit 23) | |
44 | * ICH3 errata #18 - Don't use native mode | |
45 | */ | |
46 | ||
1da177e4 LT |
47 | #include <linux/types.h> |
48 | #include <linux/module.h> | |
49 | #include <linux/kernel.h> | |
1da177e4 | 50 | #include <linux/pci.h> |
1da177e4 | 51 | #include <linux/ide.h> |
1da177e4 LT |
52 | #include <linux/init.h> |
53 | ||
54 | #include <asm/io.h> | |
55 | ||
ced3ec8a BZ |
56 | #define DRV_NAME "piix" |
57 | ||
1da177e4 LT |
58 | static int no_piix_dma; |
59 | ||
1da177e4 | 60 | /** |
88b2b32b BZ |
61 | * piix_set_pio_mode - set host controller for PIO mode |
62 | * @drive: drive | |
63 | * @pio: PIO mode number | |
1da177e4 | 64 | * |
07af4276 | 65 | * Set the interface PIO mode based upon the settings done by AMI BIOS. |
1da177e4 | 66 | */ |
88b2b32b BZ |
67 | |
68 | static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio) | |
1da177e4 LT |
69 | { |
70 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 71 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
30dfd12f | 72 | int is_slave = drive->dn & 1; |
1da177e4 LT |
73 | int master_port = hwif->channel ? 0x42 : 0x40; |
74 | int slave_port = 0x44; | |
75 | unsigned long flags; | |
76 | u16 master_data; | |
77 | u8 slave_data; | |
4fb0f76d | 78 | static DEFINE_SPINLOCK(tune_lock); |
5ac24697 | 79 | int control = 0; |
4fb0f76d | 80 | |
30dfd12f | 81 | /* ISP RTC */ |
5ac24697 AC |
82 | static const u8 timings[][2]= { |
83 | { 0, 0 }, | |
84 | { 0, 0 }, | |
85 | { 1, 0 }, | |
86 | { 2, 1 }, | |
87 | { 2, 3 }, }; | |
1da177e4 | 88 | |
4fb0f76d AC |
89 | /* |
90 | * Master vs slave is synchronized above us but the slave register is | |
91 | * shared by the two hwifs so the corner case of two slave timeouts in | |
92 | * parallel must be locked. | |
93 | */ | |
94 | spin_lock_irqsave(&tune_lock, flags); | |
1da177e4 | 95 | pci_read_config_word(dev, master_port, &master_data); |
5ac24697 | 96 | |
30dfd12f | 97 | if (pio > 1) |
5ac24697 AC |
98 | control |= 1; /* Programmable timing on */ |
99 | if (drive->media == ide_disk) | |
100 | control |= 4; /* Prefetch, post write */ | |
30dfd12f | 101 | if (pio > 2) |
5ac24697 | 102 | control |= 2; /* IORDY */ |
1da177e4 | 103 | if (is_slave) { |
30dfd12f SS |
104 | master_data |= 0x4000; |
105 | master_data &= ~0x0070; | |
5ac24697 | 106 | if (pio > 1) { |
07af4276 SS |
107 | /* Set PPE, IE and TIME */ |
108 | master_data |= control << 4; | |
5ac24697 | 109 | } |
1da177e4 | 110 | pci_read_config_byte(dev, slave_port, &slave_data); |
07af4276 SS |
111 | slave_data &= hwif->channel ? 0x0f : 0xf0; |
112 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << | |
113 | (hwif->channel ? 4 : 0); | |
1da177e4 | 114 | } else { |
30dfd12f | 115 | master_data &= ~0x3307; |
5ac24697 | 116 | if (pio > 1) { |
1da177e4 | 117 | /* enable PPE, IE and TIME */ |
07af4276 | 118 | master_data |= control; |
5ac24697 | 119 | } |
07af4276 | 120 | master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); |
1da177e4 LT |
121 | } |
122 | pci_write_config_word(dev, master_port, master_data); | |
123 | if (is_slave) | |
124 | pci_write_config_byte(dev, slave_port, slave_data); | |
4fb0f76d | 125 | spin_unlock_irqrestore(&tune_lock, flags); |
1da177e4 LT |
126 | } |
127 | ||
07af4276 | 128 | /** |
88b2b32b BZ |
129 | * piix_set_dma_mode - set host controller for DMA mode |
130 | * @drive: drive | |
131 | * @speed: DMA mode | |
1da177e4 | 132 | * |
88b2b32b BZ |
133 | * Set a PIIX host controller to the desired DMA mode. This involves |
134 | * programming the right timing data into the PCI configuration space. | |
1da177e4 | 135 | */ |
f212ff28 | 136 | |
88b2b32b | 137 | static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
138 | { |
139 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 140 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 141 | u8 maslave = hwif->channel ? 0x42 : 0x40; |
1da177e4 LT |
142 | int a_speed = 3 << (drive->dn * 4); |
143 | int u_flag = 1 << drive->dn; | |
144 | int v_flag = 0x01 << drive->dn; | |
145 | int w_flag = 0x10 << drive->dn; | |
146 | int u_speed = 0; | |
147 | int sitre; | |
148 | u16 reg4042, reg4a; | |
1c54a93d | 149 | u8 reg48, reg54, reg55; |
1da177e4 LT |
150 | |
151 | pci_read_config_word(dev, maslave, ®4042); | |
152 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
153 | pci_read_config_byte(dev, 0x48, ®48); | |
154 | pci_read_config_word(dev, 0x4a, ®4a); | |
155 | pci_read_config_byte(dev, 0x54, ®54); | |
156 | pci_read_config_byte(dev, 0x55, ®55); | |
157 | ||
1da177e4 | 158 | if (speed >= XFER_UDMA_0) { |
4db90a14 BZ |
159 | u8 udma = speed - XFER_UDMA_0; |
160 | ||
161 | u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4); | |
162 | ||
1da177e4 LT |
163 | if (!(reg48 & u_flag)) |
164 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); | |
165 | if (speed == XFER_UDMA_5) { | |
166 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); | |
167 | } else { | |
168 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
169 | } | |
170 | if ((reg4a & a_speed) != u_speed) | |
171 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); | |
172 | if (speed > XFER_UDMA_2) { | |
173 | if (!(reg54 & v_flag)) | |
174 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); | |
175 | } else | |
176 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
177 | } else { | |
8c91abf8 | 178 | const u8 mwdma_to_pio[] = { 0, 3, 4 }; |
1c54a93d | 179 | u8 pio; |
8c91abf8 | 180 | |
1da177e4 LT |
181 | if (reg48 & u_flag) |
182 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); | |
183 | if (reg4a & a_speed) | |
184 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
185 | if (reg54 & v_flag) | |
186 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
187 | if (reg55 & w_flag) | |
188 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
8c91abf8 BZ |
189 | |
190 | if (speed >= XFER_MW_DMA_0) | |
191 | pio = mwdma_to_pio[speed - XFER_MW_DMA_0]; | |
192 | else | |
193 | pio = 2; /* only SWDMA2 is allowed */ | |
1da177e4 | 194 | |
1c54a93d BZ |
195 | piix_set_pio_mode(drive, pio); |
196 | } | |
1da177e4 LT |
197 | } |
198 | ||
1da177e4 | 199 | /** |
40d2dd7e | 200 | * init_chipset_ich - set up the ICH chipset |
f0dd8712 | 201 | * @dev: PCI device to set up |
f0dd8712 | 202 | * |
40d2dd7e BZ |
203 | * Initialize the PCI device as required. For the ICH this turns |
204 | * out to be nice and simple. | |
f0dd8712 AL |
205 | */ |
206 | ||
feb22b7f | 207 | static unsigned int init_chipset_ich(struct pci_dev *dev) |
f0dd8712 | 208 | { |
40d2dd7e BZ |
209 | u32 extra = 0; |
210 | ||
211 | pci_read_config_dword(dev, 0x54, &extra); | |
212 | pci_write_config_dword(dev, 0x54, extra | 0x400); | |
f0dd8712 AL |
213 | |
214 | return 0; | |
215 | } | |
216 | ||
217 | /** | |
218 | * piix_dma_clear_irq - clear BMDMA status | |
219 | * @drive: IDE drive to clear | |
220 | * | |
221 | * Called from ide_intr() for PIO interrupts | |
222 | * to clear BMDMA status as needed by ICHx | |
223 | */ | |
224 | static void piix_dma_clear_irq(ide_drive_t *drive) | |
225 | { | |
226 | ide_hwif_t *hwif = HWIF(drive); | |
227 | u8 dma_stat; | |
228 | ||
229 | /* clear the INTR & ERROR bits */ | |
cab7f8ed | 230 | dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
f0dd8712 | 231 | /* Should we force the bit as well ? */ |
cab7f8ed | 232 | outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS); |
f0dd8712 AL |
233 | } |
234 | ||
7207626f BZ |
235 | struct ich_laptop { |
236 | u16 device; | |
237 | u16 subvendor; | |
238 | u16 subdevice; | |
239 | }; | |
240 | ||
241 | /* | |
242 | * List of laptops that use short cables rather than 80 wire | |
243 | */ | |
244 | ||
245 | static const struct ich_laptop ich_laptop[] = { | |
246 | /* devid, subvendor, subdev */ | |
afda5e4d | 247 | { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ |
7207626f BZ |
248 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ |
249 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ | |
250 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ | |
dd0fd40d | 251 | { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ |
7207626f | 252 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */ |
1fa5a40f | 253 | { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ |
7207626f BZ |
254 | /* end marker */ |
255 | { 0, } | |
256 | }; | |
257 | ||
f454cbe8 | 258 | static u8 piix_cable_detect(ide_hwif_t *hwif) |
74594fd1 | 259 | { |
36501650 | 260 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
7207626f | 261 | const struct ich_laptop *lap = &ich_laptop[0]; |
74594fd1 BZ |
262 | u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30; |
263 | ||
7207626f BZ |
264 | /* check for specials */ |
265 | while (lap->device) { | |
266 | if (lap->device == pdev->device && | |
267 | lap->subvendor == pdev->subsystem_vendor && | |
268 | lap->subdevice == pdev->subsystem_device) { | |
269 | return ATA_CBL_PATA40_SHORT; | |
270 | } | |
271 | lap++; | |
272 | } | |
273 | ||
274 | pci_read_config_byte(pdev, 0x54, ®54h); | |
74594fd1 | 275 | |
49521f97 | 276 | return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
74594fd1 BZ |
277 | } |
278 | ||
1da177e4 LT |
279 | /** |
280 | * init_hwif_piix - fill in the hwif for the PIIX | |
281 | * @hwif: IDE interface | |
282 | * | |
283 | * Set up the ide_hwif_t for the PIIX interface according to the | |
284 | * capabilities of the hardware. | |
285 | */ | |
286 | ||
287 | static void __devinit init_hwif_piix(ide_hwif_t *hwif) | |
288 | { | |
1da177e4 LT |
289 | if (!hwif->dma_base) |
290 | return; | |
291 | ||
74594fd1 BZ |
292 | if (no_piix_dma) |
293 | hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0; | |
1da177e4 LT |
294 | } |
295 | ||
40d2dd7e BZ |
296 | static void __devinit init_hwif_ich(ide_hwif_t *hwif) |
297 | { | |
298 | init_hwif_piix(hwif); | |
299 | ||
300 | /* ICHx need to clear the BMDMA status for all interrupts */ | |
301 | if (hwif->dma_base) | |
302 | hwif->ide_dma_clear_irq = &piix_dma_clear_irq; | |
303 | } | |
304 | ||
ac95beed BZ |
305 | static const struct ide_port_ops piix_port_ops = { |
306 | .set_pio_mode = piix_set_pio_mode, | |
307 | .set_dma_mode = piix_set_dma_mode, | |
308 | .cable_detect = piix_cable_detect, | |
309 | }; | |
310 | ||
3985ee3b | 311 | #ifndef CONFIG_IA64 |
5e71d9c5 | 312 | #define IDE_HFLAGS_PIIX IDE_HFLAG_LEGACY_IRQS |
3985ee3b | 313 | #else |
5e71d9c5 | 314 | #define IDE_HFLAGS_PIIX 0 |
3985ee3b BZ |
315 | #endif |
316 | ||
ced3ec8a | 317 | #define DECLARE_PIIX_DEV(udma) \ |
1da177e4 | 318 | { \ |
ced3ec8a | 319 | .name = DRV_NAME, \ |
1da177e4 | 320 | .init_hwif = init_hwif_piix, \ |
1da177e4 | 321 | .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ |
ac95beed | 322 | .port_ops = &piix_port_ops, \ |
3985ee3b | 323 | .host_flags = IDE_HFLAGS_PIIX, \ |
4099d143 | 324 | .pio_mask = ATA_PIO4, \ |
5f8b6c34 BZ |
325 | .swdma_mask = ATA_SWDMA2_ONLY, \ |
326 | .mwdma_mask = ATA_MWDMA12_ONLY, \ | |
18137207 | 327 | .udma_mask = udma, \ |
1da177e4 LT |
328 | } |
329 | ||
ced3ec8a | 330 | #define DECLARE_ICH_DEV(udma) \ |
40d2dd7e | 331 | { \ |
ced3ec8a | 332 | .name = DRV_NAME, \ |
40d2dd7e BZ |
333 | .init_chipset = init_chipset_ich, \ |
334 | .init_hwif = init_hwif_ich, \ | |
335 | .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ | |
ac95beed | 336 | .port_ops = &piix_port_ops, \ |
3985ee3b | 337 | .host_flags = IDE_HFLAGS_PIIX, \ |
40d2dd7e BZ |
338 | .pio_mask = ATA_PIO4, \ |
339 | .swdma_mask = ATA_SWDMA2_ONLY, \ | |
340 | .mwdma_mask = ATA_MWDMA12_ONLY, \ | |
341 | .udma_mask = udma, \ | |
342 | } | |
343 | ||
85620436 | 344 | static const struct ide_port_info piix_pci_info[] __devinitdata = { |
ced3ec8a | 345 | /* 0: MPIIX */ |
d2872239 SS |
346 | { /* |
347 | * MPIIX actually has only a single IDE channel mapped to | |
348 | * the primary or secondary ports depending on the value | |
349 | * of the bit 14 of the IDETIM register at offset 0x6c | |
350 | */ | |
ced3ec8a | 351 | .name = DRV_NAME, |
d2872239 | 352 | .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}}, |
47b68788 | 353 | .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA | |
3985ee3b | 354 | IDE_HFLAGS_PIIX, |
4099d143 | 355 | .pio_mask = ATA_PIO4, |
3985ee3b | 356 | /* This is a painful system best to let it self tune for now */ |
1da177e4 | 357 | }, |
ced3ec8a BZ |
358 | /* 1: PIIXa/PIIXb/PIIX3 */ |
359 | DECLARE_PIIX_DEV(0x00), /* no udma */ | |
360 | /* 2: PIIX4 */ | |
361 | DECLARE_PIIX_DEV(ATA_UDMA2), | |
362 | /* 3: ICH0 */ | |
363 | DECLARE_ICH_DEV(ATA_UDMA2), | |
364 | /* 4: ICH */ | |
365 | DECLARE_ICH_DEV(ATA_UDMA4), | |
366 | /* 5: PIIX4 */ | |
367 | DECLARE_PIIX_DEV(ATA_UDMA4), | |
368 | /* 6: ICH[2-7]/ICH[2-3]M/C-ICH/ICH5-SATA/ESB2/ICH8M */ | |
369 | DECLARE_ICH_DEV(ATA_UDMA5), | |
1da177e4 LT |
370 | }; |
371 | ||
372 | /** | |
373 | * piix_init_one - called when a PIIX is found | |
374 | * @dev: the piix device | |
375 | * @id: the matching pci id | |
376 | * | |
377 | * Called when the PCI registration layer (or the IDE initialization) | |
378 | * finds a device matching our IDE device tables. | |
379 | */ | |
380 | ||
381 | static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
382 | { | |
6cdf6eb3 | 383 | return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL); |
1da177e4 LT |
384 | } |
385 | ||
386 | /** | |
387 | * piix_check_450nx - Check for problem 450NX setup | |
388 | * | |
389 | * Check for the present of 450NX errata #19 and errata #25. If | |
390 | * they are found, disable use of DMA IDE | |
391 | */ | |
392 | ||
393 | static void __devinit piix_check_450nx(void) | |
394 | { | |
395 | struct pci_dev *pdev = NULL; | |
396 | u16 cfg; | |
1424e504 | 397 | while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL) |
1da177e4 LT |
398 | { |
399 | /* Look for 450NX PXB. Check for problem configurations | |
400 | A PCI quirk checks bit 6 already */ | |
1da177e4 LT |
401 | pci_read_config_word(pdev, 0x41, &cfg); |
402 | /* Only on the original revision: IDE DMA can hang */ | |
44c10138 | 403 | if (pdev->revision == 0x00) |
1da177e4 LT |
404 | no_piix_dma = 1; |
405 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
44c10138 | 406 | else if (cfg & (1<<14) && pdev->revision < 5) |
1da177e4 LT |
407 | no_piix_dma = 2; |
408 | } | |
409 | if(no_piix_dma) | |
ced3ec8a | 410 | printk(KERN_WARNING DRV_NAME ": 450NX errata present, disabling IDE DMA.\n"); |
1da177e4 | 411 | if(no_piix_dma == 2) |
ced3ec8a | 412 | printk(KERN_WARNING DRV_NAME ": A BIOS update may resolve this.\n"); |
1da177e4 LT |
413 | } |
414 | ||
9cbcc5e3 | 415 | static const struct pci_device_id piix_pci_tbl[] = { |
ced3ec8a BZ |
416 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 1 }, |
417 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 }, | |
418 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 0 }, | |
419 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 1 }, | |
420 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 2 }, | |
421 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 3 }, | |
422 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 2 }, | |
423 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 4 }, | |
424 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 5 }, | |
425 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 2 }, | |
426 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 6 }, | |
427 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 6 }, | |
428 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 6 }, | |
429 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 6 }, | |
430 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 6 }, | |
431 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 6 }, | |
432 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 6 }, | |
433 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 6 }, | |
1da177e4 | 434 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
ced3ec8a | 435 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 6 }, |
1da177e4 | 436 | #endif |
ced3ec8a BZ |
437 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 6 }, |
438 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 6 }, | |
439 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 6 }, | |
440 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 6 }, | |
441 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 6 }, | |
442 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 6 }, | |
1da177e4 LT |
443 | { 0, }, |
444 | }; | |
445 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
446 | ||
a9ab09e2 | 447 | static struct pci_driver piix_pci_driver = { |
1da177e4 LT |
448 | .name = "PIIX_IDE", |
449 | .id_table = piix_pci_tbl, | |
450 | .probe = piix_init_one, | |
da8c3e0d | 451 | .remove = ide_pci_remove, |
feb22b7f BZ |
452 | .suspend = ide_pci_suspend, |
453 | .resume = ide_pci_resume, | |
1da177e4 LT |
454 | }; |
455 | ||
456 | static int __init piix_ide_init(void) | |
457 | { | |
458 | piix_check_450nx(); | |
a9ab09e2 | 459 | return ide_pci_register_driver(&piix_pci_driver); |
1da177e4 LT |
460 | } |
461 | ||
da8c3e0d BZ |
462 | static void __exit piix_ide_exit(void) |
463 | { | |
a9ab09e2 | 464 | pci_unregister_driver(&piix_pci_driver); |
da8c3e0d BZ |
465 | } |
466 | ||
1da177e4 | 467 | module_init(piix_ide_init); |
da8c3e0d | 468 | module_exit(piix_ide_exit); |
1da177e4 LT |
469 | |
470 | MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz"); | |
471 | MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE"); | |
472 | MODULE_LICENSE("GPL"); |