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Commit | Line | Data |
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1da177e4 | 1 | /* |
07af4276 | 2 | * linux/drivers/ide/pci/piix.c Version 0.47 February 8, 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
5 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
6 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
07af4276 | 7 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 LT |
8 | * |
9 | * May be copied or modified under the terms of the GNU General Public License | |
10 | * | |
44854add | 11 | * PIO mode setting function for Intel chipsets. |
1da177e4 LT |
12 | * For use instead of BIOS settings. |
13 | * | |
14 | * 40-41 | |
15 | * 42-43 | |
16 | * | |
17 | * 41 | |
18 | * 43 | |
19 | * | |
20 | * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0); | |
21 | * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2); | |
22 | * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3); | |
23 | * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4); | |
24 | * | |
25 | * sitre = word40 & 0x4000; primary | |
26 | * sitre = word42 & 0x4000; secondary | |
27 | * | |
28 | * 44 8421|8421 hdd|hdb | |
44854add | 29 | * |
1da177e4 LT |
30 | * 48 8421 hdd|hdc|hdb|hda udma enabled |
31 | * | |
32 | * 0001 hda | |
33 | * 0010 hdb | |
34 | * 0100 hdc | |
35 | * 1000 hdd | |
36 | * | |
37 | * 4a 84|21 hdb|hda | |
38 | * 4b 84|21 hdd|hdc | |
39 | * | |
40 | * ata-33/82371AB | |
41 | * ata-33/82371EB | |
42 | * ata-33/82801AB ata-66/82801AA | |
43 | * 00|00 udma 0 00|00 reserved | |
44 | * 01|01 udma 1 01|01 udma 3 | |
45 | * 10|10 udma 2 10|10 udma 4 | |
46 | * 11|11 reserved 11|11 reserved | |
47 | * | |
48 | * 54 8421|8421 ata66 drive|ata66 enable | |
49 | * | |
50 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40); | |
51 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42); | |
52 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44); | |
53 | * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48); | |
54 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a); | |
55 | * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54); | |
56 | * | |
57 | * Documentation | |
58 | * Publically available from Intel web site. Errata documentation | |
59 | * is also publically available. As an aide to anyone hacking on this | |
60 | * driver the list of errata that are relevant is below.going back to | |
61 | * PIIX4. Older device documentation is now a bit tricky to find. | |
62 | * | |
63 | * Errata of note: | |
64 | * | |
65 | * Unfixable | |
66 | * PIIX4 errata #9 - Only on ultra obscure hw | |
67 | * ICH3 errata #13 - Not observed to affect real hw | |
68 | * by Intel | |
69 | * | |
70 | * Things we must deal with | |
71 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
72 | * (must stop/start dma to recover) | |
73 | * 440MX errata #15 - As PIIX4 errata #10 | |
74 | * PIIX4 errata #15 - Must not read control registers | |
75 | * during a PIO transfer | |
76 | * 440MX errata #13 - As PIIX4 errata #15 | |
77 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
78 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
79 | * ICH2 spec c #9 - Extra operations needed to handle | |
80 | * drive hotswap [NOT YET SUPPORTED] | |
81 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
82 | * and must be dword aligned | |
83 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
84 | * | |
85 | * Should have been BIOS fixed: | |
86 | * 450NX: errata #19 - DMA hangs on old 450NX | |
87 | * 450NX: errata #20 - DMA hangs on old 450NX | |
88 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
89 | * ICH3 errata #15 - IDE deadlock under high load | |
90 | * (BIOS must set dev 31 fn 0 bit 23) | |
91 | * ICH3 errata #18 - Don't use native mode | |
92 | */ | |
93 | ||
1da177e4 LT |
94 | #include <linux/types.h> |
95 | #include <linux/module.h> | |
96 | #include <linux/kernel.h> | |
97 | #include <linux/ioport.h> | |
98 | #include <linux/pci.h> | |
99 | #include <linux/hdreg.h> | |
100 | #include <linux/ide.h> | |
101 | #include <linux/delay.h> | |
102 | #include <linux/init.h> | |
103 | ||
104 | #include <asm/io.h> | |
105 | ||
106 | static int no_piix_dma; | |
107 | ||
108 | /** | |
109 | * piix_ratemask - compute rate mask for PIIX IDE | |
110 | * @drive: IDE drive to compute for | |
111 | * | |
112 | * Returns the available modes for the PIIX IDE controller. | |
113 | */ | |
114 | ||
115 | static u8 piix_ratemask (ide_drive_t *drive) | |
116 | { | |
117 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
118 | u8 mode; | |
119 | ||
120 | switch(dev->device) { | |
121 | case PCI_DEVICE_ID_INTEL_82801EB_1: | |
122 | mode = 3; | |
123 | break; | |
124 | /* UDMA 100 capable */ | |
125 | case PCI_DEVICE_ID_INTEL_82801BA_8: | |
126 | case PCI_DEVICE_ID_INTEL_82801BA_9: | |
127 | case PCI_DEVICE_ID_INTEL_82801CA_10: | |
128 | case PCI_DEVICE_ID_INTEL_82801CA_11: | |
129 | case PCI_DEVICE_ID_INTEL_82801E_11: | |
130 | case PCI_DEVICE_ID_INTEL_82801DB_1: | |
131 | case PCI_DEVICE_ID_INTEL_82801DB_10: | |
132 | case PCI_DEVICE_ID_INTEL_82801DB_11: | |
133 | case PCI_DEVICE_ID_INTEL_82801EB_11: | |
134 | case PCI_DEVICE_ID_INTEL_ESB_2: | |
135 | case PCI_DEVICE_ID_INTEL_ICH6_19: | |
136 | case PCI_DEVICE_ID_INTEL_ICH7_21: | |
d69332b8 | 137 | case PCI_DEVICE_ID_INTEL_ESB2_18: |
b7bed9ec | 138 | case PCI_DEVICE_ID_INTEL_ICH8_6: |
1da177e4 LT |
139 | mode = 3; |
140 | break; | |
141 | /* UDMA 66 capable */ | |
142 | case PCI_DEVICE_ID_INTEL_82801AA_1: | |
143 | case PCI_DEVICE_ID_INTEL_82372FB_1: | |
144 | mode = 2; | |
145 | break; | |
146 | /* UDMA 33 capable */ | |
147 | case PCI_DEVICE_ID_INTEL_82371AB: | |
148 | case PCI_DEVICE_ID_INTEL_82443MX_1: | |
149 | case PCI_DEVICE_ID_INTEL_82451NX: | |
150 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
151 | return 1; | |
152 | /* Non UDMA capable (MWDMA2) */ | |
153 | case PCI_DEVICE_ID_INTEL_82371SB_1: | |
154 | case PCI_DEVICE_ID_INTEL_82371FB_1: | |
155 | case PCI_DEVICE_ID_INTEL_82371FB_0: | |
156 | case PCI_DEVICE_ID_INTEL_82371MX: | |
157 | default: | |
158 | return 0; | |
159 | } | |
160 | ||
161 | /* | |
162 | * If we are UDMA66 capable fall back to UDMA33 | |
163 | * if the drive cannot see an 80pin cable. | |
164 | */ | |
165 | if (!eighty_ninty_three(drive)) | |
30dfd12f | 166 | mode = min_t(u8, mode, 1); |
1da177e4 LT |
167 | return mode; |
168 | } | |
169 | ||
170 | /** | |
171 | * piix_dma_2_pio - return the PIO mode matching DMA | |
172 | * @xfer_rate: transfer speed | |
173 | * | |
174 | * Returns the nearest equivalent PIO timing for the PIO or DMA | |
175 | * mode requested by the controller. | |
176 | */ | |
177 | ||
178 | static u8 piix_dma_2_pio (u8 xfer_rate) { | |
179 | switch(xfer_rate) { | |
180 | case XFER_UDMA_6: | |
181 | case XFER_UDMA_5: | |
182 | case XFER_UDMA_4: | |
183 | case XFER_UDMA_3: | |
184 | case XFER_UDMA_2: | |
185 | case XFER_UDMA_1: | |
186 | case XFER_UDMA_0: | |
187 | case XFER_MW_DMA_2: | |
188 | case XFER_PIO_4: | |
189 | return 4; | |
190 | case XFER_MW_DMA_1: | |
191 | case XFER_PIO_3: | |
192 | return 3; | |
193 | case XFER_SW_DMA_2: | |
194 | case XFER_PIO_2: | |
195 | return 2; | |
196 | case XFER_MW_DMA_0: | |
197 | case XFER_SW_DMA_1: | |
198 | case XFER_SW_DMA_0: | |
199 | case XFER_PIO_1: | |
200 | case XFER_PIO_0: | |
201 | case XFER_PIO_SLOW: | |
202 | default: | |
203 | return 0; | |
204 | } | |
205 | } | |
206 | ||
207 | /** | |
07af4276 | 208 | * piix_tune_pio - tune PIIX for PIO mode |
1da177e4 LT |
209 | * @drive: drive to tune |
210 | * @pio: desired PIO mode | |
211 | * | |
07af4276 | 212 | * Set the interface PIO mode based upon the settings done by AMI BIOS. |
1da177e4 | 213 | */ |
07af4276 | 214 | static void piix_tune_pio (ide_drive_t *drive, u8 pio) |
1da177e4 LT |
215 | { |
216 | ide_hwif_t *hwif = HWIF(drive); | |
217 | struct pci_dev *dev = hwif->pci_dev; | |
30dfd12f | 218 | int is_slave = drive->dn & 1; |
1da177e4 LT |
219 | int master_port = hwif->channel ? 0x42 : 0x40; |
220 | int slave_port = 0x44; | |
221 | unsigned long flags; | |
222 | u16 master_data; | |
223 | u8 slave_data; | |
4fb0f76d | 224 | static DEFINE_SPINLOCK(tune_lock); |
5ac24697 | 225 | int control = 0; |
4fb0f76d | 226 | |
30dfd12f | 227 | /* ISP RTC */ |
5ac24697 AC |
228 | static const u8 timings[][2]= { |
229 | { 0, 0 }, | |
230 | { 0, 0 }, | |
231 | { 1, 0 }, | |
232 | { 2, 1 }, | |
233 | { 2, 3 }, }; | |
1da177e4 | 234 | |
4fb0f76d AC |
235 | /* |
236 | * Master vs slave is synchronized above us but the slave register is | |
237 | * shared by the two hwifs so the corner case of two slave timeouts in | |
238 | * parallel must be locked. | |
239 | */ | |
240 | spin_lock_irqsave(&tune_lock, flags); | |
1da177e4 | 241 | pci_read_config_word(dev, master_port, &master_data); |
5ac24697 | 242 | |
30dfd12f | 243 | if (pio > 1) |
5ac24697 AC |
244 | control |= 1; /* Programmable timing on */ |
245 | if (drive->media == ide_disk) | |
246 | control |= 4; /* Prefetch, post write */ | |
30dfd12f | 247 | if (pio > 2) |
5ac24697 | 248 | control |= 2; /* IORDY */ |
1da177e4 | 249 | if (is_slave) { |
30dfd12f SS |
250 | master_data |= 0x4000; |
251 | master_data &= ~0x0070; | |
5ac24697 | 252 | if (pio > 1) { |
07af4276 SS |
253 | /* Set PPE, IE and TIME */ |
254 | master_data |= control << 4; | |
5ac24697 | 255 | } |
1da177e4 | 256 | pci_read_config_byte(dev, slave_port, &slave_data); |
07af4276 SS |
257 | slave_data &= hwif->channel ? 0x0f : 0xf0; |
258 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << | |
259 | (hwif->channel ? 4 : 0); | |
1da177e4 | 260 | } else { |
30dfd12f | 261 | master_data &= ~0x3307; |
5ac24697 | 262 | if (pio > 1) { |
1da177e4 | 263 | /* enable PPE, IE and TIME */ |
07af4276 | 264 | master_data |= control; |
5ac24697 | 265 | } |
07af4276 | 266 | master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); |
1da177e4 LT |
267 | } |
268 | pci_write_config_word(dev, master_port, master_data); | |
269 | if (is_slave) | |
270 | pci_write_config_byte(dev, slave_port, slave_data); | |
4fb0f76d | 271 | spin_unlock_irqrestore(&tune_lock, flags); |
1da177e4 LT |
272 | } |
273 | ||
07af4276 SS |
274 | /** |
275 | * piix_tune_drive - tune a drive attached to PIIX | |
276 | * @drive: drive to tune | |
277 | * @pio: desired PIO mode | |
278 | * | |
279 | * Set the drive's PIO mode (might be useful if drive is not registered | |
280 | * in CMOS for any reason). | |
281 | */ | |
282 | static void piix_tune_drive (ide_drive_t *drive, u8 pio) | |
283 | { | |
284 | pio = ide_get_best_pio_mode(drive, pio, 4, NULL); | |
285 | piix_tune_pio(drive, pio); | |
286 | (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio); | |
287 | } | |
288 | ||
1da177e4 LT |
289 | /** |
290 | * piix_tune_chipset - tune a PIIX interface | |
291 | * @drive: IDE drive to tune | |
292 | * @xferspeed: speed to configure | |
293 | * | |
294 | * Set a PIIX interface channel to the desired speeds. This involves | |
295 | * requires the right timing data into the PIIX configuration space | |
296 | * then setting the drive parameters appropriately | |
297 | */ | |
298 | ||
299 | static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed) | |
300 | { | |
301 | ide_hwif_t *hwif = HWIF(drive); | |
302 | struct pci_dev *dev = hwif->pci_dev; | |
303 | u8 maslave = hwif->channel ? 0x42 : 0x40; | |
304 | u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed); | |
305 | int a_speed = 3 << (drive->dn * 4); | |
306 | int u_flag = 1 << drive->dn; | |
307 | int v_flag = 0x01 << drive->dn; | |
308 | int w_flag = 0x10 << drive->dn; | |
309 | int u_speed = 0; | |
310 | int sitre; | |
311 | u16 reg4042, reg4a; | |
312 | u8 reg48, reg54, reg55; | |
313 | ||
314 | pci_read_config_word(dev, maslave, ®4042); | |
315 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
316 | pci_read_config_byte(dev, 0x48, ®48); | |
317 | pci_read_config_word(dev, 0x4a, ®4a); | |
318 | pci_read_config_byte(dev, 0x54, ®54); | |
319 | pci_read_config_byte(dev, 0x55, ®55); | |
320 | ||
321 | switch(speed) { | |
322 | case XFER_UDMA_4: | |
323 | case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break; | |
324 | case XFER_UDMA_5: | |
325 | case XFER_UDMA_3: | |
326 | case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break; | |
327 | case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break; | |
328 | case XFER_MW_DMA_2: | |
329 | case XFER_MW_DMA_1: | |
330 | case XFER_SW_DMA_2: break; | |
331 | case XFER_PIO_4: | |
332 | case XFER_PIO_3: | |
333 | case XFER_PIO_2: | |
334 | case XFER_PIO_0: break; | |
335 | default: return -1; | |
336 | } | |
337 | ||
338 | if (speed >= XFER_UDMA_0) { | |
339 | if (!(reg48 & u_flag)) | |
340 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); | |
341 | if (speed == XFER_UDMA_5) { | |
342 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); | |
343 | } else { | |
344 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
345 | } | |
346 | if ((reg4a & a_speed) != u_speed) | |
347 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); | |
348 | if (speed > XFER_UDMA_2) { | |
349 | if (!(reg54 & v_flag)) | |
350 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); | |
351 | } else | |
352 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
353 | } else { | |
354 | if (reg48 & u_flag) | |
355 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); | |
356 | if (reg4a & a_speed) | |
357 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
358 | if (reg54 & v_flag) | |
359 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
360 | if (reg55 & w_flag) | |
361 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
362 | } | |
363 | ||
07af4276 SS |
364 | piix_tune_pio(drive, piix_dma_2_pio(speed)); |
365 | return ide_config_drive_speed(drive, speed); | |
1da177e4 LT |
366 | } |
367 | ||
1da177e4 LT |
368 | /** |
369 | * piix_config_drive_for_dma - configure drive for DMA | |
370 | * @drive: IDE drive to configure | |
371 | * | |
372 | * Set up a PIIX interface channel for the best available speed. | |
44854add SS |
373 | * We prefer UDMA if it is available and then MWDMA. If DMA is |
374 | * not available we switch to PIO and return 0. | |
1da177e4 LT |
375 | */ |
376 | ||
377 | static int piix_config_drive_for_dma (ide_drive_t *drive) | |
378 | { | |
379 | u8 speed = ide_dma_speed(drive, piix_ratemask(drive)); | |
1da177e4 | 380 | |
44854add SS |
381 | /* |
382 | * If no DMA speed was available or the chipset has DMA bugs | |
383 | * then disable DMA and use PIO | |
384 | */ | |
74594fd1 | 385 | if (!speed) |
44854add | 386 | return 0; |
1da177e4 LT |
387 | |
388 | (void) piix_tune_chipset(drive, speed); | |
389 | return ide_dma_enable(drive); | |
390 | } | |
391 | ||
392 | /** | |
393 | * piix_config_drive_xfer_rate - set up an IDE device | |
394 | * @drive: IDE drive to configure | |
395 | * | |
396 | * Set up the PIIX interface for the best available speed on this | |
397 | * interface, preferring DMA to PIO. | |
398 | */ | |
399 | ||
400 | static int piix_config_drive_xfer_rate (ide_drive_t *drive) | |
401 | { | |
1da177e4 LT |
402 | drive->init_speed = 0; |
403 | ||
7569e8dc | 404 | if (ide_use_dma(drive) && piix_config_drive_for_dma(drive)) |
3608b5d7 | 405 | return 0; |
1da177e4 | 406 | |
d8f4469d | 407 | if (ide_use_fast_pio(drive)) |
07af4276 | 408 | piix_tune_drive(drive, 255); |
d8f4469d | 409 | |
3608b5d7 | 410 | return -1; |
1da177e4 LT |
411 | } |
412 | ||
413 | /** | |
f0dd8712 AL |
414 | * piix_is_ichx - check if ICHx |
415 | * @dev: PCI device to check | |
1da177e4 | 416 | * |
f0dd8712 | 417 | * returns 1 if ICHx, 0 otherwise. |
1da177e4 | 418 | */ |
f0dd8712 | 419 | static int piix_is_ichx(struct pci_dev *dev) |
1da177e4 | 420 | { |
f0dd8712 | 421 | switch (dev->device) { |
1da177e4 LT |
422 | case PCI_DEVICE_ID_INTEL_82801EB_1: |
423 | case PCI_DEVICE_ID_INTEL_82801AA_1: | |
424 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
425 | case PCI_DEVICE_ID_INTEL_82801BA_8: | |
426 | case PCI_DEVICE_ID_INTEL_82801BA_9: | |
427 | case PCI_DEVICE_ID_INTEL_82801CA_10: | |
428 | case PCI_DEVICE_ID_INTEL_82801CA_11: | |
429 | case PCI_DEVICE_ID_INTEL_82801DB_1: | |
430 | case PCI_DEVICE_ID_INTEL_82801DB_10: | |
431 | case PCI_DEVICE_ID_INTEL_82801DB_11: | |
432 | case PCI_DEVICE_ID_INTEL_82801EB_11: | |
433 | case PCI_DEVICE_ID_INTEL_82801E_11: | |
434 | case PCI_DEVICE_ID_INTEL_ESB_2: | |
435 | case PCI_DEVICE_ID_INTEL_ICH6_19: | |
436 | case PCI_DEVICE_ID_INTEL_ICH7_21: | |
d69332b8 | 437 | case PCI_DEVICE_ID_INTEL_ESB2_18: |
b7bed9ec | 438 | case PCI_DEVICE_ID_INTEL_ICH8_6: |
f0dd8712 | 439 | return 1; |
1da177e4 LT |
440 | } |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
f0dd8712 AL |
445 | /** |
446 | * init_chipset_piix - set up the PIIX chipset | |
447 | * @dev: PCI device to set up | |
448 | * @name: Name of the device | |
449 | * | |
450 | * Initialize the PCI device as required. For the PIIX this turns | |
451 | * out to be nice and simple | |
452 | */ | |
453 | ||
454 | static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name) | |
455 | { | |
456 | if (piix_is_ichx(dev)) { | |
457 | unsigned int extra = 0; | |
458 | pci_read_config_dword(dev, 0x54, &extra); | |
459 | pci_write_config_dword(dev, 0x54, extra|0x400); | |
460 | } | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
465 | /** | |
466 | * piix_dma_clear_irq - clear BMDMA status | |
467 | * @drive: IDE drive to clear | |
468 | * | |
469 | * Called from ide_intr() for PIO interrupts | |
470 | * to clear BMDMA status as needed by ICHx | |
471 | */ | |
472 | static void piix_dma_clear_irq(ide_drive_t *drive) | |
473 | { | |
474 | ide_hwif_t *hwif = HWIF(drive); | |
475 | u8 dma_stat; | |
476 | ||
477 | /* clear the INTR & ERROR bits */ | |
478 | dma_stat = hwif->INB(hwif->dma_status); | |
479 | /* Should we force the bit as well ? */ | |
480 | hwif->OUTB(dma_stat, hwif->dma_status); | |
481 | } | |
482 | ||
74594fd1 BZ |
483 | static int __devinit piix_cable_detect(ide_hwif_t *hwif) |
484 | { | |
485 | struct pci_dev *dev = hwif->pci_dev; | |
486 | u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30; | |
487 | ||
488 | pci_read_config_byte(dev, 0x54, ®54h); | |
489 | ||
490 | return (reg54h & mask) ? 1 : 0; | |
491 | } | |
492 | ||
1da177e4 LT |
493 | /** |
494 | * init_hwif_piix - fill in the hwif for the PIIX | |
495 | * @hwif: IDE interface | |
496 | * | |
497 | * Set up the ide_hwif_t for the PIIX interface according to the | |
498 | * capabilities of the hardware. | |
499 | */ | |
500 | ||
501 | static void __devinit init_hwif_piix(ide_hwif_t *hwif) | |
502 | { | |
1da177e4 LT |
503 | #ifndef CONFIG_IA64 |
504 | if (!hwif->irq) | |
505 | hwif->irq = hwif->channel ? 15 : 14; | |
506 | #endif /* CONFIG_IA64 */ | |
507 | ||
508 | if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) { | |
509 | /* This is a painful system best to let it self tune for now */ | |
510 | return; | |
511 | } | |
512 | ||
513 | hwif->autodma = 0; | |
514 | hwif->tuneproc = &piix_tune_drive; | |
515 | hwif->speedproc = &piix_tune_chipset; | |
516 | hwif->drives[0].autotune = 1; | |
517 | hwif->drives[1].autotune = 1; | |
518 | ||
519 | if (!hwif->dma_base) | |
520 | return; | |
521 | ||
f0dd8712 AL |
522 | /* ICHx need to clear the bmdma status for all interrupts */ |
523 | if (piix_is_ichx(hwif->pci_dev)) | |
524 | hwif->ide_dma_clear_irq = &piix_dma_clear_irq; | |
525 | ||
1da177e4 LT |
526 | hwif->atapi_dma = 1; |
527 | hwif->ultra_mask = 0x3f; | |
528 | hwif->mwdma_mask = 0x06; | |
529 | hwif->swdma_mask = 0x04; | |
530 | ||
531 | switch(hwif->pci_dev->device) { | |
1da177e4 LT |
532 | case PCI_DEVICE_ID_INTEL_82371FB_0: |
533 | case PCI_DEVICE_ID_INTEL_82371FB_1: | |
534 | case PCI_DEVICE_ID_INTEL_82371SB_1: | |
535 | hwif->ultra_mask = 0x80; | |
536 | break; | |
537 | case PCI_DEVICE_ID_INTEL_82371AB: | |
538 | case PCI_DEVICE_ID_INTEL_82443MX_1: | |
539 | case PCI_DEVICE_ID_INTEL_82451NX: | |
540 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
541 | hwif->ultra_mask = 0x07; | |
542 | break; | |
543 | default: | |
74594fd1 BZ |
544 | if (!hwif->udma_four) |
545 | hwif->udma_four = piix_cable_detect(hwif); | |
1da177e4 LT |
546 | break; |
547 | } | |
548 | ||
74594fd1 BZ |
549 | if (no_piix_dma) |
550 | hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0; | |
551 | ||
1da177e4 LT |
552 | hwif->ide_dma_check = &piix_config_drive_xfer_rate; |
553 | if (!noautodma) | |
554 | hwif->autodma = 1; | |
555 | ||
556 | hwif->drives[1].autodma = hwif->autodma; | |
557 | hwif->drives[0].autodma = hwif->autodma; | |
558 | } | |
559 | ||
560 | #define DECLARE_PIIX_DEV(name_str) \ | |
561 | { \ | |
562 | .name = name_str, \ | |
563 | .init_chipset = init_chipset_piix, \ | |
564 | .init_hwif = init_hwif_piix, \ | |
565 | .channels = 2, \ | |
566 | .autodma = AUTODMA, \ | |
567 | .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ | |
568 | .bootable = ON_BOARD, \ | |
569 | } | |
570 | ||
571 | static ide_pci_device_t piix_pci_info[] __devinitdata = { | |
572 | /* 0 */ DECLARE_PIIX_DEV("PIIXa"), | |
573 | /* 1 */ DECLARE_PIIX_DEV("PIIXb"), | |
574 | ||
d2872239 SS |
575 | /* 2 */ |
576 | { /* | |
577 | * MPIIX actually has only a single IDE channel mapped to | |
578 | * the primary or secondary ports depending on the value | |
579 | * of the bit 14 of the IDETIM register at offset 0x6c | |
580 | */ | |
1da177e4 LT |
581 | .name = "MPIIX", |
582 | .init_hwif = init_hwif_piix, | |
583 | .channels = 2, | |
584 | .autodma = NODMA, | |
d2872239 | 585 | .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}}, |
1da177e4 | 586 | .bootable = ON_BOARD, |
d2872239 | 587 | .flags = IDEPCI_FLAG_ISA_PORTS |
1da177e4 LT |
588 | }, |
589 | ||
590 | /* 3 */ DECLARE_PIIX_DEV("PIIX3"), | |
591 | /* 4 */ DECLARE_PIIX_DEV("PIIX4"), | |
592 | /* 5 */ DECLARE_PIIX_DEV("ICH0"), | |
593 | /* 6 */ DECLARE_PIIX_DEV("PIIX4"), | |
594 | /* 7 */ DECLARE_PIIX_DEV("ICH"), | |
595 | /* 8 */ DECLARE_PIIX_DEV("PIIX4"), | |
596 | /* 9 */ DECLARE_PIIX_DEV("PIIX4"), | |
597 | /* 10 */ DECLARE_PIIX_DEV("ICH2"), | |
598 | /* 11 */ DECLARE_PIIX_DEV("ICH2M"), | |
599 | /* 12 */ DECLARE_PIIX_DEV("ICH3M"), | |
600 | /* 13 */ DECLARE_PIIX_DEV("ICH3"), | |
601 | /* 14 */ DECLARE_PIIX_DEV("ICH4"), | |
602 | /* 15 */ DECLARE_PIIX_DEV("ICH5"), | |
603 | /* 16 */ DECLARE_PIIX_DEV("C-ICH"), | |
604 | /* 17 */ DECLARE_PIIX_DEV("ICH4"), | |
605 | /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"), | |
606 | /* 19 */ DECLARE_PIIX_DEV("ICH5"), | |
607 | /* 20 */ DECLARE_PIIX_DEV("ICH6"), | |
608 | /* 21 */ DECLARE_PIIX_DEV("ICH7"), | |
609 | /* 22 */ DECLARE_PIIX_DEV("ICH4"), | |
d69332b8 | 610 | /* 23 */ DECLARE_PIIX_DEV("ESB2"), |
b7bed9ec | 611 | /* 24 */ DECLARE_PIIX_DEV("ICH8M"), |
1da177e4 LT |
612 | }; |
613 | ||
614 | /** | |
615 | * piix_init_one - called when a PIIX is found | |
616 | * @dev: the piix device | |
617 | * @id: the matching pci id | |
618 | * | |
619 | * Called when the PCI registration layer (or the IDE initialization) | |
620 | * finds a device matching our IDE device tables. | |
621 | */ | |
622 | ||
623 | static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
624 | { | |
625 | ide_pci_device_t *d = &piix_pci_info[id->driver_data]; | |
626 | ||
627 | return ide_setup_pci_device(dev, d); | |
628 | } | |
629 | ||
630 | /** | |
631 | * piix_check_450nx - Check for problem 450NX setup | |
632 | * | |
633 | * Check for the present of 450NX errata #19 and errata #25. If | |
634 | * they are found, disable use of DMA IDE | |
635 | */ | |
636 | ||
637 | static void __devinit piix_check_450nx(void) | |
638 | { | |
639 | struct pci_dev *pdev = NULL; | |
640 | u16 cfg; | |
641 | u8 rev; | |
1424e504 | 642 | while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL) |
1da177e4 LT |
643 | { |
644 | /* Look for 450NX PXB. Check for problem configurations | |
645 | A PCI quirk checks bit 6 already */ | |
646 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); | |
647 | pci_read_config_word(pdev, 0x41, &cfg); | |
648 | /* Only on the original revision: IDE DMA can hang */ | |
649 | if(rev == 0x00) | |
650 | no_piix_dma = 1; | |
651 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
652 | else if(cfg & (1<<14) && rev < 5) | |
653 | no_piix_dma = 2; | |
654 | } | |
655 | if(no_piix_dma) | |
656 | printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n"); | |
657 | if(no_piix_dma == 2) | |
658 | printk(KERN_WARNING "piix: A BIOS update may resolve this.\n"); | |
659 | } | |
660 | ||
661 | static struct pci_device_id piix_pci_tbl[] = { | |
662 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
663 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, | |
664 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
665 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, | |
666 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, | |
667 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5}, | |
668 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6}, | |
669 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7}, | |
670 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8}, | |
671 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9}, | |
672 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10}, | |
673 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11}, | |
674 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12}, | |
675 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13}, | |
676 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14}, | |
677 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15}, | |
678 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16}, | |
679 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17}, | |
680 | #ifdef CONFIG_BLK_DEV_IDE_SATA | |
681 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18}, | |
682 | #endif | |
683 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19}, | |
684 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20}, | |
685 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21}, | |
686 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22}, | |
d69332b8 | 687 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23}, |
b7bed9ec | 688 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 24}, |
1da177e4 LT |
689 | { 0, }, |
690 | }; | |
691 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
692 | ||
693 | static struct pci_driver driver = { | |
694 | .name = "PIIX_IDE", | |
695 | .id_table = piix_pci_tbl, | |
696 | .probe = piix_init_one, | |
697 | }; | |
698 | ||
699 | static int __init piix_ide_init(void) | |
700 | { | |
701 | piix_check_450nx(); | |
702 | return ide_pci_register_driver(&driver); | |
703 | } | |
704 | ||
705 | module_init(piix_ide_init); | |
706 | ||
707 | MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz"); | |
708 | MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE"); | |
709 | MODULE_LICENSE("GPL"); |