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1da177e4 | 1 | /* |
3f019eea | 2 | * linux/drivers/ide/pci/sc1200.c Version 0.97 Aug 3 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com> | |
5fd216bb BZ |
5 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
6 | * | |
1da177e4 LT |
7 | * May be copied or modified under the terms of the GNU General Public License |
8 | * | |
9 | * Development of this chipset driver was funded | |
10 | * by the nice folks at National Semiconductor. | |
11 | * | |
12 | * Documentation: | |
13 | * Available from National Semiconductor | |
14 | */ | |
15 | ||
1da177e4 LT |
16 | #include <linux/module.h> |
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/timer.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/hdreg.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/ide.h> | |
29 | #include <linux/pm.h> | |
30 | #include <asm/io.h> | |
31 | #include <asm/irq.h> | |
32 | ||
33 | #define SC1200_REV_A 0x00 | |
34 | #define SC1200_REV_B1 0x01 | |
35 | #define SC1200_REV_B3 0x02 | |
36 | #define SC1200_REV_C1 0x03 | |
37 | #define SC1200_REV_D1 0x04 | |
38 | ||
39 | #define PCI_CLK_33 0x00 | |
40 | #define PCI_CLK_48 0x01 | |
41 | #define PCI_CLK_66 0x02 | |
42 | #define PCI_CLK_33A 0x03 | |
43 | ||
44 | static unsigned short sc1200_get_pci_clock (void) | |
45 | { | |
46 | unsigned char chip_id, silicon_revision; | |
47 | unsigned int pci_clock; | |
48 | /* | |
49 | * Check the silicon revision, as not all versions of the chip | |
50 | * have the register with the fast PCI bus timings. | |
51 | */ | |
52 | chip_id = inb (0x903c); | |
53 | silicon_revision = inb (0x903d); | |
54 | ||
55 | // Read the fast pci clock frequency | |
56 | if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) { | |
57 | pci_clock = PCI_CLK_33; | |
58 | } else { | |
59 | // check clock generator configuration (cfcc) | |
60 | // the clock is in bits 8 and 9 of this word | |
61 | ||
62 | pci_clock = inw (0x901e); | |
63 | pci_clock >>= 8; | |
64 | pci_clock &= 0x03; | |
65 | if (pci_clock == PCI_CLK_33A) | |
66 | pci_clock = PCI_CLK_33; | |
67 | } | |
68 | return pci_clock; | |
69 | } | |
70 | ||
1da177e4 LT |
71 | /* |
72 | * Here are the standard PIO mode 0-4 timings for each "format". | |
73 | * Format-0 uses fast data reg timings, with slower command reg timings. | |
74 | * Format-1 uses fast timings for all registers, but won't work with all drives. | |
75 | */ | |
76 | static const unsigned int sc1200_pio_timings[4][5] = | |
77 | {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz | |
78 | {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz | |
79 | {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz | |
80 | {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz | |
81 | ||
82 | /* | |
83 | * After chip reset, the PIO timings are set to 0x00009172, which is not valid. | |
84 | */ | |
85 | //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172) | |
86 | ||
3c3f5d2c BZ |
87 | static void sc1200_tunepio(ide_drive_t *drive, u8 pio) |
88 | { | |
89 | ide_hwif_t *hwif = drive->hwif; | |
90 | struct pci_dev *pdev = hwif->pci_dev; | |
91 | unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0; | |
92 | ||
93 | pci_read_config_dword(pdev, basereg + 4, &format); | |
94 | format = (format >> 31) & 1; | |
95 | if (format) | |
96 | format += sc1200_get_pci_clock(); | |
97 | pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3), | |
98 | sc1200_pio_timings[format][pio]); | |
99 | } | |
100 | ||
5fd216bb BZ |
101 | /* |
102 | * The SC1200 specifies that two drives sharing a cable cannot mix | |
103 | * UDMA/MDMA. It has to be one or the other, for the pair, though | |
104 | * different timings can still be chosen for each drive. We could | |
105 | * set the appropriate timing bits on the fly, but that might be | |
106 | * a bit confusing. So, for now we statically handle this requirement | |
107 | * by looking at our mate drive to see what it is capable of, before | |
108 | * choosing a mode for our own drive. | |
109 | */ | |
110 | static u8 sc1200_udma_filter(ide_drive_t *drive) | |
1da177e4 | 111 | { |
5fd216bb BZ |
112 | ide_hwif_t *hwif = drive->hwif; |
113 | ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1]; | |
114 | struct hd_driveid *mateid = mate->id; | |
115 | u8 mask = hwif->ultra_mask; | |
116 | ||
117 | if (mate->present == 0) | |
118 | goto out; | |
119 | ||
120 | if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) { | |
121 | if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7)) | |
122 | goto out; | |
123 | if ((mateid->field_valid & 2) && (mateid->dma_mword & 7)) | |
124 | mask = 0; | |
1da177e4 | 125 | } |
5fd216bb BZ |
126 | out: |
127 | return mask; | |
1da177e4 LT |
128 | } |
129 | ||
88b2b32b | 130 | static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode) |
1da177e4 LT |
131 | { |
132 | ide_hwif_t *hwif = HWIF(drive); | |
133 | int unit = drive->select.b.unit; | |
134 | unsigned int reg, timings; | |
135 | unsigned short pci_clock; | |
136 | unsigned int basereg = hwif->channel ? 0x50 : 0x40; | |
137 | ||
4eed504d BZ |
138 | static const u32 udma_timing[3][3] = { |
139 | { 0x00921250, 0x00911140, 0x00911030 }, | |
140 | { 0x00932470, 0x00922260, 0x00922140 }, | |
141 | { 0x009436a1, 0x00933481, 0x00923261 }, | |
142 | }; | |
143 | ||
144 | static const u32 mwdma_timing[3][3] = { | |
145 | { 0x00077771, 0x00012121, 0x00002020 }, | |
146 | { 0x000bbbb2, 0x00024241, 0x00013131 }, | |
147 | { 0x000ffff3, 0x00035352, 0x00015151 }, | |
148 | }; | |
149 | ||
1da177e4 LT |
150 | pci_clock = sc1200_get_pci_clock(); |
151 | ||
152 | /* | |
1da177e4 LT |
153 | * Note that each DMA mode has several timings associated with it. |
154 | * The correct timing depends on the fast PCI clock freq. | |
155 | */ | |
4eed504d BZ |
156 | |
157 | if (mode >= XFER_UDMA_0) | |
158 | timings = udma_timing[pci_clock][mode - XFER_UDMA_0]; | |
159 | else | |
160 | timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0]; | |
1da177e4 LT |
161 | |
162 | if (unit == 0) { /* are we configuring drive0? */ | |
163 | pci_read_config_dword(hwif->pci_dev, basereg+4, ®); | |
164 | timings |= reg & 0x80000000; /* preserve PIO format bit */ | |
165 | pci_write_config_dword(hwif->pci_dev, basereg+4, timings); | |
166 | } else { | |
167 | pci_write_config_dword(hwif->pci_dev, basereg+12, timings); | |
168 | } | |
1da177e4 LT |
169 | } |
170 | ||
1da177e4 LT |
171 | /* Replacement for the standard ide_dma_end action in |
172 | * dma_proc. | |
173 | * | |
174 | * returns 1 on error, 0 otherwise | |
175 | */ | |
176 | static int sc1200_ide_dma_end (ide_drive_t *drive) | |
177 | { | |
178 | ide_hwif_t *hwif = HWIF(drive); | |
179 | unsigned long dma_base = hwif->dma_base; | |
180 | byte dma_stat; | |
181 | ||
182 | dma_stat = inb(dma_base+2); /* get DMA status */ | |
183 | ||
184 | if (!(dma_stat & 4)) | |
185 | printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n", | |
186 | dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2)); | |
187 | ||
188 | outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */ | |
189 | outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */ | |
190 | ||
191 | drive->waiting_for_dma = 0; | |
192 | ide_destroy_dmatable(drive); /* purge DMA mappings */ | |
193 | ||
194 | return (dma_stat & 7) != 4; /* verify good DMA status */ | |
195 | } | |
196 | ||
197 | /* | |
26bcb879 | 198 | * sc1200_set_pio_mode() handles setting of PIO modes |
1da177e4 LT |
199 | * for both the chipset and drive. |
200 | * | |
201 | * All existing BIOSs for this chipset guarantee that all drives | |
202 | * will have valid default PIO timings set up before we get here. | |
203 | */ | |
26bcb879 BZ |
204 | |
205 | static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio) | |
1da177e4 LT |
206 | { |
207 | ide_hwif_t *hwif = HWIF(drive); | |
1da177e4 LT |
208 | int mode = -1; |
209 | ||
a01ba401 | 210 | /* |
26bcb879 | 211 | * bad abuse of ->set_pio_mode interface |
a01ba401 | 212 | */ |
1da177e4 LT |
213 | switch (pio) { |
214 | case 200: mode = XFER_UDMA_0; break; | |
215 | case 201: mode = XFER_UDMA_1; break; | |
216 | case 202: mode = XFER_UDMA_2; break; | |
217 | case 100: mode = XFER_MW_DMA_0; break; | |
218 | case 101: mode = XFER_MW_DMA_1; break; | |
219 | case 102: mode = XFER_MW_DMA_2; break; | |
220 | } | |
221 | if (mode != -1) { | |
222 | printk("SC1200: %s: changing (U)DMA mode\n", drive->name); | |
a01ba401 | 223 | hwif->dma_off_quietly(drive); |
88b2b32b | 224 | if (ide_set_dma_mode(drive, mode) == 0) |
a01ba401 | 225 | hwif->dma_host_on(drive); |
1da177e4 LT |
226 | return; |
227 | } | |
228 | ||
88b2b32b | 229 | sc1200_tunepio(drive, pio); |
1da177e4 LT |
230 | } |
231 | ||
b86cc29d | 232 | #ifdef CONFIG_PM |
7c0e2666 BZ |
233 | struct sc1200_saved_state { |
234 | u32 regs[8]; | |
235 | }; | |
1da177e4 | 236 | |
3bfffd97 | 237 | static int sc1200_suspend (struct pci_dev *dev, pm_message_t state) |
1da177e4 | 238 | { |
ca078bae | 239 | printk("SC1200: suspend(%u)\n", state.event); |
1da177e4 | 240 | |
7c0e2666 BZ |
241 | /* |
242 | * we only save state when going from full power to less | |
243 | */ | |
ca078bae | 244 | if (state.event == PM_EVENT_ON) { |
7c0e2666 BZ |
245 | struct sc1200_saved_state *ss; |
246 | unsigned int r; | |
247 | ||
248 | /* | |
249 | * allocate a permanent save area, if not already allocated | |
250 | */ | |
251 | ss = (struct sc1200_saved_state *)pci_get_drvdata(dev); | |
252 | if (ss == NULL) { | |
253 | ss = kmalloc(sizeof(*ss), GFP_KERNEL); | |
254 | if (ss == NULL) | |
255 | return -ENOMEM; | |
256 | pci_set_drvdata(dev, ss); | |
1da177e4 | 257 | } |
1da177e4 | 258 | |
7c0e2666 BZ |
259 | /* |
260 | * save timing registers | |
261 | * (this may be unnecessary if BIOS also does it) | |
262 | */ | |
263 | for (r = 0; r < 8; r++) | |
264 | pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]); | |
265 | } | |
1da177e4 LT |
266 | |
267 | pci_disable_device(dev); | |
ca078bae | 268 | pci_set_power_state(dev, pci_choose_state(dev, state)); |
1da177e4 LT |
269 | return 0; |
270 | } | |
271 | ||
272 | static int sc1200_resume (struct pci_dev *dev) | |
273 | { | |
7c0e2666 BZ |
274 | struct sc1200_saved_state *ss; |
275 | unsigned int r; | |
276 | int i; | |
9d434813 JG |
277 | |
278 | i = pci_enable_device(dev); | |
279 | if (i) | |
280 | return i; | |
1da177e4 | 281 | |
7c0e2666 BZ |
282 | ss = (struct sc1200_saved_state *)pci_get_drvdata(dev); |
283 | ||
284 | /* | |
285 | * restore timing registers | |
286 | * (this may be unnecessary if BIOS also does it) | |
287 | */ | |
288 | if (ss) { | |
289 | for (r = 0; r < 8; r++) | |
290 | pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]); | |
1da177e4 | 291 | } |
7c0e2666 | 292 | |
1da177e4 LT |
293 | return 0; |
294 | } | |
b86cc29d | 295 | #endif |
1da177e4 LT |
296 | |
297 | /* | |
298 | * This gets invoked by the IDE driver once for each channel, | |
299 | * and performs channel-specific pre-initialization before drive probing. | |
300 | */ | |
6a6e1b1c | 301 | static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif) |
1da177e4 | 302 | { |
88ae4d8c BZ |
303 | hwif->set_pio_mode = &sc1200_set_pio_mode; |
304 | hwif->set_dma_mode = &sc1200_set_dma_mode; | |
305 | ||
306 | if (hwif->dma_base == 0) | |
307 | return; | |
308 | ||
309 | hwif->udma_filter = sc1200_udma_filter; | |
88ae4d8c | 310 | hwif->ide_dma_end = &sc1200_ide_dma_end; |
1da177e4 LT |
311 | } |
312 | ||
85620436 | 313 | static const struct ide_port_info sc1200_chipset __devinitdata = { |
1da177e4 LT |
314 | .name = "SC1200", |
315 | .init_hwif = init_hwif_sc1200, | |
1c51361a BZ |
316 | .host_flags = IDE_HFLAG_SERIALIZE | |
317 | IDE_HFLAG_POST_SET_MODE | | |
318 | IDE_HFLAG_ABUSE_DMA_MODES | | |
7cab14a7 | 319 | IDE_HFLAG_BOOTABLE, |
4099d143 | 320 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
321 | .mwdma_mask = ATA_MWDMA2, |
322 | .udma_mask = ATA_UDMA2, | |
1da177e4 LT |
323 | }; |
324 | ||
325 | static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
326 | { | |
327 | return ide_setup_pci_device(dev, &sc1200_chipset); | |
328 | } | |
329 | ||
9cbcc5e3 BZ |
330 | static const struct pci_device_id sc1200_pci_tbl[] = { |
331 | { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0}, | |
1da177e4 LT |
332 | { 0, }, |
333 | }; | |
334 | MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl); | |
335 | ||
336 | static struct pci_driver driver = { | |
337 | .name = "SC1200_IDE", | |
338 | .id_table = sc1200_pci_tbl, | |
339 | .probe = sc1200_init_one, | |
b86cc29d | 340 | #ifdef CONFIG_PM |
1da177e4 LT |
341 | .suspend = sc1200_suspend, |
342 | .resume = sc1200_resume, | |
b86cc29d | 343 | #endif |
1da177e4 LT |
344 | }; |
345 | ||
82ab1eec | 346 | static int __init sc1200_ide_init(void) |
1da177e4 LT |
347 | { |
348 | return ide_pci_register_driver(&driver); | |
349 | } | |
350 | ||
351 | module_init(sc1200_ide_init); | |
352 | ||
353 | MODULE_AUTHOR("Mark Lord"); | |
354 | MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE"); | |
355 | MODULE_LICENSE("GPL"); |