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1da177e4 | 1 | /* |
a01ba401 | 2 | * linux/drivers/ide/pci/sc1200.c Version 0.93 Mar 10 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com> | |
5fd216bb BZ |
5 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
6 | * | |
1da177e4 LT |
7 | * May be copied or modified under the terms of the GNU General Public License |
8 | * | |
9 | * Development of this chipset driver was funded | |
10 | * by the nice folks at National Semiconductor. | |
11 | * | |
12 | * Documentation: | |
13 | * Available from National Semiconductor | |
14 | */ | |
15 | ||
1da177e4 LT |
16 | #include <linux/module.h> |
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/timer.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/hdreg.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/ide.h> | |
29 | #include <linux/pm.h> | |
30 | #include <asm/io.h> | |
31 | #include <asm/irq.h> | |
32 | ||
33 | #define SC1200_REV_A 0x00 | |
34 | #define SC1200_REV_B1 0x01 | |
35 | #define SC1200_REV_B3 0x02 | |
36 | #define SC1200_REV_C1 0x03 | |
37 | #define SC1200_REV_D1 0x04 | |
38 | ||
39 | #define PCI_CLK_33 0x00 | |
40 | #define PCI_CLK_48 0x01 | |
41 | #define PCI_CLK_66 0x02 | |
42 | #define PCI_CLK_33A 0x03 | |
43 | ||
44 | static unsigned short sc1200_get_pci_clock (void) | |
45 | { | |
46 | unsigned char chip_id, silicon_revision; | |
47 | unsigned int pci_clock; | |
48 | /* | |
49 | * Check the silicon revision, as not all versions of the chip | |
50 | * have the register with the fast PCI bus timings. | |
51 | */ | |
52 | chip_id = inb (0x903c); | |
53 | silicon_revision = inb (0x903d); | |
54 | ||
55 | // Read the fast pci clock frequency | |
56 | if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) { | |
57 | pci_clock = PCI_CLK_33; | |
58 | } else { | |
59 | // check clock generator configuration (cfcc) | |
60 | // the clock is in bits 8 and 9 of this word | |
61 | ||
62 | pci_clock = inw (0x901e); | |
63 | pci_clock >>= 8; | |
64 | pci_clock &= 0x03; | |
65 | if (pci_clock == PCI_CLK_33A) | |
66 | pci_clock = PCI_CLK_33; | |
67 | } | |
68 | return pci_clock; | |
69 | } | |
70 | ||
71 | extern char *ide_xfer_verbose (byte xfer_rate); | |
72 | ||
73 | /* | |
74 | * Set a new transfer mode at the drive | |
75 | */ | |
76 | static int sc1200_set_xfer_mode (ide_drive_t *drive, byte mode) | |
77 | { | |
78 | printk("%s: sc1200_set_xfer_mode(%s)\n", drive->name, ide_xfer_verbose(mode)); | |
79 | return ide_config_drive_speed(drive, mode); | |
80 | } | |
81 | ||
82 | /* | |
83 | * Here are the standard PIO mode 0-4 timings for each "format". | |
84 | * Format-0 uses fast data reg timings, with slower command reg timings. | |
85 | * Format-1 uses fast timings for all registers, but won't work with all drives. | |
86 | */ | |
87 | static const unsigned int sc1200_pio_timings[4][5] = | |
88 | {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz | |
89 | {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz | |
90 | {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz | |
91 | {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz | |
92 | ||
93 | /* | |
94 | * After chip reset, the PIO timings are set to 0x00009172, which is not valid. | |
95 | */ | |
96 | //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172) | |
97 | ||
5fd216bb BZ |
98 | /* |
99 | * The SC1200 specifies that two drives sharing a cable cannot mix | |
100 | * UDMA/MDMA. It has to be one or the other, for the pair, though | |
101 | * different timings can still be chosen for each drive. We could | |
102 | * set the appropriate timing bits on the fly, but that might be | |
103 | * a bit confusing. So, for now we statically handle this requirement | |
104 | * by looking at our mate drive to see what it is capable of, before | |
105 | * choosing a mode for our own drive. | |
106 | */ | |
107 | static u8 sc1200_udma_filter(ide_drive_t *drive) | |
1da177e4 | 108 | { |
5fd216bb BZ |
109 | ide_hwif_t *hwif = drive->hwif; |
110 | ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1]; | |
111 | struct hd_driveid *mateid = mate->id; | |
112 | u8 mask = hwif->ultra_mask; | |
113 | ||
114 | if (mate->present == 0) | |
115 | goto out; | |
116 | ||
117 | if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) { | |
118 | if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7)) | |
119 | goto out; | |
120 | if ((mateid->field_valid & 2) && (mateid->dma_mword & 7)) | |
121 | mask = 0; | |
1da177e4 | 122 | } |
5fd216bb BZ |
123 | out: |
124 | return mask; | |
1da177e4 LT |
125 | } |
126 | ||
127 | /* | |
128 | * sc1200_config_dma2() handles selection/setting of DMA/UDMA modes | |
129 | * for both the chipset and drive. | |
130 | */ | |
131 | static int sc1200_config_dma2 (ide_drive_t *drive, int mode) | |
132 | { | |
133 | ide_hwif_t *hwif = HWIF(drive); | |
134 | int unit = drive->select.b.unit; | |
135 | unsigned int reg, timings; | |
136 | unsigned short pci_clock; | |
137 | unsigned int basereg = hwif->channel ? 0x50 : 0x40; | |
138 | ||
1da177e4 LT |
139 | /* |
140 | * Tell the drive to switch to the new mode; abort on failure. | |
141 | */ | |
142 | if (!mode || sc1200_set_xfer_mode(drive, mode)) { | |
143 | printk("SC1200: set xfer mode failure\n"); | |
144 | return 1; /* failure */ | |
145 | } | |
146 | ||
147 | pci_clock = sc1200_get_pci_clock(); | |
148 | ||
149 | /* | |
150 | * Now tune the chipset to match the drive: | |
151 | * | |
152 | * Note that each DMA mode has several timings associated with it. | |
153 | * The correct timing depends on the fast PCI clock freq. | |
154 | */ | |
155 | timings = 0; | |
156 | switch (mode) { | |
157 | case XFER_UDMA_0: | |
158 | switch (pci_clock) { | |
159 | case PCI_CLK_33: timings = 0x00921250; break; | |
160 | case PCI_CLK_48: timings = 0x00932470; break; | |
161 | case PCI_CLK_66: timings = 0x009436a1; break; | |
162 | } | |
163 | break; | |
164 | case XFER_UDMA_1: | |
165 | switch (pci_clock) { | |
166 | case PCI_CLK_33: timings = 0x00911140; break; | |
167 | case PCI_CLK_48: timings = 0x00922260; break; | |
168 | case PCI_CLK_66: timings = 0x00933481; break; | |
169 | } | |
170 | break; | |
171 | case XFER_UDMA_2: | |
172 | switch (pci_clock) { | |
173 | case PCI_CLK_33: timings = 0x00911030; break; | |
174 | case PCI_CLK_48: timings = 0x00922140; break; | |
175 | case PCI_CLK_66: timings = 0x00923261; break; | |
176 | } | |
177 | break; | |
178 | case XFER_MW_DMA_0: | |
179 | switch (pci_clock) { | |
180 | case PCI_CLK_33: timings = 0x00077771; break; | |
181 | case PCI_CLK_48: timings = 0x000bbbb2; break; | |
182 | case PCI_CLK_66: timings = 0x000ffff3; break; | |
183 | } | |
184 | break; | |
185 | case XFER_MW_DMA_1: | |
186 | switch (pci_clock) { | |
187 | case PCI_CLK_33: timings = 0x00012121; break; | |
188 | case PCI_CLK_48: timings = 0x00024241; break; | |
189 | case PCI_CLK_66: timings = 0x00035352; break; | |
190 | } | |
191 | break; | |
192 | case XFER_MW_DMA_2: | |
193 | switch (pci_clock) { | |
194 | case PCI_CLK_33: timings = 0x00002020; break; | |
195 | case PCI_CLK_48: timings = 0x00013131; break; | |
196 | case PCI_CLK_66: timings = 0x00015151; break; | |
197 | } | |
198 | break; | |
199 | } | |
200 | ||
201 | if (timings == 0) { | |
202 | printk("%s: sc1200_config_dma: huh? mode=%02x clk=%x \n", drive->name, mode, pci_clock); | |
203 | return 1; /* failure */ | |
204 | } | |
205 | ||
206 | if (unit == 0) { /* are we configuring drive0? */ | |
207 | pci_read_config_dword(hwif->pci_dev, basereg+4, ®); | |
208 | timings |= reg & 0x80000000; /* preserve PIO format bit */ | |
209 | pci_write_config_dword(hwif->pci_dev, basereg+4, timings); | |
210 | } else { | |
211 | pci_write_config_dword(hwif->pci_dev, basereg+12, timings); | |
212 | } | |
213 | ||
3608b5d7 | 214 | return 0; /* success */ |
1da177e4 LT |
215 | } |
216 | ||
217 | /* | |
218 | * sc1200_config_dma() handles selection/setting of DMA/UDMA modes | |
219 | * for both the chipset and drive. | |
220 | */ | |
221 | static int sc1200_config_dma (ide_drive_t *drive) | |
222 | { | |
5fd216bb BZ |
223 | u8 mode = 0; |
224 | ||
225 | if (ide_use_dma(drive)) | |
226 | mode = ide_max_dma_mode(drive); | |
227 | ||
228 | return sc1200_config_dma2(drive, mode); | |
1da177e4 LT |
229 | } |
230 | ||
231 | ||
232 | /* Replacement for the standard ide_dma_end action in | |
233 | * dma_proc. | |
234 | * | |
235 | * returns 1 on error, 0 otherwise | |
236 | */ | |
237 | static int sc1200_ide_dma_end (ide_drive_t *drive) | |
238 | { | |
239 | ide_hwif_t *hwif = HWIF(drive); | |
240 | unsigned long dma_base = hwif->dma_base; | |
241 | byte dma_stat; | |
242 | ||
243 | dma_stat = inb(dma_base+2); /* get DMA status */ | |
244 | ||
245 | if (!(dma_stat & 4)) | |
246 | printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n", | |
247 | dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2)); | |
248 | ||
249 | outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */ | |
250 | outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */ | |
251 | ||
252 | drive->waiting_for_dma = 0; | |
253 | ide_destroy_dmatable(drive); /* purge DMA mappings */ | |
254 | ||
255 | return (dma_stat & 7) != 4; /* verify good DMA status */ | |
256 | } | |
257 | ||
258 | /* | |
259 | * sc1200_tuneproc() handles selection/setting of PIO modes | |
260 | * for both the chipset and drive. | |
261 | * | |
262 | * All existing BIOSs for this chipset guarantee that all drives | |
263 | * will have valid default PIO timings set up before we get here. | |
264 | */ | |
265 | static void sc1200_tuneproc (ide_drive_t *drive, byte pio) /* mode=255 means "autotune" */ | |
266 | { | |
267 | ide_hwif_t *hwif = HWIF(drive); | |
268 | unsigned int format; | |
269 | static byte modes[5] = {XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4}; | |
270 | int mode = -1; | |
271 | ||
a01ba401 BZ |
272 | /* |
273 | * bad abuse of ->tuneproc interface | |
274 | */ | |
1da177e4 LT |
275 | switch (pio) { |
276 | case 200: mode = XFER_UDMA_0; break; | |
277 | case 201: mode = XFER_UDMA_1; break; | |
278 | case 202: mode = XFER_UDMA_2; break; | |
279 | case 100: mode = XFER_MW_DMA_0; break; | |
280 | case 101: mode = XFER_MW_DMA_1; break; | |
281 | case 102: mode = XFER_MW_DMA_2; break; | |
282 | } | |
283 | if (mode != -1) { | |
284 | printk("SC1200: %s: changing (U)DMA mode\n", drive->name); | |
a01ba401 BZ |
285 | hwif->dma_off_quietly(drive); |
286 | if (sc1200_config_dma2(drive, mode) == 0) | |
287 | hwif->dma_host_on(drive); | |
1da177e4 LT |
288 | return; |
289 | } | |
290 | ||
291 | pio = ide_get_best_pio_mode(drive, pio, 4, NULL); | |
292 | printk("SC1200: %s: setting PIO mode%d\n", drive->name, pio); | |
293 | if (!sc1200_set_xfer_mode(drive, modes[pio])) { | |
294 | unsigned int basereg = hwif->channel ? 0x50 : 0x40; | |
295 | pci_read_config_dword (hwif->pci_dev, basereg+4, &format); | |
296 | format = (format >> 31) & 1; | |
297 | if (format) | |
298 | format += sc1200_get_pci_clock(); | |
299 | pci_write_config_dword(hwif->pci_dev, basereg + (drive->select.b.unit << 3), sc1200_pio_timings[format][pio]); | |
300 | } | |
301 | } | |
302 | ||
b86cc29d | 303 | #ifdef CONFIG_PM |
1da177e4 LT |
304 | static ide_hwif_t *lookup_pci_dev (ide_hwif_t *prev, struct pci_dev *dev) |
305 | { | |
306 | int h; | |
307 | ||
308 | for (h = 0; h < MAX_HWIFS; h++) { | |
309 | ide_hwif_t *hwif = &ide_hwifs[h]; | |
310 | if (prev) { | |
311 | if (hwif == prev) | |
312 | prev = NULL; // found previous, now look for next match | |
313 | } else { | |
314 | if (hwif && hwif->pci_dev == dev) | |
315 | return hwif; // found next match | |
316 | } | |
317 | } | |
318 | return NULL; // not found | |
319 | } | |
320 | ||
321 | typedef struct sc1200_saved_state_s { | |
322 | __u32 regs[4]; | |
323 | } sc1200_saved_state_t; | |
324 | ||
325 | ||
3bfffd97 | 326 | static int sc1200_suspend (struct pci_dev *dev, pm_message_t state) |
1da177e4 LT |
327 | { |
328 | ide_hwif_t *hwif = NULL; | |
329 | ||
ca078bae | 330 | printk("SC1200: suspend(%u)\n", state.event); |
1da177e4 | 331 | |
ca078bae | 332 | if (state.event == PM_EVENT_ON) { |
1da177e4 LT |
333 | // we only save state when going from full power to less |
334 | ||
335 | // | |
336 | // Loop over all interfaces that are part of this PCI device: | |
337 | // | |
338 | while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) { | |
339 | sc1200_saved_state_t *ss; | |
340 | unsigned int basereg, r; | |
341 | // | |
342 | // allocate a permanent save area, if not already allocated | |
343 | // | |
344 | ss = (sc1200_saved_state_t *)hwif->config_data; | |
345 | if (ss == NULL) { | |
346 | ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL); | |
347 | if (ss == NULL) | |
348 | return -ENOMEM; | |
349 | hwif->config_data = (unsigned long)ss; | |
350 | } | |
351 | ss = (sc1200_saved_state_t *)hwif->config_data; | |
352 | // | |
353 | // Save timing registers: this may be unnecessary if | |
354 | // BIOS also does it | |
355 | // | |
356 | basereg = hwif->channel ? 0x50 : 0x40; | |
357 | for (r = 0; r < 4; ++r) { | |
358 | pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]); | |
359 | } | |
360 | } | |
361 | } | |
362 | ||
363 | /* You don't need to iterate over disks -- sysfs should have done that for you already */ | |
364 | ||
365 | pci_disable_device(dev); | |
ca078bae PM |
366 | pci_set_power_state(dev, pci_choose_state(dev, state)); |
367 | dev->current_state = state.event; | |
1da177e4 LT |
368 | return 0; |
369 | } | |
370 | ||
371 | static int sc1200_resume (struct pci_dev *dev) | |
372 | { | |
373 | ide_hwif_t *hwif = NULL; | |
374 | ||
ca078bae PM |
375 | pci_set_power_state(dev, PCI_D0); // bring chip back from sleep state |
376 | dev->current_state = PM_EVENT_ON; | |
1da177e4 LT |
377 | pci_enable_device(dev); |
378 | // | |
379 | // loop over all interfaces that are part of this pci device: | |
380 | // | |
381 | while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) { | |
382 | unsigned int basereg, r, d, format; | |
383 | sc1200_saved_state_t *ss = (sc1200_saved_state_t *)hwif->config_data; | |
1da177e4 LT |
384 | |
385 | // | |
386 | // Restore timing registers: this may be unnecessary if BIOS also does it | |
387 | // | |
388 | basereg = hwif->channel ? 0x50 : 0x40; | |
389 | if (ss != NULL) { | |
390 | for (r = 0; r < 4; ++r) { | |
391 | pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]); | |
392 | } | |
393 | } | |
394 | // | |
395 | // Re-program drive PIO modes | |
396 | // | |
397 | pci_read_config_dword(hwif->pci_dev, basereg+4, &format); | |
398 | format = (format >> 31) & 1; | |
399 | if (format) | |
400 | format += sc1200_get_pci_clock(); | |
401 | for (d = 0; d < 2; ++d) { | |
402 | ide_drive_t *drive = &(hwif->drives[d]); | |
403 | if (drive->present) { | |
404 | unsigned int pio, timings; | |
405 | pci_read_config_dword(hwif->pci_dev, basereg+(drive->select.b.unit << 3), &timings); | |
406 | for (pio = 0; pio <= 4; ++pio) { | |
407 | if (sc1200_pio_timings[format][pio] == timings) | |
408 | break; | |
409 | } | |
410 | if (pio > 4) | |
411 | pio = 255; /* autotune */ | |
412 | (void)sc1200_tuneproc(drive, pio); | |
413 | } | |
414 | } | |
415 | // | |
416 | // Re-program drive DMA modes | |
417 | // | |
418 | for (d = 0; d < MAX_DRIVES; ++d) { | |
419 | ide_drive_t *drive = &(hwif->drives[d]); | |
420 | if (drive->present && !__ide_dma_bad_drive(drive)) { | |
a01ba401 | 421 | int enable_dma = drive->using_dma; |
7469aaf6 | 422 | hwif->dma_off_quietly(drive); |
a01ba401 BZ |
423 | if (sc1200_config_dma(drive)) |
424 | enable_dma = 0; | |
425 | if (enable_dma) | |
426 | hwif->dma_host_on(drive); | |
1da177e4 LT |
427 | } |
428 | } | |
429 | } | |
430 | return 0; | |
431 | } | |
b86cc29d | 432 | #endif |
1da177e4 LT |
433 | |
434 | /* | |
435 | * This gets invoked by the IDE driver once for each channel, | |
436 | * and performs channel-specific pre-initialization before drive probing. | |
437 | */ | |
6a6e1b1c | 438 | static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif) |
1da177e4 LT |
439 | { |
440 | if (hwif->mate) | |
441 | hwif->serialized = hwif->mate->serialized = 1; | |
442 | hwif->autodma = 0; | |
443 | if (hwif->dma_base) { | |
5fd216bb | 444 | hwif->udma_filter = sc1200_udma_filter; |
1da177e4 LT |
445 | hwif->ide_dma_check = &sc1200_config_dma; |
446 | hwif->ide_dma_end = &sc1200_ide_dma_end; | |
447 | if (!noautodma) | |
448 | hwif->autodma = 1; | |
449 | hwif->tuneproc = &sc1200_tuneproc; | |
450 | } | |
451 | hwif->atapi_dma = 1; | |
452 | hwif->ultra_mask = 0x07; | |
453 | hwif->mwdma_mask = 0x07; | |
454 | ||
455 | hwif->drives[0].autodma = hwif->autodma; | |
456 | hwif->drives[1].autodma = hwif->autodma; | |
457 | } | |
458 | ||
459 | static ide_pci_device_t sc1200_chipset __devinitdata = { | |
460 | .name = "SC1200", | |
461 | .init_hwif = init_hwif_sc1200, | |
462 | .channels = 2, | |
463 | .autodma = AUTODMA, | |
464 | .bootable = ON_BOARD, | |
465 | }; | |
466 | ||
467 | static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
468 | { | |
469 | return ide_setup_pci_device(dev, &sc1200_chipset); | |
470 | } | |
471 | ||
472 | static struct pci_device_id sc1200_pci_tbl[] = { | |
2930d1be | 473 | { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0}, |
1da177e4 LT |
474 | { 0, }, |
475 | }; | |
476 | MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl); | |
477 | ||
478 | static struct pci_driver driver = { | |
479 | .name = "SC1200_IDE", | |
480 | .id_table = sc1200_pci_tbl, | |
481 | .probe = sc1200_init_one, | |
b86cc29d | 482 | #ifdef CONFIG_PM |
1da177e4 LT |
483 | .suspend = sc1200_suspend, |
484 | .resume = sc1200_resume, | |
b86cc29d | 485 | #endif |
1da177e4 LT |
486 | }; |
487 | ||
82ab1eec | 488 | static int __init sc1200_ide_init(void) |
1da177e4 LT |
489 | { |
490 | return ide_pci_register_driver(&driver); | |
491 | } | |
492 | ||
493 | module_init(sc1200_ide_init); | |
494 | ||
495 | MODULE_AUTHOR("Mark Lord"); | |
496 | MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE"); | |
497 | MODULE_LICENSE("GPL"); |