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1da177e4 | 1 | /* |
31c4df44 | 2 | * linux/drivers/ide/pci/sc1200.c Version 0.95 Jun 16 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com> | |
5fd216bb BZ |
5 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
6 | * | |
1da177e4 LT |
7 | * May be copied or modified under the terms of the GNU General Public License |
8 | * | |
9 | * Development of this chipset driver was funded | |
10 | * by the nice folks at National Semiconductor. | |
11 | * | |
12 | * Documentation: | |
13 | * Available from National Semiconductor | |
14 | */ | |
15 | ||
1da177e4 LT |
16 | #include <linux/module.h> |
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/timer.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/hdreg.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/ide.h> | |
29 | #include <linux/pm.h> | |
30 | #include <asm/io.h> | |
31 | #include <asm/irq.h> | |
32 | ||
33 | #define SC1200_REV_A 0x00 | |
34 | #define SC1200_REV_B1 0x01 | |
35 | #define SC1200_REV_B3 0x02 | |
36 | #define SC1200_REV_C1 0x03 | |
37 | #define SC1200_REV_D1 0x04 | |
38 | ||
39 | #define PCI_CLK_33 0x00 | |
40 | #define PCI_CLK_48 0x01 | |
41 | #define PCI_CLK_66 0x02 | |
42 | #define PCI_CLK_33A 0x03 | |
43 | ||
44 | static unsigned short sc1200_get_pci_clock (void) | |
45 | { | |
46 | unsigned char chip_id, silicon_revision; | |
47 | unsigned int pci_clock; | |
48 | /* | |
49 | * Check the silicon revision, as not all versions of the chip | |
50 | * have the register with the fast PCI bus timings. | |
51 | */ | |
52 | chip_id = inb (0x903c); | |
53 | silicon_revision = inb (0x903d); | |
54 | ||
55 | // Read the fast pci clock frequency | |
56 | if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) { | |
57 | pci_clock = PCI_CLK_33; | |
58 | } else { | |
59 | // check clock generator configuration (cfcc) | |
60 | // the clock is in bits 8 and 9 of this word | |
61 | ||
62 | pci_clock = inw (0x901e); | |
63 | pci_clock >>= 8; | |
64 | pci_clock &= 0x03; | |
65 | if (pci_clock == PCI_CLK_33A) | |
66 | pci_clock = PCI_CLK_33; | |
67 | } | |
68 | return pci_clock; | |
69 | } | |
70 | ||
71 | extern char *ide_xfer_verbose (byte xfer_rate); | |
72 | ||
73 | /* | |
74 | * Set a new transfer mode at the drive | |
75 | */ | |
76 | static int sc1200_set_xfer_mode (ide_drive_t *drive, byte mode) | |
77 | { | |
78 | printk("%s: sc1200_set_xfer_mode(%s)\n", drive->name, ide_xfer_verbose(mode)); | |
79 | return ide_config_drive_speed(drive, mode); | |
80 | } | |
81 | ||
82 | /* | |
83 | * Here are the standard PIO mode 0-4 timings for each "format". | |
84 | * Format-0 uses fast data reg timings, with slower command reg timings. | |
85 | * Format-1 uses fast timings for all registers, but won't work with all drives. | |
86 | */ | |
87 | static const unsigned int sc1200_pio_timings[4][5] = | |
88 | {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz | |
89 | {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz | |
90 | {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz | |
91 | {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz | |
92 | ||
93 | /* | |
94 | * After chip reset, the PIO timings are set to 0x00009172, which is not valid. | |
95 | */ | |
96 | //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172) | |
97 | ||
3c3f5d2c BZ |
98 | static void sc1200_tunepio(ide_drive_t *drive, u8 pio) |
99 | { | |
100 | ide_hwif_t *hwif = drive->hwif; | |
101 | struct pci_dev *pdev = hwif->pci_dev; | |
102 | unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0; | |
103 | ||
104 | pci_read_config_dword(pdev, basereg + 4, &format); | |
105 | format = (format >> 31) & 1; | |
106 | if (format) | |
107 | format += sc1200_get_pci_clock(); | |
108 | pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3), | |
109 | sc1200_pio_timings[format][pio]); | |
110 | } | |
111 | ||
5fd216bb BZ |
112 | /* |
113 | * The SC1200 specifies that two drives sharing a cable cannot mix | |
114 | * UDMA/MDMA. It has to be one or the other, for the pair, though | |
115 | * different timings can still be chosen for each drive. We could | |
116 | * set the appropriate timing bits on the fly, but that might be | |
117 | * a bit confusing. So, for now we statically handle this requirement | |
118 | * by looking at our mate drive to see what it is capable of, before | |
119 | * choosing a mode for our own drive. | |
120 | */ | |
121 | static u8 sc1200_udma_filter(ide_drive_t *drive) | |
1da177e4 | 122 | { |
5fd216bb BZ |
123 | ide_hwif_t *hwif = drive->hwif; |
124 | ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1]; | |
125 | struct hd_driveid *mateid = mate->id; | |
126 | u8 mask = hwif->ultra_mask; | |
127 | ||
128 | if (mate->present == 0) | |
129 | goto out; | |
130 | ||
131 | if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) { | |
132 | if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7)) | |
133 | goto out; | |
134 | if ((mateid->field_valid & 2) && (mateid->dma_mword & 7)) | |
135 | mask = 0; | |
1da177e4 | 136 | } |
5fd216bb BZ |
137 | out: |
138 | return mask; | |
1da177e4 LT |
139 | } |
140 | ||
f212ff28 | 141 | static int sc1200_tune_chipset(ide_drive_t *drive, const u8 mode) |
1da177e4 LT |
142 | { |
143 | ide_hwif_t *hwif = HWIF(drive); | |
144 | int unit = drive->select.b.unit; | |
145 | unsigned int reg, timings; | |
146 | unsigned short pci_clock; | |
147 | unsigned int basereg = hwif->channel ? 0x50 : 0x40; | |
148 | ||
1da177e4 LT |
149 | /* |
150 | * Tell the drive to switch to the new mode; abort on failure. | |
151 | */ | |
fabe1510 | 152 | if (sc1200_set_xfer_mode(drive, mode)) |
1da177e4 | 153 | return 1; /* failure */ |
1da177e4 | 154 | |
3c3f5d2c BZ |
155 | switch (mode) { |
156 | case XFER_PIO_4: | |
157 | case XFER_PIO_3: | |
158 | case XFER_PIO_2: | |
159 | case XFER_PIO_1: | |
160 | case XFER_PIO_0: | |
161 | sc1200_tunepio(drive, mode - XFER_PIO_0); | |
162 | return 0; | |
163 | } | |
164 | ||
1da177e4 LT |
165 | pci_clock = sc1200_get_pci_clock(); |
166 | ||
167 | /* | |
168 | * Now tune the chipset to match the drive: | |
169 | * | |
170 | * Note that each DMA mode has several timings associated with it. | |
171 | * The correct timing depends on the fast PCI clock freq. | |
172 | */ | |
173 | timings = 0; | |
174 | switch (mode) { | |
175 | case XFER_UDMA_0: | |
176 | switch (pci_clock) { | |
177 | case PCI_CLK_33: timings = 0x00921250; break; | |
178 | case PCI_CLK_48: timings = 0x00932470; break; | |
179 | case PCI_CLK_66: timings = 0x009436a1; break; | |
180 | } | |
181 | break; | |
182 | case XFER_UDMA_1: | |
183 | switch (pci_clock) { | |
184 | case PCI_CLK_33: timings = 0x00911140; break; | |
185 | case PCI_CLK_48: timings = 0x00922260; break; | |
186 | case PCI_CLK_66: timings = 0x00933481; break; | |
187 | } | |
188 | break; | |
189 | case XFER_UDMA_2: | |
190 | switch (pci_clock) { | |
191 | case PCI_CLK_33: timings = 0x00911030; break; | |
192 | case PCI_CLK_48: timings = 0x00922140; break; | |
193 | case PCI_CLK_66: timings = 0x00923261; break; | |
194 | } | |
195 | break; | |
196 | case XFER_MW_DMA_0: | |
197 | switch (pci_clock) { | |
198 | case PCI_CLK_33: timings = 0x00077771; break; | |
199 | case PCI_CLK_48: timings = 0x000bbbb2; break; | |
200 | case PCI_CLK_66: timings = 0x000ffff3; break; | |
201 | } | |
202 | break; | |
203 | case XFER_MW_DMA_1: | |
204 | switch (pci_clock) { | |
205 | case PCI_CLK_33: timings = 0x00012121; break; | |
206 | case PCI_CLK_48: timings = 0x00024241; break; | |
207 | case PCI_CLK_66: timings = 0x00035352; break; | |
208 | } | |
209 | break; | |
210 | case XFER_MW_DMA_2: | |
211 | switch (pci_clock) { | |
212 | case PCI_CLK_33: timings = 0x00002020; break; | |
213 | case PCI_CLK_48: timings = 0x00013131; break; | |
214 | case PCI_CLK_66: timings = 0x00015151; break; | |
215 | } | |
216 | break; | |
3c3f5d2c BZ |
217 | default: |
218 | BUG(); | |
219 | break; | |
1da177e4 LT |
220 | } |
221 | ||
222 | if (unit == 0) { /* are we configuring drive0? */ | |
223 | pci_read_config_dword(hwif->pci_dev, basereg+4, ®); | |
224 | timings |= reg & 0x80000000; /* preserve PIO format bit */ | |
225 | pci_write_config_dword(hwif->pci_dev, basereg+4, timings); | |
226 | } else { | |
227 | pci_write_config_dword(hwif->pci_dev, basereg+12, timings); | |
228 | } | |
229 | ||
3608b5d7 | 230 | return 0; /* success */ |
1da177e4 LT |
231 | } |
232 | ||
233 | /* | |
234 | * sc1200_config_dma() handles selection/setting of DMA/UDMA modes | |
235 | * for both the chipset and drive. | |
236 | */ | |
237 | static int sc1200_config_dma (ide_drive_t *drive) | |
238 | { | |
4728d546 BZ |
239 | if (ide_tune_dma(drive)) |
240 | return 0; | |
5fd216bb | 241 | |
3c3f5d2c | 242 | return 1; |
1da177e4 LT |
243 | } |
244 | ||
245 | ||
246 | /* Replacement for the standard ide_dma_end action in | |
247 | * dma_proc. | |
248 | * | |
249 | * returns 1 on error, 0 otherwise | |
250 | */ | |
251 | static int sc1200_ide_dma_end (ide_drive_t *drive) | |
252 | { | |
253 | ide_hwif_t *hwif = HWIF(drive); | |
254 | unsigned long dma_base = hwif->dma_base; | |
255 | byte dma_stat; | |
256 | ||
257 | dma_stat = inb(dma_base+2); /* get DMA status */ | |
258 | ||
259 | if (!(dma_stat & 4)) | |
260 | printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n", | |
261 | dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2)); | |
262 | ||
263 | outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */ | |
264 | outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */ | |
265 | ||
266 | drive->waiting_for_dma = 0; | |
267 | ide_destroy_dmatable(drive); /* purge DMA mappings */ | |
268 | ||
269 | return (dma_stat & 7) != 4; /* verify good DMA status */ | |
270 | } | |
271 | ||
272 | /* | |
26bcb879 | 273 | * sc1200_set_pio_mode() handles setting of PIO modes |
1da177e4 LT |
274 | * for both the chipset and drive. |
275 | * | |
276 | * All existing BIOSs for this chipset guarantee that all drives | |
277 | * will have valid default PIO timings set up before we get here. | |
278 | */ | |
26bcb879 BZ |
279 | |
280 | static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio) | |
1da177e4 LT |
281 | { |
282 | ide_hwif_t *hwif = HWIF(drive); | |
1da177e4 LT |
283 | int mode = -1; |
284 | ||
a01ba401 | 285 | /* |
26bcb879 | 286 | * bad abuse of ->set_pio_mode interface |
a01ba401 | 287 | */ |
1da177e4 LT |
288 | switch (pio) { |
289 | case 200: mode = XFER_UDMA_0; break; | |
290 | case 201: mode = XFER_UDMA_1; break; | |
291 | case 202: mode = XFER_UDMA_2; break; | |
292 | case 100: mode = XFER_MW_DMA_0; break; | |
293 | case 101: mode = XFER_MW_DMA_1; break; | |
294 | case 102: mode = XFER_MW_DMA_2; break; | |
295 | } | |
296 | if (mode != -1) { | |
297 | printk("SC1200: %s: changing (U)DMA mode\n", drive->name); | |
a01ba401 | 298 | hwif->dma_off_quietly(drive); |
3c3f5d2c | 299 | if (sc1200_tune_chipset(drive, mode) == 0) |
a01ba401 | 300 | hwif->dma_host_on(drive); |
1da177e4 LT |
301 | return; |
302 | } | |
303 | ||
3c3f5d2c BZ |
304 | if (sc1200_set_xfer_mode(drive, XFER_PIO_0 + pio) == 0) |
305 | sc1200_tunepio(drive, pio); | |
1da177e4 LT |
306 | } |
307 | ||
b86cc29d | 308 | #ifdef CONFIG_PM |
1da177e4 LT |
309 | static ide_hwif_t *lookup_pci_dev (ide_hwif_t *prev, struct pci_dev *dev) |
310 | { | |
311 | int h; | |
312 | ||
313 | for (h = 0; h < MAX_HWIFS; h++) { | |
314 | ide_hwif_t *hwif = &ide_hwifs[h]; | |
315 | if (prev) { | |
316 | if (hwif == prev) | |
317 | prev = NULL; // found previous, now look for next match | |
318 | } else { | |
319 | if (hwif && hwif->pci_dev == dev) | |
320 | return hwif; // found next match | |
321 | } | |
322 | } | |
323 | return NULL; // not found | |
324 | } | |
325 | ||
326 | typedef struct sc1200_saved_state_s { | |
327 | __u32 regs[4]; | |
328 | } sc1200_saved_state_t; | |
329 | ||
330 | ||
3bfffd97 | 331 | static int sc1200_suspend (struct pci_dev *dev, pm_message_t state) |
1da177e4 LT |
332 | { |
333 | ide_hwif_t *hwif = NULL; | |
334 | ||
ca078bae | 335 | printk("SC1200: suspend(%u)\n", state.event); |
1da177e4 | 336 | |
ca078bae | 337 | if (state.event == PM_EVENT_ON) { |
1da177e4 LT |
338 | // we only save state when going from full power to less |
339 | ||
340 | // | |
341 | // Loop over all interfaces that are part of this PCI device: | |
342 | // | |
343 | while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) { | |
344 | sc1200_saved_state_t *ss; | |
345 | unsigned int basereg, r; | |
346 | // | |
347 | // allocate a permanent save area, if not already allocated | |
348 | // | |
349 | ss = (sc1200_saved_state_t *)hwif->config_data; | |
350 | if (ss == NULL) { | |
351 | ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL); | |
352 | if (ss == NULL) | |
353 | return -ENOMEM; | |
354 | hwif->config_data = (unsigned long)ss; | |
355 | } | |
356 | ss = (sc1200_saved_state_t *)hwif->config_data; | |
357 | // | |
358 | // Save timing registers: this may be unnecessary if | |
359 | // BIOS also does it | |
360 | // | |
361 | basereg = hwif->channel ? 0x50 : 0x40; | |
362 | for (r = 0; r < 4; ++r) { | |
363 | pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]); | |
364 | } | |
365 | } | |
366 | } | |
367 | ||
368 | /* You don't need to iterate over disks -- sysfs should have done that for you already */ | |
369 | ||
370 | pci_disable_device(dev); | |
ca078bae PM |
371 | pci_set_power_state(dev, pci_choose_state(dev, state)); |
372 | dev->current_state = state.event; | |
1da177e4 LT |
373 | return 0; |
374 | } | |
375 | ||
376 | static int sc1200_resume (struct pci_dev *dev) | |
377 | { | |
378 | ide_hwif_t *hwif = NULL; | |
379 | ||
ca078bae PM |
380 | pci_set_power_state(dev, PCI_D0); // bring chip back from sleep state |
381 | dev->current_state = PM_EVENT_ON; | |
1da177e4 LT |
382 | pci_enable_device(dev); |
383 | // | |
384 | // loop over all interfaces that are part of this pci device: | |
385 | // | |
386 | while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) { | |
31c4df44 | 387 | unsigned int basereg, r; |
1da177e4 | 388 | sc1200_saved_state_t *ss = (sc1200_saved_state_t *)hwif->config_data; |
1da177e4 LT |
389 | |
390 | // | |
391 | // Restore timing registers: this may be unnecessary if BIOS also does it | |
392 | // | |
393 | basereg = hwif->channel ? 0x50 : 0x40; | |
394 | if (ss != NULL) { | |
395 | for (r = 0; r < 4; ++r) { | |
396 | pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]); | |
397 | } | |
398 | } | |
1da177e4 LT |
399 | } |
400 | return 0; | |
401 | } | |
b86cc29d | 402 | #endif |
1da177e4 LT |
403 | |
404 | /* | |
405 | * This gets invoked by the IDE driver once for each channel, | |
406 | * and performs channel-specific pre-initialization before drive probing. | |
407 | */ | |
6a6e1b1c | 408 | static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif) |
1da177e4 LT |
409 | { |
410 | if (hwif->mate) | |
411 | hwif->serialized = hwif->mate->serialized = 1; | |
412 | hwif->autodma = 0; | |
413 | if (hwif->dma_base) { | |
5fd216bb | 414 | hwif->udma_filter = sc1200_udma_filter; |
1da177e4 LT |
415 | hwif->ide_dma_check = &sc1200_config_dma; |
416 | hwif->ide_dma_end = &sc1200_ide_dma_end; | |
417 | if (!noautodma) | |
418 | hwif->autodma = 1; | |
26bcb879 BZ |
419 | |
420 | hwif->set_pio_mode = &sc1200_set_pio_mode; | |
3c3f5d2c | 421 | hwif->speedproc = &sc1200_tune_chipset; |
1da177e4 LT |
422 | } |
423 | hwif->atapi_dma = 1; | |
424 | hwif->ultra_mask = 0x07; | |
425 | hwif->mwdma_mask = 0x07; | |
426 | ||
427 | hwif->drives[0].autodma = hwif->autodma; | |
428 | hwif->drives[1].autodma = hwif->autodma; | |
429 | } | |
430 | ||
431 | static ide_pci_device_t sc1200_chipset __devinitdata = { | |
432 | .name = "SC1200", | |
433 | .init_hwif = init_hwif_sc1200, | |
1da177e4 LT |
434 | .autodma = AUTODMA, |
435 | .bootable = ON_BOARD, | |
26bcb879 | 436 | .host_flags = IDE_HFLAG_ABUSE_DMA_MODES, |
4099d143 | 437 | .pio_mask = ATA_PIO4, |
1da177e4 LT |
438 | }; |
439 | ||
440 | static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
441 | { | |
442 | return ide_setup_pci_device(dev, &sc1200_chipset); | |
443 | } | |
444 | ||
445 | static struct pci_device_id sc1200_pci_tbl[] = { | |
2930d1be | 446 | { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0}, |
1da177e4 LT |
447 | { 0, }, |
448 | }; | |
449 | MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl); | |
450 | ||
451 | static struct pci_driver driver = { | |
452 | .name = "SC1200_IDE", | |
453 | .id_table = sc1200_pci_tbl, | |
454 | .probe = sc1200_init_one, | |
b86cc29d | 455 | #ifdef CONFIG_PM |
1da177e4 LT |
456 | .suspend = sc1200_suspend, |
457 | .resume = sc1200_resume, | |
b86cc29d | 458 | #endif |
1da177e4 LT |
459 | }; |
460 | ||
82ab1eec | 461 | static int __init sc1200_ide_init(void) |
1da177e4 LT |
462 | { |
463 | return ide_pci_register_driver(&driver); | |
464 | } | |
465 | ||
466 | module_init(sc1200_ide_init); | |
467 | ||
468 | MODULE_AUTHOR("Mark Lord"); | |
469 | MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE"); | |
470 | MODULE_LICENSE("GPL"); |