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Commit | Line | Data |
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bde18a2e KI |
1 | /* |
2 | * Support for IDE interfaces on Celleb platform | |
3 | * | |
4 | * (C) Copyright 2006 TOSHIBA CORPORATION | |
5 | * | |
6 | * This code is based on drivers/ide/pci/siimage.c: | |
7 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> | |
8 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along | |
21 | * with this program; if not, write to the Free Software Foundation, Inc., | |
22 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
23 | */ | |
24 | ||
25 | #include <linux/types.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/hdreg.h> | |
30 | #include <linux/ide.h> | |
31 | #include <linux/init.h> | |
32 | ||
33 | #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4 | |
34 | ||
35 | #define SCC_PATA_NAME "scc IDE" | |
36 | ||
37 | #define TDVHSEL_MASTER 0x00000001 | |
38 | #define TDVHSEL_SLAVE 0x00000004 | |
39 | ||
40 | #define MODE_JCUSFEN 0x00000080 | |
41 | ||
42 | #define CCKCTRL_ATARESET 0x00040000 | |
43 | #define CCKCTRL_BUFCNT 0x00020000 | |
44 | #define CCKCTRL_CRST 0x00010000 | |
45 | #define CCKCTRL_OCLKEN 0x00000100 | |
46 | #define CCKCTRL_ATACLKOEN 0x00000002 | |
47 | #define CCKCTRL_LCLKEN 0x00000001 | |
48 | ||
49 | #define QCHCD_IOS_SS 0x00000001 | |
50 | ||
51 | #define QCHSD_STPDIAG 0x00020000 | |
52 | ||
53 | #define INTMASK_MSK 0xD1000012 | |
54 | #define INTSTS_SERROR 0x80000000 | |
55 | #define INTSTS_PRERR 0x40000000 | |
56 | #define INTSTS_RERR 0x10000000 | |
57 | #define INTSTS_ICERR 0x01000000 | |
58 | #define INTSTS_BMSINT 0x00000010 | |
59 | #define INTSTS_BMHE 0x00000008 | |
60 | #define INTSTS_IOIRQS 0x00000004 | |
61 | #define INTSTS_INTRQ 0x00000002 | |
62 | #define INTSTS_ACTEINT 0x00000001 | |
63 | ||
64 | #define ECMODE_VALUE 0x01 | |
65 | ||
66 | static struct scc_ports { | |
67 | unsigned long ctl, dma; | |
68 | unsigned char hwif_id; /* for removing hwif from system */ | |
69 | } scc_ports[MAX_HWIFS]; | |
70 | ||
71 | /* PIO transfer mode table */ | |
72 | /* JCHST */ | |
73 | static unsigned long JCHSTtbl[2][7] = { | |
74 | {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */ | |
75 | {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */ | |
76 | }; | |
77 | ||
78 | /* JCHHT */ | |
79 | static unsigned long JCHHTtbl[2][7] = { | |
80 | {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */ | |
81 | {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */ | |
82 | }; | |
83 | ||
84 | /* JCHCT */ | |
85 | static unsigned long JCHCTtbl[2][7] = { | |
86 | {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */ | |
87 | {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */ | |
88 | }; | |
89 | ||
90 | ||
91 | /* DMA transfer mode table */ | |
92 | /* JCHDCTM/JCHDCTS */ | |
93 | static unsigned long JCHDCTxtbl[2][7] = { | |
94 | {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */ | |
95 | {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */ | |
96 | }; | |
97 | ||
98 | /* JCSTWTM/JCSTWTS */ | |
99 | static unsigned long JCSTWTxtbl[2][7] = { | |
100 | {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */ | |
101 | {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ | |
102 | }; | |
103 | ||
104 | /* JCTSS */ | |
105 | static unsigned long JCTSStbl[2][7] = { | |
106 | {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */ | |
107 | {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */ | |
108 | }; | |
109 | ||
110 | /* JCENVT */ | |
111 | static unsigned long JCENVTtbl[2][7] = { | |
112 | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */ | |
113 | {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ | |
114 | }; | |
115 | ||
116 | /* JCACTSELS/JCACTSELM */ | |
117 | static unsigned long JCACTSELtbl[2][7] = { | |
118 | {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */ | |
119 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */ | |
120 | }; | |
121 | ||
122 | ||
123 | static u8 scc_ide_inb(unsigned long port) | |
124 | { | |
125 | u32 data = in_be32((void*)port); | |
126 | return (u8)data; | |
127 | } | |
128 | ||
129 | static u16 scc_ide_inw(unsigned long port) | |
130 | { | |
131 | u32 data = in_be32((void*)port); | |
132 | return (u16)data; | |
133 | } | |
134 | ||
bde18a2e KI |
135 | static void scc_ide_insw(unsigned long port, void *addr, u32 count) |
136 | { | |
137 | u16 *ptr = (u16 *)addr; | |
138 | while (count--) { | |
139 | *ptr++ = le16_to_cpu(in_be32((void*)port)); | |
140 | } | |
141 | } | |
142 | ||
143 | static void scc_ide_insl(unsigned long port, void *addr, u32 count) | |
144 | { | |
145 | u16 *ptr = (u16 *)addr; | |
146 | while (count--) { | |
147 | *ptr++ = le16_to_cpu(in_be32((void*)port)); | |
148 | *ptr++ = le16_to_cpu(in_be32((void*)port)); | |
149 | } | |
150 | } | |
151 | ||
152 | static void scc_ide_outb(u8 addr, unsigned long port) | |
153 | { | |
154 | out_be32((void*)port, addr); | |
155 | } | |
156 | ||
157 | static void scc_ide_outw(u16 addr, unsigned long port) | |
158 | { | |
159 | out_be32((void*)port, addr); | |
160 | } | |
161 | ||
bde18a2e KI |
162 | static void |
163 | scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port) | |
164 | { | |
165 | ide_hwif_t *hwif = HWIF(drive); | |
166 | ||
167 | out_be32((void*)port, addr); | |
f644d47a | 168 | eieio(); |
bde18a2e | 169 | in_be32((void*)(hwif->dma_base + 0x01c)); |
f644d47a | 170 | eieio(); |
bde18a2e KI |
171 | } |
172 | ||
173 | static void | |
174 | scc_ide_outsw(unsigned long port, void *addr, u32 count) | |
175 | { | |
176 | u16 *ptr = (u16 *)addr; | |
177 | while (count--) { | |
178 | out_be32((void*)port, cpu_to_le16(*ptr++)); | |
179 | } | |
180 | } | |
181 | ||
182 | static void | |
183 | scc_ide_outsl(unsigned long port, void *addr, u32 count) | |
184 | { | |
185 | u16 *ptr = (u16 *)addr; | |
186 | while (count--) { | |
187 | out_be32((void*)port, cpu_to_le16(*ptr++)); | |
188 | out_be32((void*)port, cpu_to_le16(*ptr++)); | |
189 | } | |
190 | } | |
191 | ||
bde18a2e | 192 | /** |
3fcece66 | 193 | * scc_tune_pio - tune a drive PIO mode |
bde18a2e KI |
194 | * @drive: drive to tune |
195 | * @mode_wanted: the target operating mode | |
196 | * | |
197 | * Load the timing settings for this device mode into the | |
198 | * controller. | |
199 | */ | |
200 | ||
3fcece66 | 201 | static void scc_tune_pio(ide_drive_t *drive, const u8 pio) |
bde18a2e KI |
202 | { |
203 | ide_hwif_t *hwif = HWIF(drive); | |
204 | struct scc_ports *ports = ide_get_hwifdata(hwif); | |
205 | unsigned long ctl_base = ports->ctl; | |
206 | unsigned long cckctrl_port = ctl_base + 0xff0; | |
207 | unsigned long piosht_port = ctl_base + 0x000; | |
208 | unsigned long pioct_port = ctl_base + 0x004; | |
209 | unsigned long reg; | |
bde18a2e KI |
210 | int offset; |
211 | ||
0ecdca26 | 212 | reg = in_be32((void __iomem *)cckctrl_port); |
bde18a2e KI |
213 | if (reg & CCKCTRL_ATACLKOEN) { |
214 | offset = 1; /* 133MHz */ | |
215 | } else { | |
216 | offset = 0; /* 100MHz */ | |
217 | } | |
3fcece66 | 218 | reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio]; |
0ecdca26 | 219 | out_be32((void __iomem *)piosht_port, reg); |
3fcece66 | 220 | reg = JCHCTtbl[offset][pio]; |
0ecdca26 | 221 | out_be32((void __iomem *)pioct_port, reg); |
3fcece66 | 222 | } |
bde18a2e | 223 | |
26bcb879 | 224 | static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio) |
3fcece66 | 225 | { |
3fcece66 BZ |
226 | scc_tune_pio(drive, pio); |
227 | ide_config_drive_speed(drive, XFER_PIO_0 + pio); | |
bde18a2e KI |
228 | } |
229 | ||
230 | /** | |
231 | * scc_tune_chipset - tune a drive DMA mode | |
232 | * @drive: Drive to set up | |
f212ff28 | 233 | * @speed: speed we want to achieve |
bde18a2e KI |
234 | * |
235 | * Load the timing settings for this device mode into the | |
236 | * controller. | |
237 | */ | |
238 | ||
f212ff28 | 239 | static int scc_tune_chipset(ide_drive_t *drive, const u8 speed) |
bde18a2e KI |
240 | { |
241 | ide_hwif_t *hwif = HWIF(drive); | |
bde18a2e KI |
242 | struct scc_ports *ports = ide_get_hwifdata(hwif); |
243 | unsigned long ctl_base = ports->ctl; | |
244 | unsigned long cckctrl_port = ctl_base + 0xff0; | |
245 | unsigned long mdmact_port = ctl_base + 0x008; | |
246 | unsigned long mcrcst_port = ctl_base + 0x00c; | |
247 | unsigned long sdmact_port = ctl_base + 0x010; | |
248 | unsigned long scrcst_port = ctl_base + 0x014; | |
249 | unsigned long udenvt_port = ctl_base + 0x018; | |
250 | unsigned long tdvhsel_port = ctl_base + 0x020; | |
251 | int is_slave = (&hwif->drives[1] == drive); | |
252 | int offset, idx; | |
253 | unsigned long reg; | |
254 | unsigned long jcactsel; | |
255 | ||
0ecdca26 | 256 | reg = in_be32((void __iomem *)cckctrl_port); |
bde18a2e KI |
257 | if (reg & CCKCTRL_ATACLKOEN) { |
258 | offset = 1; /* 133MHz */ | |
259 | } else { | |
260 | offset = 0; /* 100MHz */ | |
261 | } | |
262 | ||
263 | switch (speed) { | |
264 | case XFER_UDMA_6: | |
bde18a2e | 265 | case XFER_UDMA_5: |
bde18a2e | 266 | case XFER_UDMA_4: |
bde18a2e | 267 | case XFER_UDMA_3: |
bde18a2e | 268 | case XFER_UDMA_2: |
bde18a2e | 269 | case XFER_UDMA_1: |
bde18a2e | 270 | case XFER_UDMA_0: |
3fcece66 | 271 | idx = speed - XFER_UDMA_0; |
bde18a2e | 272 | break; |
3fcece66 BZ |
273 | case XFER_PIO_4: |
274 | case XFER_PIO_3: | |
275 | case XFER_PIO_2: | |
276 | case XFER_PIO_1: | |
277 | case XFER_PIO_0: | |
278 | scc_tune_pio(drive, speed - XFER_PIO_0); | |
279 | return ide_config_drive_speed(drive, speed); | |
bde18a2e KI |
280 | default: |
281 | return 1; | |
282 | } | |
283 | ||
284 | jcactsel = JCACTSELtbl[offset][idx]; | |
285 | if (is_slave) { | |
0ecdca26 BZ |
286 | out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]); |
287 | out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]); | |
288 | jcactsel = jcactsel << 2; | |
289 | out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel); | |
bde18a2e | 290 | } else { |
0ecdca26 BZ |
291 | out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]); |
292 | out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]); | |
293 | out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel); | |
bde18a2e KI |
294 | } |
295 | reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]; | |
0ecdca26 | 296 | out_be32((void __iomem *)udenvt_port, reg); |
bde18a2e KI |
297 | |
298 | return ide_config_drive_speed(drive, speed); | |
299 | } | |
300 | ||
bde18a2e KI |
301 | /** |
302 | * scc_configure_drive_for_dma - set up for DMA transfers | |
303 | * @drive: drive we are going to set up | |
304 | * | |
305 | * Set up the drive for DMA, tune the controller and drive as | |
306 | * required. | |
307 | * If the drive isn't suitable for DMA or we hit other problems | |
308 | * then we will drop down to PIO and set up PIO appropriately. | |
3fcece66 | 309 | * (return -1) |
bde18a2e KI |
310 | */ |
311 | ||
312 | static int scc_config_drive_for_dma(ide_drive_t *drive) | |
313 | { | |
4728d546 | 314 | if (ide_tune_dma(drive)) |
3608b5d7 | 315 | return 0; |
7569e8dc | 316 | |
d8f4469d | 317 | if (ide_use_fast_pio(drive)) |
26bcb879 | 318 | ide_set_max_pio(drive); |
d8f4469d | 319 | |
3608b5d7 | 320 | return -1; |
bde18a2e KI |
321 | } |
322 | ||
0ecdca26 BZ |
323 | /** |
324 | * scc_ide_dma_setup - begin a DMA phase | |
325 | * @drive: target device | |
326 | * | |
327 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
328 | * and then set up the DMA transfer registers. | |
329 | * | |
330 | * Returns 0 on success. If a PIO fallback is required then 1 | |
331 | * is returned. | |
332 | */ | |
333 | ||
334 | static int scc_dma_setup(ide_drive_t *drive) | |
335 | { | |
336 | ide_hwif_t *hwif = drive->hwif; | |
337 | struct request *rq = HWGROUP(drive)->rq; | |
338 | unsigned int reading; | |
339 | u8 dma_stat; | |
340 | ||
341 | if (rq_data_dir(rq)) | |
342 | reading = 0; | |
343 | else | |
344 | reading = 1 << 3; | |
345 | ||
346 | /* fall back to pio! */ | |
347 | if (!ide_build_dmatable(drive, rq)) { | |
348 | ide_map_sg(drive, rq); | |
349 | return 1; | |
350 | } | |
351 | ||
352 | /* PRD table */ | |
353 | out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma); | |
354 | ||
355 | /* specify r/w */ | |
356 | out_be32((void __iomem *)hwif->dma_command, reading); | |
357 | ||
358 | /* read dma_status for INTR & ERROR flags */ | |
359 | dma_stat = in_be32((void __iomem *)hwif->dma_status); | |
360 | ||
361 | /* clear INTR & ERROR flags */ | |
362 | out_be32((void __iomem *)hwif->dma_status, dma_stat|6); | |
363 | drive->waiting_for_dma = 1; | |
364 | return 0; | |
365 | } | |
366 | ||
367 | ||
bde18a2e KI |
368 | /** |
369 | * scc_ide_dma_end - Stop DMA | |
370 | * @drive: IDE drive | |
371 | * | |
372 | * Check and clear INT Status register. | |
373 | * Then call __ide_dma_end(). | |
374 | */ | |
375 | ||
376 | static int scc_ide_dma_end(ide_drive_t * drive) | |
377 | { | |
378 | ide_hwif_t *hwif = HWIF(drive); | |
379 | unsigned long intsts_port = hwif->dma_base + 0x014; | |
380 | u32 reg; | |
4ae41ff8 KI |
381 | int dma_stat, data_loss = 0; |
382 | static int retry = 0; | |
383 | ||
384 | /* errata A308 workaround: Step5 (check data loss) */ | |
385 | /* We don't check non ide_disk because it is limited to UDMA4 */ | |
386 | if (!(in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) && | |
387 | drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) { | |
388 | reg = in_be32((void __iomem *)intsts_port); | |
389 | if (!(reg & INTSTS_ACTEINT)) { | |
390 | printk(KERN_WARNING "%s: operation failed (transfer data loss)\n", | |
391 | drive->name); | |
392 | data_loss = 1; | |
393 | if (retry++) { | |
394 | struct request *rq = HWGROUP(drive)->rq; | |
395 | int unit; | |
396 | /* ERROR_RESET and drive->crc_count are needed | |
397 | * to reduce DMA transfer mode in retry process. | |
398 | */ | |
399 | if (rq) | |
400 | rq->errors |= ERROR_RESET; | |
401 | for (unit = 0; unit < MAX_DRIVES; unit++) { | |
402 | ide_drive_t *drive = &hwif->drives[unit]; | |
403 | drive->crc_count++; | |
404 | } | |
405 | } | |
406 | } | |
407 | } | |
bde18a2e KI |
408 | |
409 | while (1) { | |
0ecdca26 | 410 | reg = in_be32((void __iomem *)intsts_port); |
bde18a2e KI |
411 | |
412 | if (reg & INTSTS_SERROR) { | |
413 | printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME); | |
0ecdca26 | 414 | out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT); |
bde18a2e | 415 | |
0ecdca26 | 416 | out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); |
bde18a2e KI |
417 | continue; |
418 | } | |
419 | ||
420 | if (reg & INTSTS_PRERR) { | |
421 | u32 maea0, maec0; | |
422 | unsigned long ctl_base = hwif->config_data; | |
423 | ||
0ecdca26 BZ |
424 | maea0 = in_be32((void __iomem *)(ctl_base + 0xF50)); |
425 | maec0 = in_be32((void __iomem *)(ctl_base + 0xF54)); | |
bde18a2e KI |
426 | |
427 | printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0); | |
428 | ||
0ecdca26 | 429 | out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT); |
bde18a2e | 430 | |
0ecdca26 | 431 | out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); |
bde18a2e KI |
432 | continue; |
433 | } | |
434 | ||
435 | if (reg & INTSTS_RERR) { | |
436 | printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME); | |
0ecdca26 | 437 | out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT); |
bde18a2e | 438 | |
0ecdca26 | 439 | out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); |
bde18a2e KI |
440 | continue; |
441 | } | |
442 | ||
443 | if (reg & INTSTS_ICERR) { | |
0ecdca26 | 444 | out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS); |
bde18a2e KI |
445 | |
446 | printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME); | |
0ecdca26 | 447 | out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT); |
bde18a2e KI |
448 | continue; |
449 | } | |
450 | ||
451 | if (reg & INTSTS_BMSINT) { | |
452 | printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME); | |
0ecdca26 | 453 | out_be32((void __iomem *)intsts_port, INTSTS_BMSINT); |
bde18a2e KI |
454 | |
455 | ide_do_reset(drive); | |
456 | continue; | |
457 | } | |
458 | ||
459 | if (reg & INTSTS_BMHE) { | |
0ecdca26 | 460 | out_be32((void __iomem *)intsts_port, INTSTS_BMHE); |
bde18a2e KI |
461 | continue; |
462 | } | |
463 | ||
464 | if (reg & INTSTS_ACTEINT) { | |
0ecdca26 | 465 | out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT); |
bde18a2e KI |
466 | continue; |
467 | } | |
468 | ||
469 | if (reg & INTSTS_IOIRQS) { | |
0ecdca26 | 470 | out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS); |
bde18a2e KI |
471 | continue; |
472 | } | |
473 | break; | |
474 | } | |
475 | ||
4ae41ff8 KI |
476 | dma_stat = __ide_dma_end(drive); |
477 | if (data_loss) | |
478 | dma_stat |= 2; /* emulate DMA error (to retry command) */ | |
479 | return dma_stat; | |
bde18a2e KI |
480 | } |
481 | ||
06a9952b AI |
482 | /* returns 1 if dma irq issued, 0 otherwise */ |
483 | static int scc_dma_test_irq(ide_drive_t *drive) | |
484 | { | |
4ae41ff8 KI |
485 | ide_hwif_t *hwif = HWIF(drive); |
486 | u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014); | |
06a9952b | 487 | |
4ae41ff8 KI |
488 | /* SCC errata A252,A308 workaround: Step4 */ |
489 | if ((in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) && | |
490 | (int_stat & INTSTS_INTRQ)) | |
06a9952b AI |
491 | return 1; |
492 | ||
4ae41ff8 KI |
493 | /* SCC errata A308 workaround: Step5 (polling IOIRQS) */ |
494 | if (int_stat & INTSTS_IOIRQS) | |
06a9952b AI |
495 | return 1; |
496 | ||
497 | if (!drive->waiting_for_dma) | |
498 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
499 | drive->name, __FUNCTION__); | |
500 | return 0; | |
501 | } | |
502 | ||
4ae41ff8 KI |
503 | static u8 scc_udma_filter(ide_drive_t *drive) |
504 | { | |
505 | ide_hwif_t *hwif = drive->hwif; | |
506 | u8 mask = hwif->ultra_mask; | |
507 | ||
508 | /* errata A308 workaround: limit non ide_disk drive to UDMA4 */ | |
509 | if ((drive->media != ide_disk) && (mask & 0xE0)) { | |
510 | printk(KERN_INFO "%s: limit %s to UDMA4\n", | |
511 | SCC_PATA_NAME, drive->name); | |
512 | mask = 0x1F; | |
513 | } | |
514 | ||
515 | return mask; | |
516 | } | |
517 | ||
bde18a2e KI |
518 | /** |
519 | * setup_mmio_scc - map CTRL/BMID region | |
520 | * @dev: PCI device we are configuring | |
521 | * @name: device name | |
522 | * | |
523 | */ | |
524 | ||
525 | static int setup_mmio_scc (struct pci_dev *dev, const char *name) | |
526 | { | |
527 | unsigned long ctl_base = pci_resource_start(dev, 0); | |
528 | unsigned long dma_base = pci_resource_start(dev, 1); | |
529 | unsigned long ctl_size = pci_resource_len(dev, 0); | |
530 | unsigned long dma_size = pci_resource_len(dev, 1); | |
0bd8496b AV |
531 | void __iomem *ctl_addr; |
532 | void __iomem *dma_addr; | |
bde18a2e KI |
533 | int i; |
534 | ||
535 | for (i = 0; i < MAX_HWIFS; i++) { | |
536 | if (scc_ports[i].ctl == 0) | |
537 | break; | |
538 | } | |
539 | if (i >= MAX_HWIFS) | |
540 | return -ENOMEM; | |
541 | ||
542 | if (!request_mem_region(ctl_base, ctl_size, name)) { | |
543 | printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME); | |
544 | goto fail_0; | |
545 | } | |
546 | ||
547 | if (!request_mem_region(dma_base, dma_size, name)) { | |
548 | printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME); | |
549 | goto fail_1; | |
550 | } | |
551 | ||
552 | if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL) | |
553 | goto fail_2; | |
554 | ||
555 | if ((dma_addr = ioremap(dma_base, dma_size)) == NULL) | |
556 | goto fail_3; | |
557 | ||
558 | pci_set_master(dev); | |
559 | scc_ports[i].ctl = (unsigned long)ctl_addr; | |
560 | scc_ports[i].dma = (unsigned long)dma_addr; | |
561 | pci_set_drvdata(dev, (void *) &scc_ports[i]); | |
562 | ||
563 | return 1; | |
564 | ||
565 | fail_3: | |
566 | iounmap(ctl_addr); | |
567 | fail_2: | |
568 | release_mem_region(dma_base, dma_size); | |
569 | fail_1: | |
570 | release_mem_region(ctl_base, ctl_size); | |
571 | fail_0: | |
572 | return -ENOMEM; | |
573 | } | |
574 | ||
575 | /** | |
576 | * init_setup_scc - set up an SCC PATA Controller | |
577 | * @dev: PCI device | |
578 | * @d: IDE PCI device | |
579 | * | |
580 | * Perform the initial set up for this device. | |
581 | */ | |
582 | ||
583 | static int __devinit init_setup_scc(struct pci_dev *dev, ide_pci_device_t *d) | |
584 | { | |
585 | unsigned long ctl_base; | |
586 | unsigned long dma_base; | |
587 | unsigned long cckctrl_port; | |
588 | unsigned long intmask_port; | |
589 | unsigned long mode_port; | |
590 | unsigned long ecmode_port; | |
591 | unsigned long dma_status_port; | |
592 | u32 reg = 0; | |
593 | struct scc_ports *ports; | |
594 | int rc; | |
595 | ||
596 | rc = setup_mmio_scc(dev, d->name); | |
597 | if (rc < 0) { | |
598 | return rc; | |
599 | } | |
600 | ||
601 | ports = pci_get_drvdata(dev); | |
602 | ctl_base = ports->ctl; | |
603 | dma_base = ports->dma; | |
604 | cckctrl_port = ctl_base + 0xff0; | |
605 | intmask_port = dma_base + 0x010; | |
606 | mode_port = ctl_base + 0x024; | |
607 | ecmode_port = ctl_base + 0xf00; | |
608 | dma_status_port = dma_base + 0x004; | |
609 | ||
610 | /* controller initialization */ | |
611 | reg = 0; | |
612 | out_be32((void*)cckctrl_port, reg); | |
613 | reg |= CCKCTRL_ATACLKOEN; | |
614 | out_be32((void*)cckctrl_port, reg); | |
615 | reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN; | |
616 | out_be32((void*)cckctrl_port, reg); | |
617 | reg |= CCKCTRL_CRST; | |
618 | out_be32((void*)cckctrl_port, reg); | |
619 | ||
620 | for (;;) { | |
621 | reg = in_be32((void*)cckctrl_port); | |
622 | if (reg & CCKCTRL_CRST) | |
623 | break; | |
624 | udelay(5000); | |
625 | } | |
626 | ||
627 | reg |= CCKCTRL_ATARESET; | |
628 | out_be32((void*)cckctrl_port, reg); | |
629 | ||
630 | out_be32((void*)ecmode_port, ECMODE_VALUE); | |
631 | out_be32((void*)mode_port, MODE_JCUSFEN); | |
632 | out_be32((void*)intmask_port, INTMASK_MSK); | |
633 | ||
634 | return ide_setup_pci_device(dev, d); | |
635 | } | |
636 | ||
637 | /** | |
638 | * init_mmio_iops_scc - set up the iops for MMIO | |
639 | * @hwif: interface to set up | |
640 | * | |
641 | */ | |
642 | ||
643 | static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif) | |
644 | { | |
645 | struct pci_dev *dev = hwif->pci_dev; | |
646 | struct scc_ports *ports = pci_get_drvdata(dev); | |
647 | unsigned long dma_base = ports->dma; | |
648 | ||
649 | ide_set_hwifdata(hwif, ports); | |
650 | ||
651 | hwif->INB = scc_ide_inb; | |
652 | hwif->INW = scc_ide_inw; | |
bde18a2e KI |
653 | hwif->INSW = scc_ide_insw; |
654 | hwif->INSL = scc_ide_insl; | |
655 | hwif->OUTB = scc_ide_outb; | |
656 | hwif->OUTBSYNC = scc_ide_outbsync; | |
657 | hwif->OUTW = scc_ide_outw; | |
bde18a2e KI |
658 | hwif->OUTSW = scc_ide_outsw; |
659 | hwif->OUTSL = scc_ide_outsl; | |
660 | ||
661 | hwif->io_ports[IDE_DATA_OFFSET] = dma_base + 0x20; | |
662 | hwif->io_ports[IDE_ERROR_OFFSET] = dma_base + 0x24; | |
663 | hwif->io_ports[IDE_NSECTOR_OFFSET] = dma_base + 0x28; | |
664 | hwif->io_ports[IDE_SECTOR_OFFSET] = dma_base + 0x2c; | |
665 | hwif->io_ports[IDE_LCYL_OFFSET] = dma_base + 0x30; | |
666 | hwif->io_ports[IDE_HCYL_OFFSET] = dma_base + 0x34; | |
667 | hwif->io_ports[IDE_SELECT_OFFSET] = dma_base + 0x38; | |
668 | hwif->io_ports[IDE_STATUS_OFFSET] = dma_base + 0x3c; | |
669 | hwif->io_ports[IDE_CONTROL_OFFSET] = dma_base + 0x40; | |
670 | ||
671 | hwif->irq = hwif->pci_dev->irq; | |
672 | hwif->dma_base = dma_base; | |
673 | hwif->config_data = ports->ctl; | |
2ad1e558 | 674 | hwif->mmio = 1; |
bde18a2e KI |
675 | } |
676 | ||
677 | /** | |
678 | * init_iops_scc - set up iops | |
679 | * @hwif: interface to set up | |
680 | * | |
681 | * Do the basic setup for the SCC hardware interface | |
682 | * and then do the MMIO setup. | |
683 | */ | |
684 | ||
685 | static void __devinit init_iops_scc(ide_hwif_t *hwif) | |
686 | { | |
687 | struct pci_dev *dev = hwif->pci_dev; | |
688 | hwif->hwif_data = NULL; | |
689 | if (pci_get_drvdata(dev) == NULL) | |
690 | return; | |
691 | init_mmio_iops_scc(hwif); | |
692 | } | |
693 | ||
694 | /** | |
695 | * init_hwif_scc - set up hwif | |
696 | * @hwif: interface to set up | |
697 | * | |
698 | * We do the basic set up of the interface structure. The SCC | |
699 | * requires several custom handlers so we override the default | |
700 | * ide DMA handlers appropriately. | |
701 | */ | |
702 | ||
703 | static void __devinit init_hwif_scc(ide_hwif_t *hwif) | |
704 | { | |
705 | struct scc_ports *ports = ide_get_hwifdata(hwif); | |
706 | ||
707 | ports->hwif_id = hwif->index; | |
708 | ||
709 | hwif->dma_command = hwif->dma_base; | |
710 | hwif->dma_status = hwif->dma_base + 0x04; | |
711 | hwif->dma_prdtable = hwif->dma_base + 0x08; | |
712 | ||
0ecdca26 BZ |
713 | /* PTERADD */ |
714 | out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma); | |
bde18a2e | 715 | |
0ecdca26 | 716 | hwif->dma_setup = scc_dma_setup; |
bde18a2e KI |
717 | hwif->ide_dma_end = scc_ide_dma_end; |
718 | hwif->speedproc = scc_tune_chipset; | |
26bcb879 | 719 | hwif->set_pio_mode = scc_set_pio_mode; |
bde18a2e | 720 | hwif->ide_dma_check = scc_config_drive_for_dma; |
06a9952b | 721 | hwif->ide_dma_test_irq = scc_dma_test_irq; |
4ae41ff8 | 722 | hwif->udma_filter = scc_udma_filter; |
bde18a2e KI |
723 | |
724 | hwif->drives[0].autotune = IDE_TUNE_AUTO; | |
725 | hwif->drives[1].autotune = IDE_TUNE_AUTO; | |
726 | ||
0ecdca26 | 727 | if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) { |
bde18a2e KI |
728 | hwif->ultra_mask = 0x7f; /* 133MHz */ |
729 | } else { | |
730 | hwif->ultra_mask = 0x3f; /* 100MHz */ | |
731 | } | |
732 | hwif->mwdma_mask = 0x00; | |
733 | hwif->swdma_mask = 0x00; | |
734 | hwif->atapi_dma = 1; | |
735 | ||
736 | /* we support 80c cable only. */ | |
49521f97 | 737 | hwif->cbl = ATA_CBL_PATA80; |
bde18a2e KI |
738 | |
739 | hwif->autodma = 0; | |
740 | if (!noautodma) | |
741 | hwif->autodma = 1; | |
742 | hwif->drives[0].autodma = hwif->autodma; | |
743 | hwif->drives[1].autodma = hwif->autodma; | |
744 | } | |
745 | ||
746 | #define DECLARE_SCC_DEV(name_str) \ | |
747 | { \ | |
748 | .name = name_str, \ | |
749 | .init_setup = init_setup_scc, \ | |
750 | .init_iops = init_iops_scc, \ | |
751 | .init_hwif = init_hwif_scc, \ | |
bde18a2e KI |
752 | .autodma = AUTODMA, \ |
753 | .bootable = ON_BOARD, \ | |
a5d8c5c8 | 754 | .host_flags = IDE_HFLAG_SINGLE, \ |
4099d143 | 755 | .pio_mask = ATA_PIO4, \ |
bde18a2e KI |
756 | } |
757 | ||
758 | static ide_pci_device_t scc_chipsets[] __devinitdata = { | |
759 | /* 0 */ DECLARE_SCC_DEV("sccIDE"), | |
760 | }; | |
761 | ||
762 | /** | |
763 | * scc_init_one - pci layer discovery entry | |
764 | * @dev: PCI device | |
765 | * @id: ident table entry | |
766 | * | |
767 | * Called by the PCI code when it finds an SCC PATA controller. | |
768 | * We then use the IDE PCI generic helper to do most of the work. | |
769 | */ | |
770 | ||
771 | static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
772 | { | |
773 | ide_pci_device_t *d = &scc_chipsets[id->driver_data]; | |
774 | return d->init_setup(dev, d); | |
775 | } | |
776 | ||
777 | /** | |
778 | * scc_remove - pci layer remove entry | |
779 | * @dev: PCI device | |
780 | * | |
781 | * Called by the PCI code when it removes an SCC PATA controller. | |
782 | */ | |
783 | ||
784 | static void __devexit scc_remove(struct pci_dev *dev) | |
785 | { | |
786 | struct scc_ports *ports = pci_get_drvdata(dev); | |
787 | ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id]; | |
788 | unsigned long ctl_base = pci_resource_start(dev, 0); | |
789 | unsigned long dma_base = pci_resource_start(dev, 1); | |
790 | unsigned long ctl_size = pci_resource_len(dev, 0); | |
791 | unsigned long dma_size = pci_resource_len(dev, 1); | |
792 | ||
793 | if (hwif->dmatable_cpu) { | |
794 | pci_free_consistent(hwif->pci_dev, | |
795 | PRD_ENTRIES * PRD_BYTES, | |
796 | hwif->dmatable_cpu, | |
797 | hwif->dmatable_dma); | |
798 | hwif->dmatable_cpu = NULL; | |
799 | } | |
800 | ||
801 | ide_unregister(hwif->index); | |
802 | ||
803 | hwif->chipset = ide_unknown; | |
804 | iounmap((void*)ports->dma); | |
805 | iounmap((void*)ports->ctl); | |
806 | release_mem_region(dma_base, dma_size); | |
807 | release_mem_region(ctl_base, ctl_size); | |
808 | memset(ports, 0, sizeof(*ports)); | |
809 | } | |
810 | ||
811 | static struct pci_device_id scc_pci_tbl[] = { | |
812 | { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
813 | { 0, }, | |
814 | }; | |
815 | MODULE_DEVICE_TABLE(pci, scc_pci_tbl); | |
816 | ||
817 | static struct pci_driver driver = { | |
818 | .name = "SCC IDE", | |
819 | .id_table = scc_pci_tbl, | |
820 | .probe = scc_init_one, | |
821 | .remove = scc_remove, | |
822 | }; | |
823 | ||
824 | static int scc_ide_init(void) | |
825 | { | |
826 | return ide_pci_register_driver(&driver); | |
827 | } | |
828 | ||
829 | module_init(scc_ide_init); | |
830 | /* -- No exit code? | |
831 | static void scc_ide_exit(void) | |
832 | { | |
833 | ide_pci_unregister_driver(&driver); | |
834 | } | |
835 | module_exit(scc_ide_exit); | |
836 | */ | |
837 | ||
838 | ||
839 | MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE"); | |
840 | MODULE_LICENSE("GPL"); |