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ide: use PCI_VDEVICE() macro
[mirror_ubuntu-bionic-kernel.git] / drivers / ide / pci / scc_pata.c
CommitLineData
bde18a2e
KI		 1/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat <alan@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/delay.h>
29#include <linux/hdreg.h>
30#include <linux/ide.h>
31#include <linux/init.h>
32
33#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
34
35#define SCC_PATA_NAME "scc IDE"
36
37#define TDVHSEL_MASTER 0x00000001
38#define TDVHSEL_SLAVE 0x00000004
39
40#define MODE_JCUSFEN 0x00000080
41
42#define CCKCTRL_ATARESET 0x00040000
43#define CCKCTRL_BUFCNT 0x00020000
44#define CCKCTRL_CRST 0x00010000
45#define CCKCTRL_OCLKEN 0x00000100
46#define CCKCTRL_ATACLKOEN 0x00000002
47#define CCKCTRL_LCLKEN 0x00000001
48
49#define QCHCD_IOS_SS 0x00000001
50
51#define QCHSD_STPDIAG 0x00020000
52
53#define INTMASK_MSK 0xD1000012
54#define INTSTS_SERROR 0x80000000
55#define INTSTS_PRERR 0x40000000
56#define INTSTS_RERR 0x10000000
57#define INTSTS_ICERR 0x01000000
58#define INTSTS_BMSINT 0x00000010
59#define INTSTS_BMHE 0x00000008
60#define INTSTS_IOIRQS 0x00000004
61#define INTSTS_INTRQ 0x00000002
62#define INTSTS_ACTEINT 0x00000001
63
64#define ECMODE_VALUE 0x01
65
66static struct scc_ports {
67 unsigned long ctl, dma;
68 unsigned char hwif_id; /* for removing hwif from system */
69} scc_ports[MAX_HWIFS];
70
71/* PIO transfer mode table */
72/* JCHST */
73static unsigned long JCHSTtbl[2][7] = {
74 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
75 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
76};
77
78/* JCHHT */
79static unsigned long JCHHTtbl[2][7] = {
80 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
81 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
82};
83
84/* JCHCT */
85static unsigned long JCHCTtbl[2][7] = {
86 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
87 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
88};
89
90
91/* DMA transfer mode table */
92/* JCHDCTM/JCHDCTS */
93static unsigned long JCHDCTxtbl[2][7] = {
94 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
95 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
96};
97
98/* JCSTWTM/JCSTWTS */
99static unsigned long JCSTWTxtbl[2][7] = {
100 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
101 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
102};
103
104/* JCTSS */
105static unsigned long JCTSStbl[2][7] = {
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
107 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
108};
109
110/* JCENVT */
111static unsigned long JCENVTtbl[2][7] = {
112 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
113 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
114};
115
116/* JCACTSELS/JCACTSELM */
117static unsigned long JCACTSELtbl[2][7] = {
118 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
119 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
120};
121
122
123static u8 scc_ide_inb(unsigned long port)
124{
125 u32 data = in_be32((void*)port);
126 return (u8)data;
127}
128
129static u16 scc_ide_inw(unsigned long port)
130{
131 u32 data = in_be32((void*)port);
132 return (u16)data;
133}
134
bde18a2e
KI		 135static void scc_ide_insw(unsigned long port, void *addr, u32 count)
136{
137 u16 *ptr = (u16 *)addr;
138 while (count--) {
139 *ptr++ = le16_to_cpu(in_be32((void*)port));
140 }
141}
142
143static void scc_ide_insl(unsigned long port, void *addr, u32 count)
144{
145 u16 *ptr = (u16 *)addr;
146 while (count--) {
147 *ptr++ = le16_to_cpu(in_be32((void*)port));
148 *ptr++ = le16_to_cpu(in_be32((void*)port));
149 }
150}
151
152static void scc_ide_outb(u8 addr, unsigned long port)
153{
154 out_be32((void*)port, addr);
155}
156
157static void scc_ide_outw(u16 addr, unsigned long port)
158{
159 out_be32((void*)port, addr);
160}
161
bde18a2e
KI		 162static void
163scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
164{
165 ide_hwif_t *hwif = HWIF(drive);
166
167 out_be32((void*)port, addr);
f644d47a 168 eieio();
bde18a2e 169 in_be32((void*)(hwif->dma_base + 0x01c));
f644d47a 170 eieio();
bde18a2e
KI		 171}
172
173static void
174scc_ide_outsw(unsigned long port, void *addr, u32 count)
175{
176 u16 *ptr = (u16 *)addr;
177 while (count--) {
178 out_be32((void*)port, cpu_to_le16(*ptr++));
179 }
180}
181
182static void
183scc_ide_outsl(unsigned long port, void *addr, u32 count)
184{
185 u16 *ptr = (u16 *)addr;
186 while (count--) {
187 out_be32((void*)port, cpu_to_le16(*ptr++));
188 out_be32((void*)port, cpu_to_le16(*ptr++));
189 }
190}
191
bde18a2e 192/**
88b2b32b
BZ		 193 * scc_set_pio_mode - set host controller for PIO mode
194 * @drive: drive
195 * @pio: PIO mode number
bde18a2e
KI		 196 *
197 * Load the timing settings for this device mode into the
198 * controller.
199 */
200
88b2b32b 201static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
bde18a2e
KI		 202{
203 ide_hwif_t *hwif = HWIF(drive);
204 struct scc_ports *ports = ide_get_hwifdata(hwif);
205 unsigned long ctl_base = ports->ctl;
206 unsigned long cckctrl_port = ctl_base + 0xff0;
207 unsigned long piosht_port = ctl_base + 0x000;
208 unsigned long pioct_port = ctl_base + 0x004;
209 unsigned long reg;
bde18a2e
KI		 210 int offset;
211
0ecdca26 212 reg = in_be32((void __iomem *)cckctrl_port);
bde18a2e
KI		 213 if (reg & CCKCTRL_ATACLKOEN) {
214 offset = 1; /* 133MHz */
215 } else {
216 offset = 0; /* 100MHz */
217 }
3fcece66 218 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
0ecdca26 219 out_be32((void __iomem *)piosht_port, reg);
3fcece66 220 reg = JCHCTtbl[offset][pio];
0ecdca26 221 out_be32((void __iomem *)pioct_port, reg);
3fcece66 222}
bde18a2e 223
bde18a2e 224/**
88b2b32b
BZ		 225 * scc_set_dma_mode - set host controller for DMA mode
226 * @drive: drive
227 * @speed: DMA mode
bde18a2e
KI		 228 *
229 * Load the timing settings for this device mode into the
230 * controller.
231 */
232
88b2b32b 233static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
bde18a2e
KI		 234{
235 ide_hwif_t *hwif = HWIF(drive);
bde18a2e
KI		 236 struct scc_ports *ports = ide_get_hwifdata(hwif);
237 unsigned long ctl_base = ports->ctl;
238 unsigned long cckctrl_port = ctl_base + 0xff0;
239 unsigned long mdmact_port = ctl_base + 0x008;
240 unsigned long mcrcst_port = ctl_base + 0x00c;
241 unsigned long sdmact_port = ctl_base + 0x010;
242 unsigned long scrcst_port = ctl_base + 0x014;
243 unsigned long udenvt_port = ctl_base + 0x018;
244 unsigned long tdvhsel_port = ctl_base + 0x020;
245 int is_slave = (&hwif->drives[1] == drive);
246 int offset, idx;
247 unsigned long reg;
248 unsigned long jcactsel;
249
0ecdca26 250 reg = in_be32((void __iomem *)cckctrl_port);
bde18a2e
KI		 251 if (reg & CCKCTRL_ATACLKOEN) {
252 offset = 1; /* 133MHz */
253 } else {
254 offset = 0; /* 100MHz */
255 }
256
257 switch (speed) {
258 case XFER_UDMA_6:
bde18a2e 259 case XFER_UDMA_5:
bde18a2e 260 case XFER_UDMA_4:
bde18a2e 261 case XFER_UDMA_3:
bde18a2e 262 case XFER_UDMA_2:
bde18a2e 263 case XFER_UDMA_1:
bde18a2e 264 case XFER_UDMA_0:
3fcece66 265 idx = speed - XFER_UDMA_0;
bde18a2e
KI		 266 break;
267 default:
88b2b32b 268 return;
bde18a2e
KI		 269 }
270
271 jcactsel = JCACTSELtbl[offset][idx];
272 if (is_slave) {
0ecdca26
BZ		 273 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
274 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
275 jcactsel = jcactsel << 2;
276 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
bde18a2e 277 } else {
0ecdca26
BZ		 278 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
279 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
280 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
bde18a2e
KI		 281 }
282 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
0ecdca26 283 out_be32((void __iomem *)udenvt_port, reg);
bde18a2e
KI		 284}
285
0ecdca26
BZ		 286/**
287 * scc_ide_dma_setup - begin a DMA phase
288 * @drive: target device
289 *
290 * Build an IDE DMA PRD (IDE speak for scatter gather table)
291 * and then set up the DMA transfer registers.
292 *
293 * Returns 0 on success. If a PIO fallback is required then 1
294 * is returned.
295 */
296
297static int scc_dma_setup(ide_drive_t *drive)
298{
299 ide_hwif_t *hwif = drive->hwif;
300 struct request *rq = HWGROUP(drive)->rq;
301 unsigned int reading;
302 u8 dma_stat;
303
304 if (rq_data_dir(rq))
305 reading = 0;
306 else
307 reading = 1 << 3;
308
309 /* fall back to pio! */
310 if (!ide_build_dmatable(drive, rq)) {
311 ide_map_sg(drive, rq);
312 return 1;
313 }
314
315 /* PRD table */
316 out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
317
318 /* specify r/w */
319 out_be32((void __iomem *)hwif->dma_command, reading);
320
321 /* read dma_status for INTR & ERROR flags */
322 dma_stat = in_be32((void __iomem *)hwif->dma_status);
323
324 /* clear INTR & ERROR flags */
325 out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
326 drive->waiting_for_dma = 1;
327 return 0;
328}
329
330
bde18a2e
KI		 331/**
332 * scc_ide_dma_end - Stop DMA
333 * @drive: IDE drive
334 *
335 * Check and clear INT Status register.
336 * Then call __ide_dma_end().
337 */
338
339static int scc_ide_dma_end(ide_drive_t * drive)
340{
341 ide_hwif_t *hwif = HWIF(drive);
342 unsigned long intsts_port = hwif->dma_base + 0x014;
343 u32 reg;
4ae41ff8
KI		 344 int dma_stat, data_loss = 0;
345 static int retry = 0;
346
347 /* errata A308 workaround: Step5 (check data loss) */
348 /* We don't check non ide_disk because it is limited to UDMA4 */
349 if (!(in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
350 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
351 reg = in_be32((void __iomem *)intsts_port);
352 if (!(reg & INTSTS_ACTEINT)) {
353 printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
354 drive->name);
355 data_loss = 1;
356 if (retry++) {
357 struct request *rq = HWGROUP(drive)->rq;
358 int unit;
359 /* ERROR_RESET and drive->crc_count are needed
360 * to reduce DMA transfer mode in retry process.
361 */
362 if (rq)
363 rq->errors |= ERROR_RESET;
364 for (unit = 0; unit < MAX_DRIVES; unit++) {
365 ide_drive_t *drive = &hwif->drives[unit];
366 drive->crc_count++;
367 }
368 }
369 }
370 }
bde18a2e
KI		 371
372 while (1) {
0ecdca26 373 reg = in_be32((void __iomem *)intsts_port);
bde18a2e
KI		 374
375 if (reg & INTSTS_SERROR) {
376 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
0ecdca26 377 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
bde18a2e 378
0ecdca26 379 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
bde18a2e
KI		 380 continue;
381 }
382
383 if (reg & INTSTS_PRERR) {
384 u32 maea0, maec0;
385 unsigned long ctl_base = hwif->config_data;
386
0ecdca26
BZ		 387 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
388 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
bde18a2e
KI		 389
390 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
391
0ecdca26 392 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
bde18a2e 393
0ecdca26 394 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
bde18a2e
KI		 395 continue;
396 }
397
398 if (reg & INTSTS_RERR) {
399 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
0ecdca26 400 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
bde18a2e 401
0ecdca26 402 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
bde18a2e
KI		 403 continue;
404 }
405
406 if (reg & INTSTS_ICERR) {
0ecdca26 407 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
bde18a2e
KI		 408
409 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
0ecdca26 410 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
bde18a2e
KI		 411 continue;
412 }
413
414 if (reg & INTSTS_BMSINT) {
415 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
0ecdca26 416 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
bde18a2e
KI		 417
418 ide_do_reset(drive);
419 continue;
420 }
421
422 if (reg & INTSTS_BMHE) {
0ecdca26 423 out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
bde18a2e
KI		 424 continue;
425 }
426
427 if (reg & INTSTS_ACTEINT) {
0ecdca26 428 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
bde18a2e
KI		 429 continue;
430 }
431
432 if (reg & INTSTS_IOIRQS) {
0ecdca26 433 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
bde18a2e
KI		 434 continue;
435 }
436 break;
437 }
438
4ae41ff8
KI		 439 dma_stat = __ide_dma_end(drive);
440 if (data_loss)
441 dma_stat |= 2; /* emulate DMA error (to retry command) */
442 return dma_stat;
bde18a2e
KI		 443}
444
06a9952b
AI		 445/* returns 1 if dma irq issued, 0 otherwise */
446static int scc_dma_test_irq(ide_drive_t *drive)
447{
4ae41ff8
KI		 448 ide_hwif_t *hwif = HWIF(drive);
449 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
06a9952b 450
4ae41ff8
KI		 451 /* SCC errata A252,A308 workaround: Step4 */
452 if ((in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
453 (int_stat & INTSTS_INTRQ))
06a9952b
AI		 454 return 1;
455
4ae41ff8
KI		 456 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
457 if (int_stat & INTSTS_IOIRQS)
06a9952b
AI		 458 return 1;
459
460 if (!drive->waiting_for_dma)
461 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
462 drive->name, __FUNCTION__);
463 return 0;
464}
465
4ae41ff8
KI		 466static u8 scc_udma_filter(ide_drive_t *drive)
467{
468 ide_hwif_t *hwif = drive->hwif;
469 u8 mask = hwif->ultra_mask;
470
471 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
472 if ((drive->media != ide_disk) && (mask & 0xE0)) {
473 printk(KERN_INFO "%s: limit %s to UDMA4\n",
474 SCC_PATA_NAME, drive->name);
475 mask = 0x1F;
476 }
477
478 return mask;
479}
480
bde18a2e
KI		 481/**
482 * setup_mmio_scc - map CTRL/BMID region
483 * @dev: PCI device we are configuring
484 * @name: device name
485 *
486 */
487
488static int setup_mmio_scc (struct pci_dev *dev, const char *name)
489{
490 unsigned long ctl_base = pci_resource_start(dev, 0);
491 unsigned long dma_base = pci_resource_start(dev, 1);
492 unsigned long ctl_size = pci_resource_len(dev, 0);
493 unsigned long dma_size = pci_resource_len(dev, 1);
0bd8496b
AV		 494 void __iomem *ctl_addr;
495 void __iomem *dma_addr;
bde18a2e
KI		 496 int i;
497
498 for (i = 0; i < MAX_HWIFS; i++) {
499 if (scc_ports[i].ctl == 0)
500 break;
501 }
502 if (i >= MAX_HWIFS)
503 return -ENOMEM;
504
505 if (!request_mem_region(ctl_base, ctl_size, name)) {
506 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
507 goto fail_0;
508 }
509
510 if (!request_mem_region(dma_base, dma_size, name)) {
511 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
512 goto fail_1;
513 }
514
515 if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
516 goto fail_2;
517
518 if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
519 goto fail_3;
520
521 pci_set_master(dev);
522 scc_ports[i].ctl = (unsigned long)ctl_addr;
523 scc_ports[i].dma = (unsigned long)dma_addr;
524 pci_set_drvdata(dev, (void *) &scc_ports[i]);
525
526 return 1;
527
528 fail_3:
529 iounmap(ctl_addr);
530 fail_2:
531 release_mem_region(dma_base, dma_size);
532 fail_1:
533 release_mem_region(ctl_base, ctl_size);
534 fail_0:
535 return -ENOMEM;
536}
537
538/**
539 * init_setup_scc - set up an SCC PATA Controller
540 * @dev: PCI device
541 * @d: IDE PCI device
542 *
543 * Perform the initial set up for this device.
544 */
545
546static int __devinit init_setup_scc(struct pci_dev *dev, ide_pci_device_t *d)
547{
548 unsigned long ctl_base;
549 unsigned long dma_base;
550 unsigned long cckctrl_port;
551 unsigned long intmask_port;
552 unsigned long mode_port;
553 unsigned long ecmode_port;
554 unsigned long dma_status_port;
555 u32 reg = 0;
556 struct scc_ports *ports;
557 int rc;
558
559 rc = setup_mmio_scc(dev, d->name);
560 if (rc < 0) {
561 return rc;
562 }
563
564 ports = pci_get_drvdata(dev);
565 ctl_base = ports->ctl;
566 dma_base = ports->dma;
567 cckctrl_port = ctl_base + 0xff0;
568 intmask_port = dma_base + 0x010;
569 mode_port = ctl_base + 0x024;
570 ecmode_port = ctl_base + 0xf00;
571 dma_status_port = dma_base + 0x004;
572
573 /* controller initialization */
574 reg = 0;
575 out_be32((void*)cckctrl_port, reg);
576 reg |= CCKCTRL_ATACLKOEN;
577 out_be32((void*)cckctrl_port, reg);
578 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
579 out_be32((void*)cckctrl_port, reg);
580 reg |= CCKCTRL_CRST;
581 out_be32((void*)cckctrl_port, reg);
582
583 for (;;) {
584 reg = in_be32((void*)cckctrl_port);
585 if (reg & CCKCTRL_CRST)
586 break;
587 udelay(5000);
588 }
589
590 reg |= CCKCTRL_ATARESET;
591 out_be32((void*)cckctrl_port, reg);
592
593 out_be32((void*)ecmode_port, ECMODE_VALUE);
594 out_be32((void*)mode_port, MODE_JCUSFEN);
595 out_be32((void*)intmask_port, INTMASK_MSK);
596
597 return ide_setup_pci_device(dev, d);
598}
599
600/**
601 * init_mmio_iops_scc - set up the iops for MMIO
602 * @hwif: interface to set up
603 *
604 */
605
606static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
607{
608 struct pci_dev *dev = hwif->pci_dev;
609 struct scc_ports *ports = pci_get_drvdata(dev);
610 unsigned long dma_base = ports->dma;
611
612 ide_set_hwifdata(hwif, ports);
613
614 hwif->INB = scc_ide_inb;
615 hwif->INW = scc_ide_inw;
bde18a2e
KI		 616 hwif->INSW = scc_ide_insw;
617 hwif->INSL = scc_ide_insl;
618 hwif->OUTB = scc_ide_outb;
619 hwif->OUTBSYNC = scc_ide_outbsync;
620 hwif->OUTW = scc_ide_outw;
bde18a2e
KI		 621 hwif->OUTSW = scc_ide_outsw;
622 hwif->OUTSL = scc_ide_outsl;
623
624 hwif->io_ports[IDE_DATA_OFFSET] = dma_base + 0x20;
625 hwif->io_ports[IDE_ERROR_OFFSET] = dma_base + 0x24;
626 hwif->io_ports[IDE_NSECTOR_OFFSET] = dma_base + 0x28;
627 hwif->io_ports[IDE_SECTOR_OFFSET] = dma_base + 0x2c;
628 hwif->io_ports[IDE_LCYL_OFFSET] = dma_base + 0x30;
629 hwif->io_ports[IDE_HCYL_OFFSET] = dma_base + 0x34;
630 hwif->io_ports[IDE_SELECT_OFFSET] = dma_base + 0x38;
631 hwif->io_ports[IDE_STATUS_OFFSET] = dma_base + 0x3c;
632 hwif->io_ports[IDE_CONTROL_OFFSET] = dma_base + 0x40;
633
634 hwif->irq = hwif->pci_dev->irq;
635 hwif->dma_base = dma_base;
636 hwif->config_data = ports->ctl;
2ad1e558 637 hwif->mmio = 1;
bde18a2e
KI		 638}
639
640/**
641 * init_iops_scc - set up iops
642 * @hwif: interface to set up
643 *
644 * Do the basic setup for the SCC hardware interface
645 * and then do the MMIO setup.
646 */
647
648static void __devinit init_iops_scc(ide_hwif_t *hwif)
649{
650 struct pci_dev *dev = hwif->pci_dev;
651 hwif->hwif_data = NULL;
652 if (pci_get_drvdata(dev) == NULL)
653 return;
654 init_mmio_iops_scc(hwif);
655}
656
657/**
658 * init_hwif_scc - set up hwif
659 * @hwif: interface to set up
660 *
661 * We do the basic set up of the interface structure. The SCC
662 * requires several custom handlers so we override the default
663 * ide DMA handlers appropriately.
664 */
665
666static void __devinit init_hwif_scc(ide_hwif_t *hwif)
667{
668 struct scc_ports *ports = ide_get_hwifdata(hwif);
669
670 ports->hwif_id = hwif->index;
671
672 hwif->dma_command = hwif->dma_base;
673 hwif->dma_status = hwif->dma_base + 0x04;
674 hwif->dma_prdtable = hwif->dma_base + 0x08;
675
0ecdca26
BZ		 676 /* PTERADD */
677 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
bde18a2e 678
0ecdca26 679 hwif->dma_setup = scc_dma_setup;
bde18a2e 680 hwif->ide_dma_end = scc_ide_dma_end;
26bcb879 681 hwif->set_pio_mode = scc_set_pio_mode;
88b2b32b 682 hwif->set_dma_mode = scc_set_dma_mode;
06a9952b 683 hwif->ide_dma_test_irq = scc_dma_test_irq;
4ae41ff8 684 hwif->udma_filter = scc_udma_filter;
bde18a2e
KI		 685
686 hwif->drives[0].autotune = IDE_TUNE_AUTO;
687 hwif->drives[1].autotune = IDE_TUNE_AUTO;
688
0ecdca26 689 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) {
bde18a2e
KI		 690 hwif->ultra_mask = 0x7f; /* 133MHz */
691 } else {
692 hwif->ultra_mask = 0x3f; /* 100MHz */
693 }
694 hwif->mwdma_mask = 0x00;
695 hwif->swdma_mask = 0x00;
696 hwif->atapi_dma = 1;
697
698 /* we support 80c cable only. */
49521f97 699 hwif->cbl = ATA_CBL_PATA80;
bde18a2e
KI		 700
701 hwif->autodma = 0;
702 if (!noautodma)
703 hwif->autodma = 1;
704 hwif->drives[0].autodma = hwif->autodma;
705 hwif->drives[1].autodma = hwif->autodma;
706}
707
708#define DECLARE_SCC_DEV(name_str) \
709 { \
710 .name = name_str, \
711 .init_setup = init_setup_scc, \
712 .init_iops = init_iops_scc, \
713 .init_hwif = init_hwif_scc, \
bde18a2e
KI		 714 .autodma = AUTODMA, \
715 .bootable = ON_BOARD, \
a5d8c5c8 716 .host_flags = IDE_HFLAG_SINGLE, \
4099d143 717 .pio_mask = ATA_PIO4, \
bde18a2e
KI		 718 }
719
720static ide_pci_device_t scc_chipsets[] __devinitdata = {
721 /* 0 */ DECLARE_SCC_DEV("sccIDE"),
722};
723
724/**
725 * scc_init_one - pci layer discovery entry
726 * @dev: PCI device
727 * @id: ident table entry
728 *
729 * Called by the PCI code when it finds an SCC PATA controller.
730 * We then use the IDE PCI generic helper to do most of the work.
731 */
732
733static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
734{
735 ide_pci_device_t *d = &scc_chipsets[id->driver_data];
736 return d->init_setup(dev, d);
737}
738
739/**
740 * scc_remove - pci layer remove entry
741 * @dev: PCI device
742 *
743 * Called by the PCI code when it removes an SCC PATA controller.
744 */
745
746static void __devexit scc_remove(struct pci_dev *dev)
747{
748 struct scc_ports *ports = pci_get_drvdata(dev);
749 ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id];
750 unsigned long ctl_base = pci_resource_start(dev, 0);
751 unsigned long dma_base = pci_resource_start(dev, 1);
752 unsigned long ctl_size = pci_resource_len(dev, 0);
753 unsigned long dma_size = pci_resource_len(dev, 1);
754
755 if (hwif->dmatable_cpu) {
756 pci_free_consistent(hwif->pci_dev,
757 PRD_ENTRIES * PRD_BYTES,
758 hwif->dmatable_cpu,
759 hwif->dmatable_dma);
760 hwif->dmatable_cpu = NULL;
761 }
762
763 ide_unregister(hwif->index);
764
765 hwif->chipset = ide_unknown;
766 iounmap((void*)ports->dma);
767 iounmap((void*)ports->ctl);
768 release_mem_region(dma_base, dma_size);
769 release_mem_region(ctl_base, ctl_size);
770 memset(ports, 0, sizeof(*ports));
771}
772
9cbcc5e3
BZ		 773static const struct pci_device_id scc_pci_tbl[] = {
774 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
bde18a2e
KI		 775 { 0, },
776};
777MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
778
779static struct pci_driver driver = {
780 .name = "SCC IDE",
781 .id_table = scc_pci_tbl,
782 .probe = scc_init_one,
783 .remove = scc_remove,
784};
785
786static int scc_ide_init(void)
787{
788 return ide_pci_register_driver(&driver);
789}
790
791module_init(scc_ide_init);
792/* -- No exit code?
793static void scc_ide_exit(void)
794{
795 ide_pci_unregister_driver(&driver);
796}
797module_exit(scc_ide_exit);
798 */
799
800
801MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
802MODULE_LICENSE("GPL");
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