]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/ide/pci/scc_pata.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
xfs ioctl __user annotations
[mirror_ubuntu-zesty-kernel.git] / drivers / ide / pci / scc_pata.c
CommitLineData
bde18a2e
KI		 1/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat <alan@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/delay.h>
29#include <linux/hdreg.h>
30#include <linux/ide.h>
31#include <linux/init.h>
32
33#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
34
35#define SCC_PATA_NAME "scc IDE"
36
37#define TDVHSEL_MASTER 0x00000001
38#define TDVHSEL_SLAVE 0x00000004
39
40#define MODE_JCUSFEN 0x00000080
41
42#define CCKCTRL_ATARESET 0x00040000
43#define CCKCTRL_BUFCNT 0x00020000
44#define CCKCTRL_CRST 0x00010000
45#define CCKCTRL_OCLKEN 0x00000100
46#define CCKCTRL_ATACLKOEN 0x00000002
47#define CCKCTRL_LCLKEN 0x00000001
48
49#define QCHCD_IOS_SS 0x00000001
50
51#define QCHSD_STPDIAG 0x00020000
52
53#define INTMASK_MSK 0xD1000012
54#define INTSTS_SERROR 0x80000000
55#define INTSTS_PRERR 0x40000000
56#define INTSTS_RERR 0x10000000
57#define INTSTS_ICERR 0x01000000
58#define INTSTS_BMSINT 0x00000010
59#define INTSTS_BMHE 0x00000008
60#define INTSTS_IOIRQS 0x00000004
61#define INTSTS_INTRQ 0x00000002
62#define INTSTS_ACTEINT 0x00000001
63
64#define ECMODE_VALUE 0x01
65
66static struct scc_ports {
67 unsigned long ctl, dma;
68 unsigned char hwif_id; /* for removing hwif from system */
69} scc_ports[MAX_HWIFS];
70
71/* PIO transfer mode table */
72/* JCHST */
73static unsigned long JCHSTtbl[2][7] = {
74 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
75 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
76};
77
78/* JCHHT */
79static unsigned long JCHHTtbl[2][7] = {
80 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
81 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
82};
83
84/* JCHCT */
85static unsigned long JCHCTtbl[2][7] = {
86 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
87 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
88};
89
90
91/* DMA transfer mode table */
92/* JCHDCTM/JCHDCTS */
93static unsigned long JCHDCTxtbl[2][7] = {
94 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
95 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
96};
97
98/* JCSTWTM/JCSTWTS */
99static unsigned long JCSTWTxtbl[2][7] = {
100 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
101 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
102};
103
104/* JCTSS */
105static unsigned long JCTSStbl[2][7] = {
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
107 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
108};
109
110/* JCENVT */
111static unsigned long JCENVTtbl[2][7] = {
112 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
113 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
114};
115
116/* JCACTSELS/JCACTSELM */
117static unsigned long JCACTSELtbl[2][7] = {
118 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
119 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
120};
121
122
123static u8 scc_ide_inb(unsigned long port)
124{
125 u32 data = in_be32((void*)port);
126 return (u8)data;
127}
128
129static u16 scc_ide_inw(unsigned long port)
130{
131 u32 data = in_be32((void*)port);
132 return (u16)data;
133}
134
bde18a2e
KI		 135static void scc_ide_insw(unsigned long port, void *addr, u32 count)
136{
137 u16 *ptr = (u16 *)addr;
138 while (count--) {
139 *ptr++ = le16_to_cpu(in_be32((void*)port));
140 }
141}
142
143static void scc_ide_insl(unsigned long port, void *addr, u32 count)
144{
145 u16 *ptr = (u16 *)addr;
146 while (count--) {
147 *ptr++ = le16_to_cpu(in_be32((void*)port));
148 *ptr++ = le16_to_cpu(in_be32((void*)port));
149 }
150}
151
152static void scc_ide_outb(u8 addr, unsigned long port)
153{
154 out_be32((void*)port, addr);
155}
156
157static void scc_ide_outw(u16 addr, unsigned long port)
158{
159 out_be32((void*)port, addr);
160}
161
bde18a2e
KI		 162static void
163scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
164{
165 ide_hwif_t *hwif = HWIF(drive);
166
167 out_be32((void*)port, addr);
f644d47a 168 eieio();
bde18a2e 169 in_be32((void*)(hwif->dma_base + 0x01c));
f644d47a 170 eieio();
bde18a2e
KI		 171}
172
173static void
174scc_ide_outsw(unsigned long port, void *addr, u32 count)
175{
176 u16 *ptr = (u16 *)addr;
177 while (count--) {
178 out_be32((void*)port, cpu_to_le16(*ptr++));
179 }
180}
181
182static void
183scc_ide_outsl(unsigned long port, void *addr, u32 count)
184{
185 u16 *ptr = (u16 *)addr;
186 while (count--) {
187 out_be32((void*)port, cpu_to_le16(*ptr++));
188 out_be32((void*)port, cpu_to_le16(*ptr++));
189 }
190}
191
bde18a2e
KI		 192/**
193 * scc_tuneproc - tune a drive PIO mode
194 * @drive: drive to tune
195 * @mode_wanted: the target operating mode
196 *
197 * Load the timing settings for this device mode into the
198 * controller.
199 */
200
201static void scc_tuneproc(ide_drive_t *drive, byte mode_wanted)
202{
203 ide_hwif_t *hwif = HWIF(drive);
204 struct scc_ports *ports = ide_get_hwifdata(hwif);
205 unsigned long ctl_base = ports->ctl;
206 unsigned long cckctrl_port = ctl_base + 0xff0;
207 unsigned long piosht_port = ctl_base + 0x000;
208 unsigned long pioct_port = ctl_base + 0x004;
209 unsigned long reg;
210 unsigned char speed = XFER_PIO_0;
211 int offset;
212
2134758d 213 mode_wanted = ide_get_best_pio_mode(drive, mode_wanted, 4);
bde18a2e
KI		 214 switch (mode_wanted) {
215 case 4:
216 speed = XFER_PIO_4;
217 break;
218 case 3:
219 speed = XFER_PIO_3;
220 break;
221 case 2:
222 speed = XFER_PIO_2;
223 break;
224 case 1:
225 speed = XFER_PIO_1;
226 break;
227 case 0:
228 default:
229 speed = XFER_PIO_0;
230 break;
231 }
232
0ecdca26 233 reg = in_be32((void __iomem *)cckctrl_port);
bde18a2e
KI		 234 if (reg & CCKCTRL_ATACLKOEN) {
235 offset = 1; /* 133MHz */
236 } else {
237 offset = 0; /* 100MHz */
238 }
239 reg = JCHSTtbl[offset][mode_wanted] << 16 | JCHHTtbl[offset][mode_wanted];
0ecdca26 240 out_be32((void __iomem *)piosht_port, reg);
bde18a2e 241 reg = JCHCTtbl[offset][mode_wanted];
0ecdca26 242 out_be32((void __iomem *)pioct_port, reg);
bde18a2e
KI		 243
244 ide_config_drive_speed(drive, speed);
245}
246
247/**
248 * scc_tune_chipset - tune a drive DMA mode
249 * @drive: Drive to set up
250 * @xferspeed: speed we want to achieve
251 *
252 * Load the timing settings for this device mode into the
253 * controller.
254 */
255
256static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed)
257{
258 ide_hwif_t *hwif = HWIF(drive);
2d5eaa6d 259 u8 speed = ide_rate_filter(drive, xferspeed);
bde18a2e
KI		 260 struct scc_ports *ports = ide_get_hwifdata(hwif);
261 unsigned long ctl_base = ports->ctl;
262 unsigned long cckctrl_port = ctl_base + 0xff0;
263 unsigned long mdmact_port = ctl_base + 0x008;
264 unsigned long mcrcst_port = ctl_base + 0x00c;
265 unsigned long sdmact_port = ctl_base + 0x010;
266 unsigned long scrcst_port = ctl_base + 0x014;
267 unsigned long udenvt_port = ctl_base + 0x018;
268 unsigned long tdvhsel_port = ctl_base + 0x020;
269 int is_slave = (&hwif->drives[1] == drive);
270 int offset, idx;
271 unsigned long reg;
272 unsigned long jcactsel;
273
0ecdca26 274 reg = in_be32((void __iomem *)cckctrl_port);
bde18a2e
KI		 275 if (reg & CCKCTRL_ATACLKOEN) {
276 offset = 1; /* 133MHz */
277 } else {
278 offset = 0; /* 100MHz */
279 }
280
281 switch (speed) {
282 case XFER_UDMA_6:
283 idx = 6;
284 break;
285 case XFER_UDMA_5:
286 idx = 5;
287 break;
288 case XFER_UDMA_4:
289 idx = 4;
290 break;
291 case XFER_UDMA_3:
292 idx = 3;
293 break;
294 case XFER_UDMA_2:
295 idx = 2;
296 break;
297 case XFER_UDMA_1:
298 idx = 1;
299 break;
300 case XFER_UDMA_0:
301 idx = 0;
302 break;
303 default:
304 return 1;
305 }
306
307 jcactsel = JCACTSELtbl[offset][idx];
308 if (is_slave) {
0ecdca26
BZ		 309 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
310 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
311 jcactsel = jcactsel << 2;
312 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
bde18a2e 313 } else {
0ecdca26
BZ		 314 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
315 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
316 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
bde18a2e
KI		 317 }
318 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
0ecdca26 319 out_be32((void __iomem *)udenvt_port, reg);
bde18a2e
KI		 320
321 return ide_config_drive_speed(drive, speed);
322}
323
bde18a2e
KI		 324/**
325 * scc_configure_drive_for_dma - set up for DMA transfers
326 * @drive: drive we are going to set up
327 *
328 * Set up the drive for DMA, tune the controller and drive as
329 * required.
330 * If the drive isn't suitable for DMA or we hit other problems
331 * then we will drop down to PIO and set up PIO appropriately.
332 * (return 1)
333 */
334
335static int scc_config_drive_for_dma(ide_drive_t *drive)
336{
4728d546 337 if (ide_tune_dma(drive))
3608b5d7 338 return 0;
7569e8dc 339
d8f4469d 340 if (ide_use_fast_pio(drive))
3608b5d7 341 scc_tuneproc(drive, 4);
d8f4469d 342
3608b5d7 343 return -1;
bde18a2e
KI		 344}
345
0ecdca26
BZ		 346/**
347 * scc_ide_dma_setup - begin a DMA phase
348 * @drive: target device
349 *
350 * Build an IDE DMA PRD (IDE speak for scatter gather table)
351 * and then set up the DMA transfer registers.
352 *
353 * Returns 0 on success. If a PIO fallback is required then 1
354 * is returned.
355 */
356
357static int scc_dma_setup(ide_drive_t *drive)
358{
359 ide_hwif_t *hwif = drive->hwif;
360 struct request *rq = HWGROUP(drive)->rq;
361 unsigned int reading;
362 u8 dma_stat;
363
364 if (rq_data_dir(rq))
365 reading = 0;
366 else
367 reading = 1 << 3;
368
369 /* fall back to pio! */
370 if (!ide_build_dmatable(drive, rq)) {
371 ide_map_sg(drive, rq);
372 return 1;
373 }
374
375 /* PRD table */
376 out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
377
378 /* specify r/w */
379 out_be32((void __iomem *)hwif->dma_command, reading);
380
381 /* read dma_status for INTR & ERROR flags */
382 dma_stat = in_be32((void __iomem *)hwif->dma_status);
383
384 /* clear INTR & ERROR flags */
385 out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
386 drive->waiting_for_dma = 1;
387 return 0;
388}
389
390
bde18a2e
KI		 391/**
392 * scc_ide_dma_end - Stop DMA
393 * @drive: IDE drive
394 *
395 * Check and clear INT Status register.
396 * Then call __ide_dma_end().
397 */
398
399static int scc_ide_dma_end(ide_drive_t * drive)
400{
401 ide_hwif_t *hwif = HWIF(drive);
402 unsigned long intsts_port = hwif->dma_base + 0x014;
403 u32 reg;
4ae41ff8
KI		 404 int dma_stat, data_loss = 0;
405 static int retry = 0;
406
407 /* errata A308 workaround: Step5 (check data loss) */
408 /* We don't check non ide_disk because it is limited to UDMA4 */
409 if (!(in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
410 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
411 reg = in_be32((void __iomem *)intsts_port);
412 if (!(reg & INTSTS_ACTEINT)) {
413 printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
414 drive->name);
415 data_loss = 1;
416 if (retry++) {
417 struct request *rq = HWGROUP(drive)->rq;
418 int unit;
419 /* ERROR_RESET and drive->crc_count are needed
420 * to reduce DMA transfer mode in retry process.
421 */
422 if (rq)
423 rq->errors |= ERROR_RESET;
424 for (unit = 0; unit < MAX_DRIVES; unit++) {
425 ide_drive_t *drive = &hwif->drives[unit];
426 drive->crc_count++;
427 }
428 }
429 }
430 }
bde18a2e
KI		 431
432 while (1) {
0ecdca26 433 reg = in_be32((void __iomem *)intsts_port);
bde18a2e
KI		 434
435 if (reg & INTSTS_SERROR) {
436 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
0ecdca26 437 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
bde18a2e 438
0ecdca26 439 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
bde18a2e
KI		 440 continue;
441 }
442
443 if (reg & INTSTS_PRERR) {
444 u32 maea0, maec0;
445 unsigned long ctl_base = hwif->config_data;
446
0ecdca26
BZ		 447 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
448 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
bde18a2e
KI		 449
450 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
451
0ecdca26 452 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
bde18a2e 453
0ecdca26 454 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
bde18a2e
KI		 455 continue;
456 }
457
458 if (reg & INTSTS_RERR) {
459 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
0ecdca26 460 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
bde18a2e 461
0ecdca26 462 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
bde18a2e
KI		 463 continue;
464 }
465
466 if (reg & INTSTS_ICERR) {
0ecdca26 467 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
bde18a2e
KI		 468
469 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
0ecdca26 470 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
bde18a2e
KI		 471 continue;
472 }
473
474 if (reg & INTSTS_BMSINT) {
475 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
0ecdca26 476 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
bde18a2e
KI		 477
478 ide_do_reset(drive);
479 continue;
480 }
481
482 if (reg & INTSTS_BMHE) {
0ecdca26 483 out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
bde18a2e
KI		 484 continue;
485 }
486
487 if (reg & INTSTS_ACTEINT) {
0ecdca26 488 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
bde18a2e
KI		 489 continue;
490 }
491
492 if (reg & INTSTS_IOIRQS) {
0ecdca26 493 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
bde18a2e
KI		 494 continue;
495 }
496 break;
497 }
498
4ae41ff8
KI		 499 dma_stat = __ide_dma_end(drive);
500 if (data_loss)
501 dma_stat |= 2; /* emulate DMA error (to retry command) */
502 return dma_stat;
bde18a2e
KI		 503}
504
06a9952b
AI		 505/* returns 1 if dma irq issued, 0 otherwise */
506static int scc_dma_test_irq(ide_drive_t *drive)
507{
4ae41ff8
KI		 508 ide_hwif_t *hwif = HWIF(drive);
509 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
06a9952b 510
4ae41ff8
KI		 511 /* SCC errata A252,A308 workaround: Step4 */
512 if ((in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
513 (int_stat & INTSTS_INTRQ))
06a9952b
AI		 514 return 1;
515
4ae41ff8
KI		 516 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
517 if (int_stat & INTSTS_IOIRQS)
06a9952b
AI		 518 return 1;
519
520 if (!drive->waiting_for_dma)
521 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
522 drive->name, __FUNCTION__);
523 return 0;
524}
525
4ae41ff8
KI		 526static u8 scc_udma_filter(ide_drive_t *drive)
527{
528 ide_hwif_t *hwif = drive->hwif;
529 u8 mask = hwif->ultra_mask;
530
531 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
532 if ((drive->media != ide_disk) && (mask & 0xE0)) {
533 printk(KERN_INFO "%s: limit %s to UDMA4\n",
534 SCC_PATA_NAME, drive->name);
535 mask = 0x1F;
536 }
537
538 return mask;
539}
540
bde18a2e
KI		 541/**
542 * setup_mmio_scc - map CTRL/BMID region
543 * @dev: PCI device we are configuring
544 * @name: device name
545 *
546 */
547
548static int setup_mmio_scc (struct pci_dev *dev, const char *name)
549{
550 unsigned long ctl_base = pci_resource_start(dev, 0);
551 unsigned long dma_base = pci_resource_start(dev, 1);
552 unsigned long ctl_size = pci_resource_len(dev, 0);
553 unsigned long dma_size = pci_resource_len(dev, 1);
554 void *ctl_addr;
555 void *dma_addr;
556 int i;
557
558 for (i = 0; i < MAX_HWIFS; i++) {
559 if (scc_ports[i].ctl == 0)
560 break;
561 }
562 if (i >= MAX_HWIFS)
563 return -ENOMEM;
564
565 if (!request_mem_region(ctl_base, ctl_size, name)) {
566 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
567 goto fail_0;
568 }
569
570 if (!request_mem_region(dma_base, dma_size, name)) {
571 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
572 goto fail_1;
573 }
574
575 if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
576 goto fail_2;
577
578 if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
579 goto fail_3;
580
581 pci_set_master(dev);
582 scc_ports[i].ctl = (unsigned long)ctl_addr;
583 scc_ports[i].dma = (unsigned long)dma_addr;
584 pci_set_drvdata(dev, (void *) &scc_ports[i]);
585
586 return 1;
587
588 fail_3:
589 iounmap(ctl_addr);
590 fail_2:
591 release_mem_region(dma_base, dma_size);
592 fail_1:
593 release_mem_region(ctl_base, ctl_size);
594 fail_0:
595 return -ENOMEM;
596}
597
598/**
599 * init_setup_scc - set up an SCC PATA Controller
600 * @dev: PCI device
601 * @d: IDE PCI device
602 *
603 * Perform the initial set up for this device.
604 */
605
606static int __devinit init_setup_scc(struct pci_dev *dev, ide_pci_device_t *d)
607{
608 unsigned long ctl_base;
609 unsigned long dma_base;
610 unsigned long cckctrl_port;
611 unsigned long intmask_port;
612 unsigned long mode_port;
613 unsigned long ecmode_port;
614 unsigned long dma_status_port;
615 u32 reg = 0;
616 struct scc_ports *ports;
617 int rc;
618
619 rc = setup_mmio_scc(dev, d->name);
620 if (rc < 0) {
621 return rc;
622 }
623
624 ports = pci_get_drvdata(dev);
625 ctl_base = ports->ctl;
626 dma_base = ports->dma;
627 cckctrl_port = ctl_base + 0xff0;
628 intmask_port = dma_base + 0x010;
629 mode_port = ctl_base + 0x024;
630 ecmode_port = ctl_base + 0xf00;
631 dma_status_port = dma_base + 0x004;
632
633 /* controller initialization */
634 reg = 0;
635 out_be32((void*)cckctrl_port, reg);
636 reg |= CCKCTRL_ATACLKOEN;
637 out_be32((void*)cckctrl_port, reg);
638 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
639 out_be32((void*)cckctrl_port, reg);
640 reg |= CCKCTRL_CRST;
641 out_be32((void*)cckctrl_port, reg);
642
643 for (;;) {
644 reg = in_be32((void*)cckctrl_port);
645 if (reg & CCKCTRL_CRST)
646 break;
647 udelay(5000);
648 }
649
650 reg |= CCKCTRL_ATARESET;
651 out_be32((void*)cckctrl_port, reg);
652
653 out_be32((void*)ecmode_port, ECMODE_VALUE);
654 out_be32((void*)mode_port, MODE_JCUSFEN);
655 out_be32((void*)intmask_port, INTMASK_MSK);
656
657 return ide_setup_pci_device(dev, d);
658}
659
660/**
661 * init_mmio_iops_scc - set up the iops for MMIO
662 * @hwif: interface to set up
663 *
664 */
665
666static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
667{
668 struct pci_dev *dev = hwif->pci_dev;
669 struct scc_ports *ports = pci_get_drvdata(dev);
670 unsigned long dma_base = ports->dma;
671
672 ide_set_hwifdata(hwif, ports);
673
674 hwif->INB = scc_ide_inb;
675 hwif->INW = scc_ide_inw;
bde18a2e
KI		 676 hwif->INSW = scc_ide_insw;
677 hwif->INSL = scc_ide_insl;
678 hwif->OUTB = scc_ide_outb;
679 hwif->OUTBSYNC = scc_ide_outbsync;
680 hwif->OUTW = scc_ide_outw;
bde18a2e
KI		 681 hwif->OUTSW = scc_ide_outsw;
682 hwif->OUTSL = scc_ide_outsl;
683
684 hwif->io_ports[IDE_DATA_OFFSET] = dma_base + 0x20;
685 hwif->io_ports[IDE_ERROR_OFFSET] = dma_base + 0x24;
686 hwif->io_ports[IDE_NSECTOR_OFFSET] = dma_base + 0x28;
687 hwif->io_ports[IDE_SECTOR_OFFSET] = dma_base + 0x2c;
688 hwif->io_ports[IDE_LCYL_OFFSET] = dma_base + 0x30;
689 hwif->io_ports[IDE_HCYL_OFFSET] = dma_base + 0x34;
690 hwif->io_ports[IDE_SELECT_OFFSET] = dma_base + 0x38;
691 hwif->io_ports[IDE_STATUS_OFFSET] = dma_base + 0x3c;
692 hwif->io_ports[IDE_CONTROL_OFFSET] = dma_base + 0x40;
693
694 hwif->irq = hwif->pci_dev->irq;
695 hwif->dma_base = dma_base;
696 hwif->config_data = ports->ctl;
2ad1e558 697 hwif->mmio = 1;
bde18a2e
KI		 698}
699
700/**
701 * init_iops_scc - set up iops
702 * @hwif: interface to set up
703 *
704 * Do the basic setup for the SCC hardware interface
705 * and then do the MMIO setup.
706 */
707
708static void __devinit init_iops_scc(ide_hwif_t *hwif)
709{
710 struct pci_dev *dev = hwif->pci_dev;
711 hwif->hwif_data = NULL;
712 if (pci_get_drvdata(dev) == NULL)
713 return;
714 init_mmio_iops_scc(hwif);
715}
716
717/**
718 * init_hwif_scc - set up hwif
719 * @hwif: interface to set up
720 *
721 * We do the basic set up of the interface structure. The SCC
722 * requires several custom handlers so we override the default
723 * ide DMA handlers appropriately.
724 */
725
726static void __devinit init_hwif_scc(ide_hwif_t *hwif)
727{
728 struct scc_ports *ports = ide_get_hwifdata(hwif);
729
730 ports->hwif_id = hwif->index;
731
732 hwif->dma_command = hwif->dma_base;
733 hwif->dma_status = hwif->dma_base + 0x04;
734 hwif->dma_prdtable = hwif->dma_base + 0x08;
735
0ecdca26
BZ		 736 /* PTERADD */
737 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
bde18a2e 738
0ecdca26 739 hwif->dma_setup = scc_dma_setup;
bde18a2e
KI		 740 hwif->ide_dma_end = scc_ide_dma_end;
741 hwif->speedproc = scc_tune_chipset;
742 hwif->tuneproc = scc_tuneproc;
743 hwif->ide_dma_check = scc_config_drive_for_dma;
06a9952b 744 hwif->ide_dma_test_irq = scc_dma_test_irq;
4ae41ff8 745 hwif->udma_filter = scc_udma_filter;
bde18a2e
KI		 746
747 hwif->drives[0].autotune = IDE_TUNE_AUTO;
748 hwif->drives[1].autotune = IDE_TUNE_AUTO;
749
0ecdca26 750 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) {
bde18a2e
KI		 751 hwif->ultra_mask = 0x7f; /* 133MHz */
752 } else {
753 hwif->ultra_mask = 0x3f; /* 100MHz */
754 }
755 hwif->mwdma_mask = 0x00;
756 hwif->swdma_mask = 0x00;
757 hwif->atapi_dma = 1;
758
759 /* we support 80c cable only. */
49521f97 760 hwif->cbl = ATA_CBL_PATA80;
bde18a2e
KI		 761
762 hwif->autodma = 0;
763 if (!noautodma)
764 hwif->autodma = 1;
765 hwif->drives[0].autodma = hwif->autodma;
766 hwif->drives[1].autodma = hwif->autodma;
767}
768
769#define DECLARE_SCC_DEV(name_str) \
770 { \
771 .name = name_str, \
772 .init_setup = init_setup_scc, \
773 .init_iops = init_iops_scc, \
774 .init_hwif = init_hwif_scc, \
bde18a2e
KI		 775 .autodma = AUTODMA, \
776 .bootable = ON_BOARD, \
a5d8c5c8 777 .host_flags = IDE_HFLAG_SINGLE, \
4099d143 778 .pio_mask = ATA_PIO4, \
bde18a2e
KI		 779 }
780
781static ide_pci_device_t scc_chipsets[] __devinitdata = {
782 /* 0 */ DECLARE_SCC_DEV("sccIDE"),
783};
784
785/**
786 * scc_init_one - pci layer discovery entry
787 * @dev: PCI device
788 * @id: ident table entry
789 *
790 * Called by the PCI code when it finds an SCC PATA controller.
791 * We then use the IDE PCI generic helper to do most of the work.
792 */
793
794static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
795{
796 ide_pci_device_t *d = &scc_chipsets[id->driver_data];
797 return d->init_setup(dev, d);
798}
799
800/**
801 * scc_remove - pci layer remove entry
802 * @dev: PCI device
803 *
804 * Called by the PCI code when it removes an SCC PATA controller.
805 */
806
807static void __devexit scc_remove(struct pci_dev *dev)
808{
809 struct scc_ports *ports = pci_get_drvdata(dev);
810 ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id];
811 unsigned long ctl_base = pci_resource_start(dev, 0);
812 unsigned long dma_base = pci_resource_start(dev, 1);
813 unsigned long ctl_size = pci_resource_len(dev, 0);
814 unsigned long dma_size = pci_resource_len(dev, 1);
815
816 if (hwif->dmatable_cpu) {
817 pci_free_consistent(hwif->pci_dev,
818 PRD_ENTRIES * PRD_BYTES,
819 hwif->dmatable_cpu,
820 hwif->dmatable_dma);
821 hwif->dmatable_cpu = NULL;
822 }
823
824 ide_unregister(hwif->index);
825
826 hwif->chipset = ide_unknown;
827 iounmap((void*)ports->dma);
828 iounmap((void*)ports->ctl);
829 release_mem_region(dma_base, dma_size);
830 release_mem_region(ctl_base, ctl_size);
831 memset(ports, 0, sizeof(*ports));
832}
833
834static struct pci_device_id scc_pci_tbl[] = {
835 { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
836 { 0, },
837};
838MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
839
840static struct pci_driver driver = {
841 .name = "SCC IDE",
842 .id_table = scc_pci_tbl,
843 .probe = scc_init_one,
844 .remove = scc_remove,
845};
846
847static int scc_ide_init(void)
848{
849 return ide_pci_register_driver(&driver);
850}
851
852module_init(scc_ide_init);
853/* -- No exit code?
854static void scc_ide_exit(void)
855{
856 ide_pci_unregister_driver(&driver);
857}
858module_exit(scc_ide_exit);
859 */
860
861
862MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
863MODULE_LICENSE("GPL");
ubuntu-zesty-kernel mirror