[mirror_ubuntu-bionic-kernel.git] / drivers / ide / pci / serverworks.c

/*
 * linux/drivers/ide/pci/serverworks.c		Version 0.8	 25 Ebr 2003
 *
 * Copyright (C) 1998-2000 Michel Aubry
 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 * Portions copyright (c) 2001 Sun Microsystems
 *
 *
 * RCC/ServerWorks IDE driver for Linux
 *
 *   OSB4: `Open South Bridge' IDE Interface (fn 1)
 *         supports UDMA mode 2 (33 MB/s)
 *
 *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
 *         all revisions support UDMA mode 4 (66 MB/s)
 *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
 *
 *         *** The CSB5 does not provide ANY register ***
 *         *** to detect 80-conductor cable presence. ***
 *
 *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
 *
 *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
 *   controller same as the CSB6. Single channel ATA100 only.
 *
 * Documentation:
 *	Available under NDA only. Errata info very hard to get.
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>
#include <linux/delay.h>

#include <asm/io.h>

#define SVWKS_CSB5_REVISION_NEW	0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
#define SVWKS_CSB6_REVISION	0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */

/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
 * can overrun their FIFOs when used with the CSB5 */
static const char *svwks_bad_ata100[] = {
	"ST320011A",
	"ST340016A",
	"ST360021A",
	"ST380021A",
	NULL
};

static u8 svwks_revision = 0;
static struct pci_dev *isa_dev;

static int check_in_drive_lists (ide_drive_t *drive, const char **list)
{
	while (*list)
		if (!strcmp(*list++, drive->id->model))
			return 1;
	return 0;
}

static u8 svwks_ratemask (ide_drive_t *drive)
{
	struct pci_dev *dev     = HWIF(drive)->pci_dev;
	u8 mode = 0;

	if (!svwks_revision)
		pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);

	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
		return 2;
	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
		u32 reg = 0;
		if (isa_dev)
			pci_read_config_dword(isa_dev, 0x64, &reg);
			
		/*
		 *	Don't enable UDMA on disk devices for the moment
		 */
		if(drive->media == ide_disk)
			return 0;
		/* Check the OSB4 DMA33 enable bit */
		return ((reg & 0x00004000) == 0x00004000) ? 1 : 0;
	} else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
		return 1;
	} else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
		u8 btr = 0;
		pci_read_config_byte(dev, 0x5A, &btr);
		mode = btr & 0x3;
		if (!eighty_ninty_three(drive))
			mode = min(mode, (u8)1);
		/* If someone decides to do UDMA133 on CSB5 the same
		   issue will bite so be inclusive */
		if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
			mode = 2;
	}
	if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
	     (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
	    (!(PCI_FUNC(dev->devfn) & 1)))
		mode = 2;
	return mode;
}

static u8 svwks_csb_check (struct pci_dev *dev)
{
	switch (dev->device) {
		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
			return 1;
		default:
			break;
	}
	return 0;
}
static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
{
	static const u8 udma_modes[]		= { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
	static const u8 dma_modes[]		= { 0x77, 0x21, 0x20 };
	static const u8 pio_modes[]		= { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	static const u8 drive_pci[]		= { 0x41, 0x40, 0x43, 0x42 };
	static const u8 drive_pci2[]		= { 0x45, 0x44, 0x47, 0x46 };

	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 speed;
	u8 pio			= ide_get_best_pio_mode(drive, 255, 5, NULL);
	u8 unit			= (drive->select.b.unit & 0x01);
	u8 csb5			= svwks_csb_check(dev);
	u8 ultra_enable		= 0, ultra_timing = 0;
	u8 dma_timing		= 0, pio_timing = 0;
	u16 csb5_pio		= 0;

	if (xferspeed == 255)	/* PIO auto-tuning */
		speed = XFER_PIO_0 + pio;
	else
		speed = ide_rate_filter(svwks_ratemask(drive), xferspeed);

	/* If we are about to put a disk into UDMA mode we screwed up.
	   Our code assumes we never _ever_ do this on an OSB4 */
	   
	if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
		drive->media == ide_disk && speed >= XFER_UDMA_0)
			BUG();
			
	pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
	pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
	pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
	pci_read_config_word(dev, 0x4A, &csb5_pio);
	pci_read_config_byte(dev, 0x54, &ultra_enable);

	/* Per Specified Design by OEM, and ASIC Architect */
	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
		if (!drive->init_speed) {
			u8 dma_stat = inb(hwif->dma_status);

dma_pio:
			if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
			    ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
				drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
				return 0;
			} else if ((dma_timing) &&
				   ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
				u8 dmaspeed = dma_timing;

				dma_timing &= ~0xFF;
				if ((dmaspeed & 0x20) == 0x20)
					dmaspeed = XFER_MW_DMA_2;
				else if ((dmaspeed & 0x21) == 0x21)
					dmaspeed = XFER_MW_DMA_1;
				else if ((dmaspeed & 0x77) == 0x77)
					dmaspeed = XFER_MW_DMA_0;
				else
					goto dma_pio;
				drive->current_speed = drive->init_speed = dmaspeed;
				return 0;
			} else if (pio_timing) {
				u8 piospeed = pio_timing;

				pio_timing &= ~0xFF;
				if ((piospeed & 0x20) == 0x20)
					piospeed = XFER_PIO_4;
				else if ((piospeed & 0x22) == 0x22)
					piospeed = XFER_PIO_3;
				else if ((piospeed & 0x34) == 0x34)
					piospeed = XFER_PIO_2;
				else if ((piospeed & 0x47) == 0x47)
					piospeed = XFER_PIO_1;
				else if ((piospeed & 0x5d) == 0x5d)
					piospeed = XFER_PIO_0;
				else
					goto oem_setup_failed;
				drive->current_speed = drive->init_speed = piospeed;
				return 0;
			}
		}
	}

oem_setup_failed:

	pio_timing	&= ~0xFF;
	dma_timing	&= ~0xFF;
	ultra_timing	&= ~(0x0F << (4*unit));
	ultra_enable	&= ~(0x01 << drive->dn);
	csb5_pio	&= ~(0x0F << (4*drive->dn));

	switch(speed) {
		case XFER_PIO_4:
		case XFER_PIO_3:
		case XFER_PIO_2:
		case XFER_PIO_1:
		case XFER_PIO_0:
			pio_timing |= pio_modes[speed - XFER_PIO_0];
			csb5_pio   |= ((speed - XFER_PIO_0) << (4*drive->dn));
			break;

		case XFER_MW_DMA_2:
		case XFER_MW_DMA_1:
		case XFER_MW_DMA_0:
			pio_timing |= pio_modes[pio];
			csb5_pio   |= (pio << (4*drive->dn));
			dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
			break;

		case XFER_UDMA_5:
		case XFER_UDMA_4:
		case XFER_UDMA_3:
		case XFER_UDMA_2:
		case XFER_UDMA_1:
		case XFER_UDMA_0:
			pio_timing   |= pio_modes[pio];
			csb5_pio     |= (pio << (4*drive->dn));
			dma_timing   |= dma_modes[2];
			ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
			ultra_enable |= (0x01 << drive->dn);
		default:
			break;
	}

	pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
	if (csb5)
		pci_write_config_word(dev, 0x4A, csb5_pio);

	pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
	pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
	pci_write_config_byte(dev, 0x54, ultra_enable);

	return (ide_config_drive_speed(drive, speed));
}

static void config_chipset_for_pio (ide_drive_t *drive)
{
	u16 eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
	u16 xfer_pio = drive->id->eide_pio_modes;
	u8 timing, speed, pio;

	pio = ide_get_best_pio_mode(drive, 255, 5, NULL);

	if (xfer_pio > 4)
		xfer_pio = 0;

	if (drive->id->eide_pio_iordy > 0)
		for (xfer_pio = 5;
			xfer_pio>0 &&
			drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
			xfer_pio--);
	else
		xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
			   (drive->id->eide_pio_modes & 2) ? 0x04 :
			   (drive->id->eide_pio_modes & 1) ? 0x03 :
			   (drive->id->tPIO & 2) ? 0x02 :
			   (drive->id->tPIO & 1) ? 0x01 : xfer_pio;

	timing = (xfer_pio >= pio) ? xfer_pio : pio;

	switch(timing) {
		case 4: speed = XFER_PIO_4;break;
		case 3: speed = XFER_PIO_3;break;
		case 2: speed = XFER_PIO_2;break;
		case 1: speed = XFER_PIO_1;break;
		default:
			speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
			break;
	}
	(void) svwks_tune_chipset(drive, speed);
	drive->current_speed = speed;
}

static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
{
	if(pio == 255)
		(void) svwks_tune_chipset(drive, 255);
	else
		(void) svwks_tune_chipset(drive, (XFER_PIO_0 + pio));
}

static int config_chipset_for_dma (ide_drive_t *drive)
{
	u8 speed = ide_dma_speed(drive, svwks_ratemask(drive));

	if (!(speed))
		speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);

	(void) svwks_tune_chipset(drive, speed);
	return ide_dma_enable(drive);
}

static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);

	drive->init_speed = 0;

	if (ide_use_dma(drive) && config_chipset_for_dma(drive))
		return hwif->ide_dma_on(drive);

	if (ide_use_fast_pio(drive)) {
		config_chipset_for_pio(drive);
		//	hwif->tuneproc(drive, 5);
		return hwif->ide_dma_off_quietly(drive);
	}
	/* IORDY not supported */
	return 0;
}

static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
{
	unsigned int reg;
	u8 btr;

	/* save revision id to determine DMA capability */
	pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);

	/* force Master Latency Timer value to 64 PCICLKs */
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);

	/* OSB4 : South Bridge and IDE */
	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
		isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
			  PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
		if (isa_dev) {
			pci_read_config_dword(isa_dev, 0x64, &reg);
			reg &= ~0x00002000; /* disable 600ns interrupt mask */
			if(!(reg & 0x00004000))
				printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
			reg |=  0x00004000; /* enable UDMA/33 support */
			pci_write_config_dword(isa_dev, 0x64, reg);
		}
	}

	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {

		/* Third Channel Test */
		if (!(PCI_FUNC(dev->devfn) & 1)) {
			struct pci_dev * findev = NULL;
			u32 reg4c = 0;
			findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
				PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
			if (findev) {
				pci_read_config_dword(findev, 0x4C, &reg4c);
				reg4c &= ~0x000007FF;
				reg4c |=  0x00000040;
				reg4c |=  0x00000020;
				pci_write_config_dword(findev, 0x4C, reg4c);
				pci_dev_put(findev);
			}
			outb_p(0x06, 0x0c00);
			dev->irq = inb_p(0x0c01);
		} else {
			struct pci_dev * findev = NULL;
			u8 reg41 = 0;

			findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
					PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
			if (findev) {
				pci_read_config_byte(findev, 0x41, &reg41);
				reg41 &= ~0x40;
				pci_write_config_byte(findev, 0x41, reg41);
				pci_dev_put(findev);
			}
			/*
			 * This is a device pin issue on CSB6.
			 * Since there will be a future raid mode,
			 * early versions of the chipset require the
			 * interrupt pin to be set, and it is a compatibility
			 * mode issue.
			 */
			if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
				dev->irq = 0;
		}
//		pci_read_config_dword(dev, 0x40, &pioreg)
//		pci_write_config_dword(dev, 0x40, 0x99999999);
//		pci_read_config_dword(dev, 0x44, &dmareg);
//		pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
		/* setup the UDMA Control register
		 *
		 * 1. clear bit 6 to enable DMA
		 * 2. enable DMA modes with bits 0-1
		 * 	00 : legacy
		 * 	01 : udma2
		 * 	10 : udma2/udma4
		 * 	11 : udma2/udma4/udma5
		 */
		pci_read_config_byte(dev, 0x5A, &btr);
		btr &= ~0x40;
		if (!(PCI_FUNC(dev->devfn) & 1))
			btr |= 0x2;
		else
			btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
		pci_write_config_byte(dev, 0x5A, btr);
	}
	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
		pci_read_config_byte(dev, 0x5A, &btr);
		btr &= ~0x40;
		btr |= 0x3;
		pci_write_config_byte(dev, 0x5A, btr);
	}

	return dev->irq;
}

static unsigned int __devinit ata66_svwks_svwks (ide_hwif_t *hwif)
{
	return 1;
}

/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 * of the subsystem device ID indicate presence of an 80-pin cable.
 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 * Bit 15 set   = secondary IDE channel has 80-pin cable.
 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 * Bit 14 set   = primary IDE channel has 80-pin cable.
 */
static unsigned int __devinit ata66_svwks_dell (ide_hwif_t *hwif)
{
	struct pci_dev *dev = hwif->pci_dev;
	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
	    dev->vendor	== PCI_VENDOR_ID_SERVERWORKS &&
	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
	     dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
		return ((1 << (hwif->channel + 14)) &
			dev->subsystem_device) ? 1 : 0;
	return 0;
}

/* Sun Cobalt Alpine hardware avoids the 80-pin cable
 * detect issue by attaching the drives directly to the board.
 * This check follows the Dell precedent (how scary is that?!)
 *
 * WARNING: this only works on Alpine hardware!
 */
static unsigned int __devinit ata66_svwks_cobalt (ide_hwif_t *hwif)
{
	struct pci_dev *dev = hwif->pci_dev;
	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
	    dev->vendor	== PCI_VENDOR_ID_SERVERWORKS &&
	    dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
		return ((1 << (hwif->channel + 14)) &
			dev->subsystem_device) ? 1 : 0;
	return 0;
}

static unsigned int __devinit ata66_svwks (ide_hwif_t *hwif)
{
	struct pci_dev *dev = hwif->pci_dev;

	/* Server Works */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
		return ata66_svwks_svwks (hwif);
	
	/* Dell PowerEdge */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
		return ata66_svwks_dell (hwif);

	/* Cobalt Alpine */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
		return ata66_svwks_cobalt (hwif);

	/* Per Specified Design by OEM, and ASIC Architect */
	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
		return 1;

	return 0;
}

static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
{
	u8 dma_stat = 0;

	if (!hwif->irq)
		hwif->irq = hwif->channel ? 15 : 14;

	hwif->tuneproc = &svwks_tune_drive;
	hwif->speedproc = &svwks_tune_chipset;

	hwif->atapi_dma = 1;

	if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
		hwif->ultra_mask = 0x3f;

	hwif->mwdma_mask = 0x07;

	hwif->autodma = 0;

	if (!hwif->dma_base) {
		hwif->drives[0].autotune = 1;
		hwif->drives[1].autotune = 1;
		return;
	}

	hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
	if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
		if (!hwif->udma_four)
			hwif->udma_four = ata66_svwks(hwif);
	}
	if (!noautodma)
		hwif->autodma = 1;

	dma_stat = inb(hwif->dma_status);
	hwif->drives[0].autodma = (dma_stat & 0x20);
	hwif->drives[1].autodma = (dma_stat & 0x40);
	hwif->drives[0].autotune = (!(dma_stat & 0x20));
	hwif->drives[1].autotune = (!(dma_stat & 0x40));
}

static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
{
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
{
	if (!(PCI_FUNC(dev->devfn) & 1)) {
		d->bootable = NEVER_BOARD;
		if (dev->resource[0].start == 0x01f1)
			d->bootable = ON_BOARD;
	}

	d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
			dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
		       (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;

	return ide_setup_pci_device(dev, d);
}

static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "SvrWks OSB4",
		.init_setup	= init_setup_svwks,
		.init_chipset	= init_chipset_svwks,
		.init_hwif	= init_hwif_svwks,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= ON_BOARD,
	},{	/* 1 */
		.name		= "SvrWks CSB5",
		.init_setup	= init_setup_svwks,
		.init_chipset	= init_chipset_svwks,
		.init_hwif	= init_hwif_svwks,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= ON_BOARD,
	},{	/* 2 */
		.name		= "SvrWks CSB6",
		.init_setup	= init_setup_csb6,
		.init_chipset	= init_chipset_svwks,
		.init_hwif	= init_hwif_svwks,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= ON_BOARD,
	},{	/* 3 */
		.name		= "SvrWks CSB6",
		.init_setup	= init_setup_csb6,
		.init_chipset	= init_chipset_svwks,
		.init_hwif	= init_hwif_svwks,
		.channels	= 1,	/* 2 */
		.autodma	= AUTODMA,
		.bootable	= ON_BOARD,
	},{	/* 4 */
		.name		= "SvrWks HT1000",
		.init_setup	= init_setup_svwks,
		.init_chipset	= init_chipset_svwks,
		.init_hwif	= init_hwif_svwks,
		.channels	= 1,	/* 2 */
		.autodma	= AUTODMA,
		.bootable	= ON_BOARD,
	}
};

/**
 *	svwks_init_one	-	called when a OSB/CSB is found
 *	@dev: the svwks device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];

	return d->init_setup(dev, d);
}

static struct pci_device_id svwks_pci_tbl[] = {
	{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
	{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
	{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);

static struct pci_driver driver = {
	.name		= "Serverworks_IDE",
	.id_table	= svwks_pci_tbl,
	.probe		= svwks_init_one,
};

static int __init svwks_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(svwks_ide_init);

MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/ide/pci/serverworks.c Version 0.8 25 Ebr 2003
	3	*
	4	* Copyright (C) 1998-2000 Michel Aubry
	5	* Copyright (C) 1998-2000 Andrzej Krzysztofowicz
	6	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
	7	* Portions copyright (c) 2001 Sun Microsystems
	8	*
	9	*
	10	* RCC/ServerWorks IDE driver for Linux
	11	*
	12	* OSB4: `Open South Bridge' IDE Interface (fn 1)
	13	* supports UDMA mode 2 (33 MB/s)
	14	*
	15	* CSB5: `Champion South Bridge' IDE Interface (fn 1)
	16	* all revisions support UDMA mode 4 (66 MB/s)
	17	* revision A2.0 and up support UDMA mode 5 (100 MB/s)
	18	*
	19	* * The CSB5 does not provide ANY register *
	20	* * to detect 80-conductor cable presence. *
	21	*
	22	* CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
	23	*
84f57fbc NS	24	* HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
	25	* controller same as the CSB6. Single channel ATA100 only.
	26	*
1da177e4 LT	27	* Documentation:
	28	* Available under NDA only. Errata info very hard to get.
	29	*
	30	*/
	31
1da177e4 LT	32	#include <linux/types.h>
	33	#include <linux/module.h>
	34	#include <linux/kernel.h>
	35	#include <linux/ioport.h>
	36	#include <linux/pci.h>
	37	#include <linux/hdreg.h>
	38	#include <linux/ide.h>
	39	#include <linux/init.h>
	40	#include <linux/delay.h>
	41
	42	#include <asm/io.h>
	43
	44	#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
	45	#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
	46
	47	/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
	48	* can overrun their FIFOs when used with the CSB5 */
	49	static const char *svwks_bad_ata100[] = {
	50	"ST320011A",
	51	"ST340016A",
	52	"ST360021A",
	53	"ST380021A",
	54	NULL
	55	};
	56
	57	static u8 svwks_revision = 0;
	58	static struct pci_dev *isa_dev;
	59
	60	static int check_in_drive_lists (ide_drive_t drive, const char *list)
	61	{
	62	while (*list)
	63	if (!strcmp(*list++, drive->id->model))
	64	return 1;
	65	return 0;
	66	}
	67
	68	static u8 svwks_ratemask (ide_drive_t *drive)
	69	{
	70	struct pci_dev *dev = HWIF(drive)->pci_dev;
6d524aed	71	u8 mode = 0;
1da177e4 LT	72
	73	if (!svwks_revision)
	74	pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
	75
84f57fbc NS	76	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
84f57fbc NS	77	return 2;
1da177e4 LT	78	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
	79	u32 reg = 0;
	80	if (isa_dev)
	81	pci_read_config_dword(isa_dev, 0x64, &reg);
	82
	83	/*
	84	* Don't enable UDMA on disk devices for the moment
	85	*/
	86	if(drive->media == ide_disk)
	87	return 0;
	88	/* Check the OSB4 DMA33 enable bit */
	89	return ((reg & 0x00004000) == 0x00004000) ? 1 : 0;
	90	} else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
	91	return 1;
	92	} else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
	93	u8 btr = 0;
	94	pci_read_config_byte(dev, 0x5A, &btr);
	95	mode = btr & 0x3;
	96	if (!eighty_ninty_three(drive))
	97	mode = min(mode, (u8)1);
	98	/* If someone decides to do UDMA133 on CSB5 the same
	99	issue will bite so be inclusive */
	100	if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
	101	mode = 2;
	102	}
	103	if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	104	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
	105	(!(PCI_FUNC(dev->devfn) & 1)))
	106	mode = 2;
	107	return mode;
	108	}
	109
	110	static u8 svwks_csb_check (struct pci_dev *dev)
	111	{
	112	switch (dev->device) {
	113	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
	114	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	115	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
84f57fbc	116	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
1da177e4 LT	117	return 1;
	118	default:
	119	break;
	120	}
	121	return 0;
	122	}
	123	static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
	124	{
f201f504 AC	125	static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
	126	static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
	127	static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	128	static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
	129	static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
1da177e4 LT	130
	131	ide_hwif_t *hwif = HWIF(drive);
	132	struct pci_dev *dev = hwif->pci_dev;
	133	u8 speed;
	134	u8 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
	135	u8 unit = (drive->select.b.unit & 0x01);
	136	u8 csb5 = svwks_csb_check(dev);
	137	u8 ultra_enable = 0, ultra_timing = 0;
	138	u8 dma_timing = 0, pio_timing = 0;
	139	u16 csb5_pio = 0;
	140
	141	if (xferspeed == 255) /* PIO auto-tuning */
	142	speed = XFER_PIO_0 + pio;
	143	else
	144	speed = ide_rate_filter(svwks_ratemask(drive), xferspeed);
	145
	146	/* If we are about to put a disk into UDMA mode we screwed up.
	147	Our code assumes we never _ever_ do this on an OSB4 */
	148
	149	if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
	150	drive->media == ide_disk && speed >= XFER_UDMA_0)
	151	BUG();
	152
	153	pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
	154	pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
	155	pci_read_config_byte(dev, (0x56\|hwif->channel), &ultra_timing);
	156	pci_read_config_word(dev, 0x4A, &csb5_pio);
	157	pci_read_config_byte(dev, 0x54, &ultra_enable);
	158
	159	/* Per Specified Design by OEM, and ASIC Architect */
	160	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	161	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
	162	if (!drive->init_speed) {
0ecdca26	163	u8 dma_stat = inb(hwif->dma_status);
1da177e4 LT	164
	165	dma_pio:
	166	if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
	167	((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
	168	drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
	169	return 0;
	170	} else if ((dma_timing) &&
	171	((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
	172	u8 dmaspeed = dma_timing;
	173
	174	dma_timing &= ~0xFF;
	175	if ((dmaspeed & 0x20) == 0x20)
	176	dmaspeed = XFER_MW_DMA_2;
	177	else if ((dmaspeed & 0x21) == 0x21)
	178	dmaspeed = XFER_MW_DMA_1;
	179	else if ((dmaspeed & 0x77) == 0x77)
	180	dmaspeed = XFER_MW_DMA_0;
	181	else
	182	goto dma_pio;
	183	drive->current_speed = drive->init_speed = dmaspeed;
	184	return 0;
	185	} else if (pio_timing) {
	186	u8 piospeed = pio_timing;
	187
	188	pio_timing &= ~0xFF;
	189	if ((piospeed & 0x20) == 0x20)
	190	piospeed = XFER_PIO_4;
	191	else if ((piospeed & 0x22) == 0x22)
	192	piospeed = XFER_PIO_3;
	193	else if ((piospeed & 0x34) == 0x34)
	194	piospeed = XFER_PIO_2;
	195	else if ((piospeed & 0x47) == 0x47)
	196	piospeed = XFER_PIO_1;
	197	else if ((piospeed & 0x5d) == 0x5d)
	198	piospeed = XFER_PIO_0;
	199	else
	200	goto oem_setup_failed;
	201	drive->current_speed = drive->init_speed = piospeed;
	202	return 0;
	203	}
	204	}
	205	}
	206
	207	oem_setup_failed:
	208
	209	pio_timing &= ~0xFF;
	210	dma_timing &= ~0xFF;
	211	ultra_timing &= ~(0x0F << (4*unit));
	212	ultra_enable &= ~(0x01 << drive->dn);
	213	csb5_pio &= ~(0x0F << (4*drive->dn));
	214
	215	switch(speed) {
	216	case XFER_PIO_4:
	217	case XFER_PIO_3:
	218	case XFER_PIO_2:
	219	case XFER_PIO_1:
	220	case XFER_PIO_0:
	221	pio_timing \|= pio_modes[speed - XFER_PIO_0];
	222	csb5_pio \|= ((speed - XFER_PIO_0) << (4*drive->dn));
	223	break;
	224
	225	case XFER_MW_DMA_2:
	226	case XFER_MW_DMA_1:
	227	case XFER_MW_DMA_0:
228	pio_timing \|= pio_modes[pio];
229	csb5_pio \|= (pio << (4*drive->dn));
230	dma_timing \|= dma_modes[speed - XFER_MW_DMA_0];
231	break;
232
233	case XFER_UDMA_5:
234	case XFER_UDMA_4:
235	case XFER_UDMA_3:
236	case XFER_UDMA_2:
237	case XFER_UDMA_1:
238	case XFER_UDMA_0:
239	pio_timing \|= pio_modes[pio];
240	csb5_pio \|= (pio << (4*drive->dn));
241	dma_timing \|= dma_modes[2];
242	ultra_timing \|= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
243	ultra_enable \|= (0x01 << drive->dn);
244	default:
245	break;
246	}
247
248	pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
249	if (csb5)
250	pci_write_config_word(dev, 0x4A, csb5_pio);
251
252	pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
253	pci_write_config_byte(dev, (0x56\|hwif->channel), ultra_timing);
254	pci_write_config_byte(dev, 0x54, ultra_enable);
255
256	return (ide_config_drive_speed(drive, speed));
257	}
258
259	static void config_chipset_for_pio (ide_drive_t *drive)
260	{
261	u16 eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
262	u16 xfer_pio = drive->id->eide_pio_modes;
263	u8 timing, speed, pio;
264
265	pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
266
267	if (xfer_pio > 4)
268	xfer_pio = 0;
269
270	if (drive->id->eide_pio_iordy > 0)
271	for (xfer_pio = 5;
272	xfer_pio>0 &&
273	drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
274	xfer_pio--);
275	else
276	xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
277	(drive->id->eide_pio_modes & 2) ? 0x04 :
278	(drive->id->eide_pio_modes & 1) ? 0x03 :
279	(drive->id->tPIO & 2) ? 0x02 :
280	(drive->id->tPIO & 1) ? 0x01 : xfer_pio;
281
282	timing = (xfer_pio >= pio) ? xfer_pio : pio;
283
284	switch(timing) {
285	case 4: speed = XFER_PIO_4;break;
286	case 3: speed = XFER_PIO_3;break;
287	case 2: speed = XFER_PIO_2;break;
288	case 1: speed = XFER_PIO_1;break;
289	default:
290	speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
291	break;
292	}
293	(void) svwks_tune_chipset(drive, speed);
294	drive->current_speed = speed;
295	}
296
297	static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
298	{
299	if(pio == 255)
300	(void) svwks_tune_chipset(drive, 255);
301	else
302	(void) svwks_tune_chipset(drive, (XFER_PIO_0 + pio));
303	}
304
305	static int config_chipset_for_dma (ide_drive_t *drive)
306	{
307	u8 speed = ide_dma_speed(drive, svwks_ratemask(drive));
308
309	if (!(speed))
310	speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
311
312	(void) svwks_tune_chipset(drive, speed);
313	return ide_dma_enable(drive);
314	}
315
316	static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
317	{
318	ide_hwif_t *hwif = HWIF(drive);
1da177e4 LT	319
	320	drive->init_speed = 0;
	321
7569e8dc BZ	322	if (ide_use_dma(drive) && config_chipset_for_dma(drive))
7569e8dc BZ	323	return hwif->ide_dma_on(drive);
1da177e4	324
7569e8dc	325	if (ide_use_fast_pio(drive)) {
1da177e4 LT	326	config_chipset_for_pio(drive);
	327	// hwif->tuneproc(drive, 5);
	328	return hwif->ide_dma_off_quietly(drive);
	329	}
	330	/* IORDY not supported */
	331	return 0;
	332	}
	333
1da177e4 LT	334	static unsigned int __devinit init_chipset_svwks (struct pci_dev dev, const char name)
	335	{
	336	unsigned int reg;
	337	u8 btr;
	338
	339	/* save revision id to determine DMA capability */
	340	pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
	341
	342	/* force Master Latency Timer value to 64 PCICLKs */
	343	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
	344
	345	/* OSB4 : South Bridge and IDE */
	346	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
970a6136	347	isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4 LT	348	PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
	349	if (isa_dev) {
	350	pci_read_config_dword(isa_dev, 0x64, &reg);
	351	reg &= ~0x00002000; /* disable 600ns interrupt mask */
	352	if(!(reg & 0x00004000))
	353	printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
	354	reg \|= 0x00004000; /* enable UDMA/33 support */
	355	pci_write_config_dword(isa_dev, 0x64, reg);
	356	}
	357	}
	358
	359	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	360	else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) \|\|
	361	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	362	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
	363
	364	/* Third Channel Test */
	365	if (!(PCI_FUNC(dev->devfn) & 1)) {
	366	struct pci_dev * findev = NULL;
	367	u32 reg4c = 0;
970a6136	368	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4 LT	369	PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
	370	if (findev) {
	371	pci_read_config_dword(findev, 0x4C, &reg4c);
	372	reg4c &= ~0x000007FF;
	373	reg4c \|= 0x00000040;
	374	reg4c \|= 0x00000020;
	375	pci_write_config_dword(findev, 0x4C, reg4c);
970a6136	376	pci_dev_put(findev);
1da177e4 LT	377	}
	378	outb_p(0x06, 0x0c00);
	379	dev->irq = inb_p(0x0c01);
1da177e4 LT	380	} else {
	381	struct pci_dev * findev = NULL;
	382	u8 reg41 = 0;
	383
970a6136	384	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4 LT	385	PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
	386	if (findev) {
	387	pci_read_config_byte(findev, 0x41, &reg41);
	388	reg41 &= ~0x40;
	389	pci_write_config_byte(findev, 0x41, reg41);
970a6136	390	pci_dev_put(findev);
1da177e4 LT	391	}
	392	/*
	393	* This is a device pin issue on CSB6.
	394	* Since there will be a future raid mode,
	395	* early versions of the chipset require the
	396	* interrupt pin to be set, and it is a compatibility
	397	* mode issue.
	398	*/
	399	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
	400	dev->irq = 0;
	401	}
	402	// pci_read_config_dword(dev, 0x40, &pioreg)
	403	// pci_write_config_dword(dev, 0x40, 0x99999999);
	404	// pci_read_config_dword(dev, 0x44, &dmareg);
	405	// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
	406	/* setup the UDMA Control register
	407	*
	408	* 1. clear bit 6 to enable DMA
	409	* 2. enable DMA modes with bits 0-1
	410	* 00 : legacy
	411	* 01 : udma2
	412	* 10 : udma2/udma4
	413	* 11 : udma2/udma4/udma5
	414	*/
	415	pci_read_config_byte(dev, 0x5A, &btr);
	416	btr &= ~0x40;
	417	if (!(PCI_FUNC(dev->devfn) & 1))
	418	btr \|= 0x2;
	419	else
	420	btr \|= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
	421	pci_write_config_byte(dev, 0x5A, btr);
	422	}
84f57fbc NS	423	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	424	else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
	425	pci_read_config_byte(dev, 0x5A, &btr);
	426	btr &= ~0x40;
	427	btr \|= 0x3;
	428	pci_write_config_byte(dev, 0x5A, btr);
	429	}
1da177e4	430
f201f504	431	return dev->irq;
1da177e4 LT	432	}
1da177e4 LT	433
bb732d7b	434	static unsigned int __devinit ata66_svwks_svwks (ide_hwif_t *hwif)
1da177e4 LT	435	{
	436	return 1;
	437	}
	438
	439	/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
	440	* of the subsystem device ID indicate presence of an 80-pin cable.
	441	* Bit 15 clear = secondary IDE channel does not have 80-pin cable.
	442	* Bit 15 set = secondary IDE channel has 80-pin cable.
	443	* Bit 14 clear = primary IDE channel does not have 80-pin cable.
	444	* Bit 14 set = primary IDE channel has 80-pin cable.
	445	*/
bb732d7b	446	static unsigned int __devinit ata66_svwks_dell (ide_hwif_t *hwif)
1da177e4 LT	447	{
	448	struct pci_dev *dev = hwif->pci_dev;
	449	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
	450	dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
	451	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE \|\|
	452	dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
	453	return ((1 << (hwif->channel + 14)) &
	454	dev->subsystem_device) ? 1 : 0;
	455	return 0;
	456	}
	457
	458	/* Sun Cobalt Alpine hardware avoids the 80-pin cable
	459	* detect issue by attaching the drives directly to the board.
	460	* This check follows the Dell precedent (how scary is that?!)
	461	*
	462	* WARNING: this only works on Alpine hardware!
	463	*/
bb732d7b	464	static unsigned int __devinit ata66_svwks_cobalt (ide_hwif_t *hwif)
1da177e4 LT	465	{
	466	struct pci_dev *dev = hwif->pci_dev;
	467	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
	468	dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
	469	dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
	470	return ((1 << (hwif->channel + 14)) &
	471	dev->subsystem_device) ? 1 : 0;
	472	return 0;
	473	}
	474
bb732d7b	475	static unsigned int __devinit ata66_svwks (ide_hwif_t *hwif)
1da177e4 LT	476	{
	477	struct pci_dev *dev = hwif->pci_dev;
	478
1da177e4 LT	479	/* Server Works */
	480	if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
	481	return ata66_svwks_svwks (hwif);
	482
	483	/* Dell PowerEdge */
	484	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
	485	return ata66_svwks_dell (hwif);
	486
	487	/* Cobalt Alpine */
	488	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
	489	return ata66_svwks_cobalt (hwif);
	490
f201f504 AC	491	/* Per Specified Design by OEM, and ASIC Architect */
	492	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	493	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
	494	return 1;
	495
1da177e4 LT	496	return 0;
	497	}
	498
1da177e4 LT	499	static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
	500	{
	501	u8 dma_stat = 0;
	502
	503	if (!hwif->irq)
	504	hwif->irq = hwif->channel ? 15 : 14;
	505
	506	hwif->tuneproc = &svwks_tune_drive;
	507	hwif->speedproc = &svwks_tune_chipset;
	508
	509	hwif->atapi_dma = 1;
	510
	511	if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
	512	hwif->ultra_mask = 0x3f;
	513
	514	hwif->mwdma_mask = 0x07;
1da177e4 LT	515
	516	hwif->autodma = 0;
	517
	518	if (!hwif->dma_base) {
	519	hwif->drives[0].autotune = 1;
	520	hwif->drives[1].autotune = 1;
	521	return;
	522	}
	523
	524	hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
946f8e4a BZ	525	if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
	526	if (!hwif->udma_four)
	527	hwif->udma_four = ata66_svwks(hwif);
	528	}
1da177e4 LT	529	if (!noautodma)
	530	hwif->autodma = 1;
	531
0ecdca26	532	dma_stat = inb(hwif->dma_status);
1da177e4 LT	533	hwif->drives[0].autodma = (dma_stat & 0x20);
	534	hwif->drives[1].autodma = (dma_stat & 0x40);
	535	hwif->drives[0].autotune = (!(dma_stat & 0x20));
	536	hwif->drives[1].autotune = (!(dma_stat & 0x40));
1da177e4 LT	537	}
1da177e4 LT	538
1da177e4 LT	539	static int __devinit init_setup_svwks (struct pci_dev dev, ide_pci_device_t d)
	540	{
	541	return ide_setup_pci_device(dev, d);
	542	}
	543
bb732d7b	544	static int __devinit init_setup_csb6 (struct pci_dev dev, ide_pci_device_t d)
1da177e4 LT	545	{
	546	if (!(PCI_FUNC(dev->devfn) & 1)) {
	547	d->bootable = NEVER_BOARD;
	548	if (dev->resource[0].start == 0x01f1)
	549	d->bootable = ON_BOARD;
	550	}
1da177e4 LT	551
	552	d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE \|\|
	553	dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
	554	(!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
	555
	556	return ide_setup_pci_device(dev, d);
	557	}
	558
	559	static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
	560	{ /* 0 */
	561	.name = "SvrWks OSB4",
	562	.init_setup = init_setup_svwks,
	563	.init_chipset = init_chipset_svwks,
	564	.init_hwif = init_hwif_svwks,
	565	.channels = 2,
	566	.autodma = AUTODMA,
	567	.bootable = ON_BOARD,
	568	},{ /* 1 */
	569	.name = "SvrWks CSB5",
	570	.init_setup = init_setup_svwks,
	571	.init_chipset = init_chipset_svwks,
	572	.init_hwif = init_hwif_svwks,
1da177e4 LT	573	.channels = 2,
	574	.autodma = AUTODMA,
	575	.bootable = ON_BOARD,
	576	},{ /* 2 */
	577	.name = "SvrWks CSB6",
	578	.init_setup = init_setup_csb6,
	579	.init_chipset = init_chipset_svwks,
	580	.init_hwif = init_hwif_svwks,
1da177e4 LT	581	.channels = 2,
	582	.autodma = AUTODMA,
	583	.bootable = ON_BOARD,
	584	},{ /* 3 */
	585	.name = "SvrWks CSB6",
	586	.init_setup = init_setup_csb6,
	587	.init_chipset = init_chipset_svwks,
	588	.init_hwif = init_hwif_svwks,
1da177e4 LT	589	.channels = 1, /* 2 */
	590	.autodma = AUTODMA,
	591	.bootable = ON_BOARD,
84f57fbc NS	592	},{ /* 4 */
	593	.name = "SvrWks HT1000",
	594	.init_setup = init_setup_svwks,
	595	.init_chipset = init_chipset_svwks,
	596	.init_hwif = init_hwif_svwks,
84f57fbc NS	597	.channels = 1, /* 2 */
	598	.autodma = AUTODMA,
	599	.bootable = ON_BOARD,
1da177e4 LT	600	}
	601	};
	602
	603	/**
	604	* svwks_init_one - called when a OSB/CSB is found
	605	* @dev: the svwks device
	606	* @id: the matching pci id
	607	*
	608	* Called when the PCI registration layer (or the IDE initialization)
	609	* finds a device matching our IDE device tables.
	610	*/
	611
	612	static int __devinit svwks_init_one(struct pci_dev dev, const struct pci_device_id id)
	613	{
	614	ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
	615
	616	return d->init_setup(dev, d);
	617	}
	618
	619	static struct pci_device_id svwks_pci_tbl[] = {
28a2a3f5 AC	620	{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	621	{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	622	{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
	623	{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
	624	{ PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1da177e4 LT	625	{ 0, },
	626	};
	627	MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
	628
	629	static struct pci_driver driver = {
	630	.name = "Serverworks_IDE",
	631	.id_table = svwks_pci_tbl,
	632	.probe = svwks_init_one,
	633	};
	634
82ab1eec	635	static int __init svwks_ide_init(void)
1da177e4 LT	636	{
	637	return ide_pci_register_driver(&driver);
	638	}
	639
	640	module_init(svwks_ide_init);
	641
	642	MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
	643	MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
	644	MODULE_LICENSE("GPL");