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1da177e4 | 1 | /* |
1c164acf | 2 | * linux/drivers/ide/pci/serverworks.c Version 0.22 Jun 27 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1998-2000 Michel Aubry | |
5 | * Copyright (C) 1998-2000 Andrzej Krzysztofowicz | |
6 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
9445de76 | 7 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
8 | * Portions copyright (c) 2001 Sun Microsystems |
9 | * | |
10 | * | |
11 | * RCC/ServerWorks IDE driver for Linux | |
12 | * | |
13 | * OSB4: `Open South Bridge' IDE Interface (fn 1) | |
14 | * supports UDMA mode 2 (33 MB/s) | |
15 | * | |
16 | * CSB5: `Champion South Bridge' IDE Interface (fn 1) | |
17 | * all revisions support UDMA mode 4 (66 MB/s) | |
18 | * revision A2.0 and up support UDMA mode 5 (100 MB/s) | |
19 | * | |
20 | * *** The CSB5 does not provide ANY register *** | |
21 | * *** to detect 80-conductor cable presence. *** | |
22 | * | |
23 | * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) | |
24 | * | |
84f57fbc NS |
25 | * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE |
26 | * controller same as the CSB6. Single channel ATA100 only. | |
27 | * | |
1da177e4 LT |
28 | * Documentation: |
29 | * Available under NDA only. Errata info very hard to get. | |
30 | * | |
31 | */ | |
32 | ||
1da177e4 LT |
33 | #include <linux/types.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/hdreg.h> | |
39 | #include <linux/ide.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/delay.h> | |
42 | ||
43 | #include <asm/io.h> | |
44 | ||
45 | #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ | |
46 | #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ | |
47 | ||
48 | /* Seagate Barracuda ATA IV Family drives in UDMA mode 5 | |
49 | * can overrun their FIFOs when used with the CSB5 */ | |
50 | static const char *svwks_bad_ata100[] = { | |
51 | "ST320011A", | |
52 | "ST340016A", | |
53 | "ST360021A", | |
54 | "ST380021A", | |
55 | NULL | |
56 | }; | |
57 | ||
1da177e4 LT |
58 | static struct pci_dev *isa_dev; |
59 | ||
60 | static int check_in_drive_lists (ide_drive_t *drive, const char **list) | |
61 | { | |
62 | while (*list) | |
63 | if (!strcmp(*list++, drive->id->model)) | |
64 | return 1; | |
65 | return 0; | |
66 | } | |
67 | ||
2d5eaa6d | 68 | static u8 svwks_udma_filter(ide_drive_t *drive) |
1da177e4 LT |
69 | { |
70 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
2d5eaa6d | 71 | u8 mask = 0; |
1da177e4 | 72 | |
84f57fbc | 73 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) |
2d5eaa6d | 74 | return 0x1f; |
1da177e4 LT |
75 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { |
76 | u32 reg = 0; | |
77 | if (isa_dev) | |
78 | pci_read_config_dword(isa_dev, 0x64, ®); | |
79 | ||
80 | /* | |
81 | * Don't enable UDMA on disk devices for the moment | |
82 | */ | |
83 | if(drive->media == ide_disk) | |
84 | return 0; | |
85 | /* Check the OSB4 DMA33 enable bit */ | |
2d5eaa6d | 86 | return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0; |
44c10138 | 87 | } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) { |
2d5eaa6d | 88 | return 0x07; |
44c10138 | 89 | } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) { |
2d5eaa6d | 90 | u8 btr = 0, mode; |
1da177e4 LT |
91 | pci_read_config_byte(dev, 0x5A, &btr); |
92 | mode = btr & 0x3; | |
2d5eaa6d | 93 | |
1da177e4 LT |
94 | /* If someone decides to do UDMA133 on CSB5 the same |
95 | issue will bite so be inclusive */ | |
96 | if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100)) | |
97 | mode = 2; | |
2d5eaa6d BZ |
98 | |
99 | switch(mode) { | |
0c824b51 | 100 | case 3: mask = 0x3f; break; |
2d5eaa6d BZ |
101 | case 2: mask = 0x1f; break; |
102 | case 1: mask = 0x07; break; | |
103 | default: mask = 0x00; break; | |
104 | } | |
1da177e4 LT |
105 | } |
106 | if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
107 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) && | |
108 | (!(PCI_FUNC(dev->devfn) & 1))) | |
2d5eaa6d BZ |
109 | mask = 0x1f; |
110 | ||
111 | return mask; | |
1da177e4 LT |
112 | } |
113 | ||
114 | static u8 svwks_csb_check (struct pci_dev *dev) | |
115 | { | |
116 | switch (dev->device) { | |
117 | case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: | |
118 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: | |
119 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: | |
84f57fbc | 120 | case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: |
1da177e4 LT |
121 | return 1; |
122 | default: | |
123 | break; | |
124 | } | |
125 | return 0; | |
126 | } | |
1880a8d7 | 127 | |
88b2b32b | 128 | static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1880a8d7 BZ |
129 | { |
130 | static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; | |
131 | static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 }; | |
132 | ||
133 | struct pci_dev *dev = drive->hwif->pci_dev; | |
134 | ||
135 | pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]); | |
136 | ||
137 | if (svwks_csb_check(dev)) { | |
138 | u16 csb_pio = 0; | |
139 | ||
140 | pci_read_config_word(dev, 0x4a, &csb_pio); | |
141 | ||
142 | csb_pio &= ~(0x0f << (4 * drive->dn)); | |
143 | csb_pio |= (pio << (4 * drive->dn)); | |
144 | ||
145 | pci_write_config_word(dev, 0x4a, csb_pio); | |
146 | } | |
147 | } | |
148 | ||
88b2b32b | 149 | static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 150 | { |
f201f504 AC |
151 | static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 }; |
152 | static const u8 dma_modes[] = { 0x77, 0x21, 0x20 }; | |
f201f504 | 153 | static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 }; |
1da177e4 LT |
154 | |
155 | ide_hwif_t *hwif = HWIF(drive); | |
156 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 | 157 | u8 unit = (drive->select.b.unit & 0x01); |
1880a8d7 BZ |
158 | |
159 | u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0; | |
160 | ||
1da177e4 LT |
161 | /* If we are about to put a disk into UDMA mode we screwed up. |
162 | Our code assumes we never _ever_ do this on an OSB4 */ | |
163 | ||
164 | if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 && | |
165 | drive->media == ide_disk && speed >= XFER_UDMA_0) | |
166 | BUG(); | |
b740d884 | 167 | |
1da177e4 | 168 | pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing); |
1da177e4 LT |
169 | pci_read_config_byte(dev, 0x54, &ultra_enable); |
170 | ||
1da177e4 LT |
171 | ultra_timing &= ~(0x0F << (4*unit)); |
172 | ultra_enable &= ~(0x01 << drive->dn); | |
1da177e4 LT |
173 | |
174 | switch(speed) { | |
1da177e4 LT |
175 | case XFER_MW_DMA_2: |
176 | case XFER_MW_DMA_1: | |
177 | case XFER_MW_DMA_0: | |
1da177e4 LT |
178 | dma_timing |= dma_modes[speed - XFER_MW_DMA_0]; |
179 | break; | |
180 | ||
181 | case XFER_UDMA_5: | |
182 | case XFER_UDMA_4: | |
183 | case XFER_UDMA_3: | |
184 | case XFER_UDMA_2: | |
185 | case XFER_UDMA_1: | |
186 | case XFER_UDMA_0: | |
1da177e4 LT |
187 | dma_timing |= dma_modes[2]; |
188 | ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit)); | |
189 | ultra_enable |= (0x01 << drive->dn); | |
190 | default: | |
191 | break; | |
192 | } | |
193 | ||
1da177e4 LT |
194 | pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing); |
195 | pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing); | |
196 | pci_write_config_byte(dev, 0x54, ultra_enable); | |
1da177e4 LT |
197 | } |
198 | ||
1da177e4 LT |
199 | static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name) |
200 | { | |
201 | unsigned int reg; | |
202 | u8 btr; | |
203 | ||
1da177e4 LT |
204 | /* force Master Latency Timer value to 64 PCICLKs */ |
205 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40); | |
206 | ||
207 | /* OSB4 : South Bridge and IDE */ | |
208 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { | |
970a6136 | 209 | isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
210 | PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); |
211 | if (isa_dev) { | |
212 | pci_read_config_dword(isa_dev, 0x64, ®); | |
213 | reg &= ~0x00002000; /* disable 600ns interrupt mask */ | |
214 | if(!(reg & 0x00004000)) | |
215 | printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name); | |
216 | reg |= 0x00004000; /* enable UDMA/33 support */ | |
217 | pci_write_config_dword(isa_dev, 0x64, reg); | |
218 | } | |
219 | } | |
220 | ||
221 | /* setup CSB5/CSB6 : South Bridge and IDE option RAID */ | |
222 | else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || | |
223 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
224 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { | |
225 | ||
226 | /* Third Channel Test */ | |
227 | if (!(PCI_FUNC(dev->devfn) & 1)) { | |
228 | struct pci_dev * findev = NULL; | |
229 | u32 reg4c = 0; | |
970a6136 | 230 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
231 | PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); |
232 | if (findev) { | |
233 | pci_read_config_dword(findev, 0x4C, ®4c); | |
234 | reg4c &= ~0x000007FF; | |
235 | reg4c |= 0x00000040; | |
236 | reg4c |= 0x00000020; | |
237 | pci_write_config_dword(findev, 0x4C, reg4c); | |
970a6136 | 238 | pci_dev_put(findev); |
1da177e4 LT |
239 | } |
240 | outb_p(0x06, 0x0c00); | |
241 | dev->irq = inb_p(0x0c01); | |
1da177e4 LT |
242 | } else { |
243 | struct pci_dev * findev = NULL; | |
244 | u8 reg41 = 0; | |
245 | ||
970a6136 | 246 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
247 | PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); |
248 | if (findev) { | |
249 | pci_read_config_byte(findev, 0x41, ®41); | |
250 | reg41 &= ~0x40; | |
251 | pci_write_config_byte(findev, 0x41, reg41); | |
970a6136 | 252 | pci_dev_put(findev); |
1da177e4 LT |
253 | } |
254 | /* | |
255 | * This is a device pin issue on CSB6. | |
256 | * Since there will be a future raid mode, | |
257 | * early versions of the chipset require the | |
258 | * interrupt pin to be set, and it is a compatibility | |
259 | * mode issue. | |
260 | */ | |
261 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
262 | dev->irq = 0; | |
263 | } | |
264 | // pci_read_config_dword(dev, 0x40, &pioreg) | |
265 | // pci_write_config_dword(dev, 0x40, 0x99999999); | |
266 | // pci_read_config_dword(dev, 0x44, &dmareg); | |
267 | // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF); | |
268 | /* setup the UDMA Control register | |
269 | * | |
270 | * 1. clear bit 6 to enable DMA | |
271 | * 2. enable DMA modes with bits 0-1 | |
272 | * 00 : legacy | |
273 | * 01 : udma2 | |
274 | * 10 : udma2/udma4 | |
275 | * 11 : udma2/udma4/udma5 | |
276 | */ | |
277 | pci_read_config_byte(dev, 0x5A, &btr); | |
278 | btr &= ~0x40; | |
279 | if (!(PCI_FUNC(dev->devfn) & 1)) | |
280 | btr |= 0x2; | |
281 | else | |
44c10138 | 282 | btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; |
1da177e4 LT |
283 | pci_write_config_byte(dev, 0x5A, btr); |
284 | } | |
84f57fbc NS |
285 | /* Setup HT1000 SouthBridge Controller - Single Channel Only */ |
286 | else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) { | |
287 | pci_read_config_byte(dev, 0x5A, &btr); | |
288 | btr &= ~0x40; | |
289 | btr |= 0x3; | |
290 | pci_write_config_byte(dev, 0x5A, btr); | |
291 | } | |
1da177e4 | 292 | |
f201f504 | 293 | return dev->irq; |
1da177e4 LT |
294 | } |
295 | ||
49521f97 | 296 | static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif) |
1da177e4 | 297 | { |
49521f97 | 298 | return ATA_CBL_PATA80; |
1da177e4 LT |
299 | } |
300 | ||
301 | /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits | |
302 | * of the subsystem device ID indicate presence of an 80-pin cable. | |
303 | * Bit 15 clear = secondary IDE channel does not have 80-pin cable. | |
304 | * Bit 15 set = secondary IDE channel has 80-pin cable. | |
305 | * Bit 14 clear = primary IDE channel does not have 80-pin cable. | |
306 | * Bit 14 set = primary IDE channel has 80-pin cable. | |
307 | */ | |
49521f97 | 308 | static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif) |
1da177e4 LT |
309 | { |
310 | struct pci_dev *dev = hwif->pci_dev; | |
311 | if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
312 | dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
313 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE || | |
314 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE)) | |
315 | return ((1 << (hwif->channel + 14)) & | |
49521f97 BZ |
316 | dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
317 | return ATA_CBL_PATA40; | |
1da177e4 LT |
318 | } |
319 | ||
320 | /* Sun Cobalt Alpine hardware avoids the 80-pin cable | |
321 | * detect issue by attaching the drives directly to the board. | |
322 | * This check follows the Dell precedent (how scary is that?!) | |
323 | * | |
324 | * WARNING: this only works on Alpine hardware! | |
325 | */ | |
49521f97 | 326 | static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif) |
1da177e4 LT |
327 | { |
328 | struct pci_dev *dev = hwif->pci_dev; | |
329 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN && | |
330 | dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
331 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) | |
332 | return ((1 << (hwif->channel + 14)) & | |
49521f97 BZ |
333 | dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
334 | return ATA_CBL_PATA40; | |
1da177e4 LT |
335 | } |
336 | ||
49521f97 | 337 | static u8 __devinit ata66_svwks(ide_hwif_t *hwif) |
1da177e4 LT |
338 | { |
339 | struct pci_dev *dev = hwif->pci_dev; | |
340 | ||
1da177e4 LT |
341 | /* Server Works */ |
342 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS) | |
343 | return ata66_svwks_svwks (hwif); | |
344 | ||
345 | /* Dell PowerEdge */ | |
346 | if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
347 | return ata66_svwks_dell (hwif); | |
348 | ||
349 | /* Cobalt Alpine */ | |
350 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN) | |
351 | return ata66_svwks_cobalt (hwif); | |
352 | ||
f201f504 AC |
353 | /* Per Specified Design by OEM, and ASIC Architect */ |
354 | if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
355 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) | |
49521f97 | 356 | return ATA_CBL_PATA80; |
f201f504 | 357 | |
49521f97 | 358 | return ATA_CBL_PATA40; |
1da177e4 LT |
359 | } |
360 | ||
1da177e4 LT |
361 | static void __devinit init_hwif_svwks (ide_hwif_t *hwif) |
362 | { | |
1da177e4 LT |
363 | if (!hwif->irq) |
364 | hwif->irq = hwif->channel ? 15 : 14; | |
365 | ||
26bcb879 | 366 | hwif->set_pio_mode = &svwks_set_pio_mode; |
88b2b32b | 367 | hwif->set_dma_mode = &svwks_set_dma_mode; |
2d5eaa6d | 368 | hwif->udma_filter = &svwks_udma_filter; |
1da177e4 | 369 | |
1da177e4 LT |
370 | if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) |
371 | hwif->ultra_mask = 0x3f; | |
372 | ||
373 | hwif->mwdma_mask = 0x07; | |
1da177e4 | 374 | |
1880a8d7 BZ |
375 | hwif->drives[0].autotune = 1; |
376 | hwif->drives[1].autotune = 1; | |
377 | ||
378 | if (!hwif->dma_base) | |
1da177e4 | 379 | return; |
1da177e4 | 380 | |
946f8e4a | 381 | if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { |
49521f97 BZ |
382 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
383 | hwif->cbl = ata66_svwks(hwif); | |
946f8e4a | 384 | } |
1da177e4 LT |
385 | } |
386 | ||
1da177e4 LT |
387 | static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d) |
388 | { | |
389 | return ide_setup_pci_device(dev, d); | |
390 | } | |
391 | ||
bb732d7b | 392 | static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d) |
1da177e4 LT |
393 | { |
394 | if (!(PCI_FUNC(dev->devfn) & 1)) { | |
1da177e4 | 395 | if (dev->resource[0].start == 0x01f1) |
7cab14a7 BZ |
396 | d->host_flags |= IDE_HFLAG_BOOTABLE; |
397 | else | |
398 | d->host_flags &= ~IDE_HFLAG_BOOTABLE; | |
1da177e4 | 399 | } |
1da177e4 | 400 | |
a5d8c5c8 BZ |
401 | if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE || |
402 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) && | |
403 | (!(PCI_FUNC(dev->devfn) & 1))) | |
404 | d->host_flags |= IDE_HFLAG_SINGLE; | |
405 | else | |
406 | d->host_flags &= ~IDE_HFLAG_SINGLE; | |
1da177e4 LT |
407 | |
408 | return ide_setup_pci_device(dev, d); | |
409 | } | |
410 | ||
411 | static ide_pci_device_t serverworks_chipsets[] __devinitdata = { | |
412 | { /* 0 */ | |
413 | .name = "SvrWks OSB4", | |
414 | .init_setup = init_setup_svwks, | |
415 | .init_chipset = init_chipset_svwks, | |
416 | .init_hwif = init_hwif_svwks, | |
7cab14a7 | 417 | .host_flags = IDE_HFLAG_BOOTABLE, |
4099d143 | 418 | .pio_mask = ATA_PIO4, |
1da177e4 LT |
419 | },{ /* 1 */ |
420 | .name = "SvrWks CSB5", | |
421 | .init_setup = init_setup_svwks, | |
422 | .init_chipset = init_chipset_svwks, | |
423 | .init_hwif = init_hwif_svwks, | |
7cab14a7 | 424 | .host_flags = IDE_HFLAG_BOOTABLE, |
4099d143 | 425 | .pio_mask = ATA_PIO4, |
1da177e4 LT |
426 | },{ /* 2 */ |
427 | .name = "SvrWks CSB6", | |
428 | .init_setup = init_setup_csb6, | |
429 | .init_chipset = init_chipset_svwks, | |
430 | .init_hwif = init_hwif_svwks, | |
7cab14a7 | 431 | .host_flags = IDE_HFLAG_BOOTABLE, |
4099d143 | 432 | .pio_mask = ATA_PIO4, |
1da177e4 LT |
433 | },{ /* 3 */ |
434 | .name = "SvrWks CSB6", | |
435 | .init_setup = init_setup_csb6, | |
436 | .init_chipset = init_chipset_svwks, | |
437 | .init_hwif = init_hwif_svwks, | |
7cab14a7 | 438 | .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_BOOTABLE, |
4099d143 | 439 | .pio_mask = ATA_PIO4, |
84f57fbc NS |
440 | },{ /* 4 */ |
441 | .name = "SvrWks HT1000", | |
442 | .init_setup = init_setup_svwks, | |
443 | .init_chipset = init_chipset_svwks, | |
444 | .init_hwif = init_hwif_svwks, | |
7cab14a7 | 445 | .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_BOOTABLE, |
4099d143 | 446 | .pio_mask = ATA_PIO4, |
1da177e4 LT |
447 | } |
448 | }; | |
449 | ||
450 | /** | |
451 | * svwks_init_one - called when a OSB/CSB is found | |
452 | * @dev: the svwks device | |
453 | * @id: the matching pci id | |
454 | * | |
455 | * Called when the PCI registration layer (or the IDE initialization) | |
456 | * finds a device matching our IDE device tables. | |
457 | */ | |
458 | ||
459 | static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
460 | { | |
461 | ide_pci_device_t *d = &serverworks_chipsets[id->driver_data]; | |
462 | ||
463 | return d->init_setup(dev, d); | |
464 | } | |
465 | ||
9cbcc5e3 BZ |
466 | static const struct pci_device_id svwks_pci_tbl[] = { |
467 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 }, | |
468 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 }, | |
469 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 }, | |
470 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 }, | |
471 | { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 }, | |
1da177e4 LT |
472 | { 0, }, |
473 | }; | |
474 | MODULE_DEVICE_TABLE(pci, svwks_pci_tbl); | |
475 | ||
476 | static struct pci_driver driver = { | |
477 | .name = "Serverworks_IDE", | |
478 | .id_table = svwks_pci_tbl, | |
479 | .probe = svwks_init_one, | |
480 | }; | |
481 | ||
82ab1eec | 482 | static int __init svwks_ide_init(void) |
1da177e4 LT |
483 | { |
484 | return ide_pci_register_driver(&driver); | |
485 | } | |
486 | ||
487 | module_init(svwks_ide_init); | |
488 | ||
489 | MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick"); | |
490 | MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE"); | |
491 | MODULE_LICENSE("GPL"); |