]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1c164acf | 2 | * linux/drivers/ide/pci/serverworks.c Version 0.22 Jun 27 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1998-2000 Michel Aubry | |
5 | * Copyright (C) 1998-2000 Andrzej Krzysztofowicz | |
6 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
9445de76 | 7 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
8 | * Portions copyright (c) 2001 Sun Microsystems |
9 | * | |
10 | * | |
11 | * RCC/ServerWorks IDE driver for Linux | |
12 | * | |
13 | * OSB4: `Open South Bridge' IDE Interface (fn 1) | |
14 | * supports UDMA mode 2 (33 MB/s) | |
15 | * | |
16 | * CSB5: `Champion South Bridge' IDE Interface (fn 1) | |
17 | * all revisions support UDMA mode 4 (66 MB/s) | |
18 | * revision A2.0 and up support UDMA mode 5 (100 MB/s) | |
19 | * | |
20 | * *** The CSB5 does not provide ANY register *** | |
21 | * *** to detect 80-conductor cable presence. *** | |
22 | * | |
23 | * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) | |
24 | * | |
84f57fbc NS |
25 | * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE |
26 | * controller same as the CSB6. Single channel ATA100 only. | |
27 | * | |
1da177e4 LT |
28 | * Documentation: |
29 | * Available under NDA only. Errata info very hard to get. | |
30 | * | |
31 | */ | |
32 | ||
1da177e4 LT |
33 | #include <linux/types.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/hdreg.h> | |
39 | #include <linux/ide.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/delay.h> | |
42 | ||
43 | #include <asm/io.h> | |
44 | ||
45 | #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ | |
46 | #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ | |
47 | ||
48 | /* Seagate Barracuda ATA IV Family drives in UDMA mode 5 | |
49 | * can overrun their FIFOs when used with the CSB5 */ | |
50 | static const char *svwks_bad_ata100[] = { | |
51 | "ST320011A", | |
52 | "ST340016A", | |
53 | "ST360021A", | |
54 | "ST380021A", | |
55 | NULL | |
56 | }; | |
57 | ||
1da177e4 LT |
58 | static struct pci_dev *isa_dev; |
59 | ||
60 | static int check_in_drive_lists (ide_drive_t *drive, const char **list) | |
61 | { | |
62 | while (*list) | |
63 | if (!strcmp(*list++, drive->id->model)) | |
64 | return 1; | |
65 | return 0; | |
66 | } | |
67 | ||
2d5eaa6d | 68 | static u8 svwks_udma_filter(ide_drive_t *drive) |
1da177e4 LT |
69 | { |
70 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
2d5eaa6d | 71 | u8 mask = 0; |
1da177e4 | 72 | |
84f57fbc | 73 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) |
2d5eaa6d | 74 | return 0x1f; |
1da177e4 LT |
75 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { |
76 | u32 reg = 0; | |
77 | if (isa_dev) | |
78 | pci_read_config_dword(isa_dev, 0x64, ®); | |
79 | ||
80 | /* | |
81 | * Don't enable UDMA on disk devices for the moment | |
82 | */ | |
83 | if(drive->media == ide_disk) | |
84 | return 0; | |
85 | /* Check the OSB4 DMA33 enable bit */ | |
2d5eaa6d | 86 | return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0; |
44c10138 | 87 | } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) { |
2d5eaa6d | 88 | return 0x07; |
44c10138 | 89 | } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) { |
2d5eaa6d | 90 | u8 btr = 0, mode; |
1da177e4 LT |
91 | pci_read_config_byte(dev, 0x5A, &btr); |
92 | mode = btr & 0x3; | |
2d5eaa6d | 93 | |
1da177e4 LT |
94 | /* If someone decides to do UDMA133 on CSB5 the same |
95 | issue will bite so be inclusive */ | |
96 | if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100)) | |
97 | mode = 2; | |
2d5eaa6d BZ |
98 | |
99 | switch(mode) { | |
100 | case 2: mask = 0x1f; break; | |
101 | case 1: mask = 0x07; break; | |
102 | default: mask = 0x00; break; | |
103 | } | |
1da177e4 LT |
104 | } |
105 | if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
106 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) && | |
107 | (!(PCI_FUNC(dev->devfn) & 1))) | |
2d5eaa6d BZ |
108 | mask = 0x1f; |
109 | ||
110 | return mask; | |
1da177e4 LT |
111 | } |
112 | ||
113 | static u8 svwks_csb_check (struct pci_dev *dev) | |
114 | { | |
115 | switch (dev->device) { | |
116 | case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: | |
117 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: | |
118 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: | |
84f57fbc | 119 | case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: |
1da177e4 LT |
120 | return 1; |
121 | default: | |
122 | break; | |
123 | } | |
124 | return 0; | |
125 | } | |
1880a8d7 | 126 | |
88b2b32b | 127 | static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1880a8d7 BZ |
128 | { |
129 | static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; | |
130 | static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 }; | |
131 | ||
132 | struct pci_dev *dev = drive->hwif->pci_dev; | |
133 | ||
134 | pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]); | |
135 | ||
136 | if (svwks_csb_check(dev)) { | |
137 | u16 csb_pio = 0; | |
138 | ||
139 | pci_read_config_word(dev, 0x4a, &csb_pio); | |
140 | ||
141 | csb_pio &= ~(0x0f << (4 * drive->dn)); | |
142 | csb_pio |= (pio << (4 * drive->dn)); | |
143 | ||
144 | pci_write_config_word(dev, 0x4a, csb_pio); | |
145 | } | |
146 | } | |
147 | ||
88b2b32b | 148 | static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 149 | { |
f201f504 AC |
150 | static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 }; |
151 | static const u8 dma_modes[] = { 0x77, 0x21, 0x20 }; | |
f201f504 | 152 | static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 }; |
1da177e4 LT |
153 | |
154 | ide_hwif_t *hwif = HWIF(drive); | |
155 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 | 156 | u8 unit = (drive->select.b.unit & 0x01); |
1880a8d7 BZ |
157 | |
158 | u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0; | |
159 | ||
1da177e4 LT |
160 | /* If we are about to put a disk into UDMA mode we screwed up. |
161 | Our code assumes we never _ever_ do this on an OSB4 */ | |
162 | ||
163 | if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 && | |
164 | drive->media == ide_disk && speed >= XFER_UDMA_0) | |
165 | BUG(); | |
b740d884 | 166 | |
1da177e4 | 167 | pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing); |
1da177e4 LT |
168 | pci_read_config_byte(dev, 0x54, &ultra_enable); |
169 | ||
1da177e4 LT |
170 | ultra_timing &= ~(0x0F << (4*unit)); |
171 | ultra_enable &= ~(0x01 << drive->dn); | |
1da177e4 LT |
172 | |
173 | switch(speed) { | |
1da177e4 LT |
174 | case XFER_MW_DMA_2: |
175 | case XFER_MW_DMA_1: | |
176 | case XFER_MW_DMA_0: | |
1da177e4 LT |
177 | dma_timing |= dma_modes[speed - XFER_MW_DMA_0]; |
178 | break; | |
179 | ||
180 | case XFER_UDMA_5: | |
181 | case XFER_UDMA_4: | |
182 | case XFER_UDMA_3: | |
183 | case XFER_UDMA_2: | |
184 | case XFER_UDMA_1: | |
185 | case XFER_UDMA_0: | |
1da177e4 LT |
186 | dma_timing |= dma_modes[2]; |
187 | ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit)); | |
188 | ultra_enable |= (0x01 << drive->dn); | |
189 | default: | |
190 | break; | |
191 | } | |
192 | ||
1da177e4 LT |
193 | pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing); |
194 | pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing); | |
195 | pci_write_config_byte(dev, 0x54, ultra_enable); | |
1da177e4 LT |
196 | } |
197 | ||
1da177e4 LT |
198 | static int svwks_config_drive_xfer_rate (ide_drive_t *drive) |
199 | { | |
1da177e4 LT |
200 | drive->init_speed = 0; |
201 | ||
bd203b57 | 202 | if (ide_tune_dma(drive)) |
3608b5d7 | 203 | return 0; |
1da177e4 | 204 | |
d8f4469d | 205 | if (ide_use_fast_pio(drive)) |
26bcb879 | 206 | ide_set_max_pio(drive); |
d8f4469d | 207 | |
3608b5d7 | 208 | return -1; |
1da177e4 LT |
209 | } |
210 | ||
1da177e4 LT |
211 | static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name) |
212 | { | |
213 | unsigned int reg; | |
214 | u8 btr; | |
215 | ||
1da177e4 LT |
216 | /* force Master Latency Timer value to 64 PCICLKs */ |
217 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40); | |
218 | ||
219 | /* OSB4 : South Bridge and IDE */ | |
220 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { | |
970a6136 | 221 | isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
222 | PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); |
223 | if (isa_dev) { | |
224 | pci_read_config_dword(isa_dev, 0x64, ®); | |
225 | reg &= ~0x00002000; /* disable 600ns interrupt mask */ | |
226 | if(!(reg & 0x00004000)) | |
227 | printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name); | |
228 | reg |= 0x00004000; /* enable UDMA/33 support */ | |
229 | pci_write_config_dword(isa_dev, 0x64, reg); | |
230 | } | |
231 | } | |
232 | ||
233 | /* setup CSB5/CSB6 : South Bridge and IDE option RAID */ | |
234 | else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || | |
235 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
236 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { | |
237 | ||
238 | /* Third Channel Test */ | |
239 | if (!(PCI_FUNC(dev->devfn) & 1)) { | |
240 | struct pci_dev * findev = NULL; | |
241 | u32 reg4c = 0; | |
970a6136 | 242 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
243 | PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); |
244 | if (findev) { | |
245 | pci_read_config_dword(findev, 0x4C, ®4c); | |
246 | reg4c &= ~0x000007FF; | |
247 | reg4c |= 0x00000040; | |
248 | reg4c |= 0x00000020; | |
249 | pci_write_config_dword(findev, 0x4C, reg4c); | |
970a6136 | 250 | pci_dev_put(findev); |
1da177e4 LT |
251 | } |
252 | outb_p(0x06, 0x0c00); | |
253 | dev->irq = inb_p(0x0c01); | |
1da177e4 LT |
254 | } else { |
255 | struct pci_dev * findev = NULL; | |
256 | u8 reg41 = 0; | |
257 | ||
970a6136 | 258 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
259 | PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); |
260 | if (findev) { | |
261 | pci_read_config_byte(findev, 0x41, ®41); | |
262 | reg41 &= ~0x40; | |
263 | pci_write_config_byte(findev, 0x41, reg41); | |
970a6136 | 264 | pci_dev_put(findev); |
1da177e4 LT |
265 | } |
266 | /* | |
267 | * This is a device pin issue on CSB6. | |
268 | * Since there will be a future raid mode, | |
269 | * early versions of the chipset require the | |
270 | * interrupt pin to be set, and it is a compatibility | |
271 | * mode issue. | |
272 | */ | |
273 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
274 | dev->irq = 0; | |
275 | } | |
276 | // pci_read_config_dword(dev, 0x40, &pioreg) | |
277 | // pci_write_config_dword(dev, 0x40, 0x99999999); | |
278 | // pci_read_config_dword(dev, 0x44, &dmareg); | |
279 | // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF); | |
280 | /* setup the UDMA Control register | |
281 | * | |
282 | * 1. clear bit 6 to enable DMA | |
283 | * 2. enable DMA modes with bits 0-1 | |
284 | * 00 : legacy | |
285 | * 01 : udma2 | |
286 | * 10 : udma2/udma4 | |
287 | * 11 : udma2/udma4/udma5 | |
288 | */ | |
289 | pci_read_config_byte(dev, 0x5A, &btr); | |
290 | btr &= ~0x40; | |
291 | if (!(PCI_FUNC(dev->devfn) & 1)) | |
292 | btr |= 0x2; | |
293 | else | |
44c10138 | 294 | btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; |
1da177e4 LT |
295 | pci_write_config_byte(dev, 0x5A, btr); |
296 | } | |
84f57fbc NS |
297 | /* Setup HT1000 SouthBridge Controller - Single Channel Only */ |
298 | else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) { | |
299 | pci_read_config_byte(dev, 0x5A, &btr); | |
300 | btr &= ~0x40; | |
301 | btr |= 0x3; | |
302 | pci_write_config_byte(dev, 0x5A, btr); | |
303 | } | |
1da177e4 | 304 | |
f201f504 | 305 | return dev->irq; |
1da177e4 LT |
306 | } |
307 | ||
49521f97 | 308 | static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif) |
1da177e4 | 309 | { |
49521f97 | 310 | return ATA_CBL_PATA80; |
1da177e4 LT |
311 | } |
312 | ||
313 | /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits | |
314 | * of the subsystem device ID indicate presence of an 80-pin cable. | |
315 | * Bit 15 clear = secondary IDE channel does not have 80-pin cable. | |
316 | * Bit 15 set = secondary IDE channel has 80-pin cable. | |
317 | * Bit 14 clear = primary IDE channel does not have 80-pin cable. | |
318 | * Bit 14 set = primary IDE channel has 80-pin cable. | |
319 | */ | |
49521f97 | 320 | static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif) |
1da177e4 LT |
321 | { |
322 | struct pci_dev *dev = hwif->pci_dev; | |
323 | if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
324 | dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
325 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE || | |
326 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE)) | |
327 | return ((1 << (hwif->channel + 14)) & | |
49521f97 BZ |
328 | dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
329 | return ATA_CBL_PATA40; | |
1da177e4 LT |
330 | } |
331 | ||
332 | /* Sun Cobalt Alpine hardware avoids the 80-pin cable | |
333 | * detect issue by attaching the drives directly to the board. | |
334 | * This check follows the Dell precedent (how scary is that?!) | |
335 | * | |
336 | * WARNING: this only works on Alpine hardware! | |
337 | */ | |
49521f97 | 338 | static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif) |
1da177e4 LT |
339 | { |
340 | struct pci_dev *dev = hwif->pci_dev; | |
341 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN && | |
342 | dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
343 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) | |
344 | return ((1 << (hwif->channel + 14)) & | |
49521f97 BZ |
345 | dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
346 | return ATA_CBL_PATA40; | |
1da177e4 LT |
347 | } |
348 | ||
49521f97 | 349 | static u8 __devinit ata66_svwks(ide_hwif_t *hwif) |
1da177e4 LT |
350 | { |
351 | struct pci_dev *dev = hwif->pci_dev; | |
352 | ||
1da177e4 LT |
353 | /* Server Works */ |
354 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS) | |
355 | return ata66_svwks_svwks (hwif); | |
356 | ||
357 | /* Dell PowerEdge */ | |
358 | if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
359 | return ata66_svwks_dell (hwif); | |
360 | ||
361 | /* Cobalt Alpine */ | |
362 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN) | |
363 | return ata66_svwks_cobalt (hwif); | |
364 | ||
f201f504 AC |
365 | /* Per Specified Design by OEM, and ASIC Architect */ |
366 | if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
367 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) | |
49521f97 | 368 | return ATA_CBL_PATA80; |
f201f504 | 369 | |
49521f97 | 370 | return ATA_CBL_PATA40; |
1da177e4 LT |
371 | } |
372 | ||
1da177e4 LT |
373 | static void __devinit init_hwif_svwks (ide_hwif_t *hwif) |
374 | { | |
1da177e4 LT |
375 | if (!hwif->irq) |
376 | hwif->irq = hwif->channel ? 15 : 14; | |
377 | ||
26bcb879 | 378 | hwif->set_pio_mode = &svwks_set_pio_mode; |
88b2b32b | 379 | hwif->set_dma_mode = &svwks_set_dma_mode; |
2d5eaa6d | 380 | hwif->udma_filter = &svwks_udma_filter; |
1da177e4 LT |
381 | |
382 | hwif->atapi_dma = 1; | |
383 | ||
384 | if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) | |
385 | hwif->ultra_mask = 0x3f; | |
386 | ||
387 | hwif->mwdma_mask = 0x07; | |
1da177e4 LT |
388 | |
389 | hwif->autodma = 0; | |
390 | ||
1880a8d7 BZ |
391 | hwif->drives[0].autotune = 1; |
392 | hwif->drives[1].autotune = 1; | |
393 | ||
394 | if (!hwif->dma_base) | |
1da177e4 | 395 | return; |
1da177e4 LT |
396 | |
397 | hwif->ide_dma_check = &svwks_config_drive_xfer_rate; | |
946f8e4a | 398 | if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { |
49521f97 BZ |
399 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
400 | hwif->cbl = ata66_svwks(hwif); | |
946f8e4a | 401 | } |
1da177e4 LT |
402 | if (!noautodma) |
403 | hwif->autodma = 1; | |
404 | ||
1c164acf | 405 | hwif->drives[0].autodma = hwif->drives[1].autodma = 1; |
1da177e4 LT |
406 | } |
407 | ||
1da177e4 LT |
408 | static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d) |
409 | { | |
410 | return ide_setup_pci_device(dev, d); | |
411 | } | |
412 | ||
bb732d7b | 413 | static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d) |
1da177e4 LT |
414 | { |
415 | if (!(PCI_FUNC(dev->devfn) & 1)) { | |
416 | d->bootable = NEVER_BOARD; | |
417 | if (dev->resource[0].start == 0x01f1) | |
418 | d->bootable = ON_BOARD; | |
419 | } | |
1da177e4 | 420 | |
a5d8c5c8 BZ |
421 | if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE || |
422 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) && | |
423 | (!(PCI_FUNC(dev->devfn) & 1))) | |
424 | d->host_flags |= IDE_HFLAG_SINGLE; | |
425 | else | |
426 | d->host_flags &= ~IDE_HFLAG_SINGLE; | |
1da177e4 LT |
427 | |
428 | return ide_setup_pci_device(dev, d); | |
429 | } | |
430 | ||
431 | static ide_pci_device_t serverworks_chipsets[] __devinitdata = { | |
432 | { /* 0 */ | |
433 | .name = "SvrWks OSB4", | |
434 | .init_setup = init_setup_svwks, | |
435 | .init_chipset = init_chipset_svwks, | |
436 | .init_hwif = init_hwif_svwks, | |
1da177e4 LT |
437 | .autodma = AUTODMA, |
438 | .bootable = ON_BOARD, | |
4099d143 | 439 | .pio_mask = ATA_PIO4, |
1da177e4 LT |
440 | },{ /* 1 */ |
441 | .name = "SvrWks CSB5", | |
442 | .init_setup = init_setup_svwks, | |
443 | .init_chipset = init_chipset_svwks, | |
444 | .init_hwif = init_hwif_svwks, | |
1da177e4 LT |
445 | .autodma = AUTODMA, |
446 | .bootable = ON_BOARD, | |
4099d143 | 447 | .pio_mask = ATA_PIO4, |
1da177e4 LT |
448 | },{ /* 2 */ |
449 | .name = "SvrWks CSB6", | |
450 | .init_setup = init_setup_csb6, | |
451 | .init_chipset = init_chipset_svwks, | |
452 | .init_hwif = init_hwif_svwks, | |
1da177e4 LT |
453 | .autodma = AUTODMA, |
454 | .bootable = ON_BOARD, | |
4099d143 | 455 | .pio_mask = ATA_PIO4, |
1da177e4 LT |
456 | },{ /* 3 */ |
457 | .name = "SvrWks CSB6", | |
458 | .init_setup = init_setup_csb6, | |
459 | .init_chipset = init_chipset_svwks, | |
460 | .init_hwif = init_hwif_svwks, | |
1da177e4 LT |
461 | .autodma = AUTODMA, |
462 | .bootable = ON_BOARD, | |
a5d8c5c8 | 463 | .host_flags = IDE_HFLAG_SINGLE, |
4099d143 | 464 | .pio_mask = ATA_PIO4, |
84f57fbc NS |
465 | },{ /* 4 */ |
466 | .name = "SvrWks HT1000", | |
467 | .init_setup = init_setup_svwks, | |
468 | .init_chipset = init_chipset_svwks, | |
469 | .init_hwif = init_hwif_svwks, | |
84f57fbc NS |
470 | .autodma = AUTODMA, |
471 | .bootable = ON_BOARD, | |
a5d8c5c8 | 472 | .host_flags = IDE_HFLAG_SINGLE, |
4099d143 | 473 | .pio_mask = ATA_PIO4, |
1da177e4 LT |
474 | } |
475 | }; | |
476 | ||
477 | /** | |
478 | * svwks_init_one - called when a OSB/CSB is found | |
479 | * @dev: the svwks device | |
480 | * @id: the matching pci id | |
481 | * | |
482 | * Called when the PCI registration layer (or the IDE initialization) | |
483 | * finds a device matching our IDE device tables. | |
484 | */ | |
485 | ||
486 | static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
487 | { | |
488 | ide_pci_device_t *d = &serverworks_chipsets[id->driver_data]; | |
489 | ||
490 | return d->init_setup(dev, d); | |
491 | } | |
492 | ||
493 | static struct pci_device_id svwks_pci_tbl[] = { | |
28a2a3f5 AC |
494 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
495 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, | |
496 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
497 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, | |
498 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, | |
1da177e4 LT |
499 | { 0, }, |
500 | }; | |
501 | MODULE_DEVICE_TABLE(pci, svwks_pci_tbl); | |
502 | ||
503 | static struct pci_driver driver = { | |
504 | .name = "Serverworks_IDE", | |
505 | .id_table = svwks_pci_tbl, | |
506 | .probe = svwks_init_one, | |
507 | }; | |
508 | ||
82ab1eec | 509 | static int __init svwks_ide_init(void) |
1da177e4 LT |
510 | { |
511 | return ide_pci_register_driver(&driver); | |
512 | } | |
513 | ||
514 | module_init(svwks_ide_init); | |
515 | ||
516 | MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick"); | |
517 | MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE"); | |
518 | MODULE_LICENSE("GPL"); |