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1da177e4 | 1 | /* |
b740d884 | 2 | * linux/drivers/ide/pci/serverworks.c Version 0.20 Jun 3 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1998-2000 Michel Aubry | |
5 | * Copyright (C) 1998-2000 Andrzej Krzysztofowicz | |
6 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
9445de76 | 7 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
8 | * Portions copyright (c) 2001 Sun Microsystems |
9 | * | |
10 | * | |
11 | * RCC/ServerWorks IDE driver for Linux | |
12 | * | |
13 | * OSB4: `Open South Bridge' IDE Interface (fn 1) | |
14 | * supports UDMA mode 2 (33 MB/s) | |
15 | * | |
16 | * CSB5: `Champion South Bridge' IDE Interface (fn 1) | |
17 | * all revisions support UDMA mode 4 (66 MB/s) | |
18 | * revision A2.0 and up support UDMA mode 5 (100 MB/s) | |
19 | * | |
20 | * *** The CSB5 does not provide ANY register *** | |
21 | * *** to detect 80-conductor cable presence. *** | |
22 | * | |
23 | * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) | |
24 | * | |
84f57fbc NS |
25 | * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE |
26 | * controller same as the CSB6. Single channel ATA100 only. | |
27 | * | |
1da177e4 LT |
28 | * Documentation: |
29 | * Available under NDA only. Errata info very hard to get. | |
30 | * | |
31 | */ | |
32 | ||
1da177e4 LT |
33 | #include <linux/types.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/hdreg.h> | |
39 | #include <linux/ide.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/delay.h> | |
42 | ||
43 | #include <asm/io.h> | |
44 | ||
45 | #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ | |
46 | #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ | |
47 | ||
48 | /* Seagate Barracuda ATA IV Family drives in UDMA mode 5 | |
49 | * can overrun their FIFOs when used with the CSB5 */ | |
50 | static const char *svwks_bad_ata100[] = { | |
51 | "ST320011A", | |
52 | "ST340016A", | |
53 | "ST360021A", | |
54 | "ST380021A", | |
55 | NULL | |
56 | }; | |
57 | ||
1da177e4 LT |
58 | static struct pci_dev *isa_dev; |
59 | ||
60 | static int check_in_drive_lists (ide_drive_t *drive, const char **list) | |
61 | { | |
62 | while (*list) | |
63 | if (!strcmp(*list++, drive->id->model)) | |
64 | return 1; | |
65 | return 0; | |
66 | } | |
67 | ||
2d5eaa6d | 68 | static u8 svwks_udma_filter(ide_drive_t *drive) |
1da177e4 LT |
69 | { |
70 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
2d5eaa6d | 71 | u8 mask = 0; |
1da177e4 | 72 | |
84f57fbc | 73 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) |
2d5eaa6d | 74 | return 0x1f; |
1da177e4 LT |
75 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { |
76 | u32 reg = 0; | |
77 | if (isa_dev) | |
78 | pci_read_config_dword(isa_dev, 0x64, ®); | |
79 | ||
80 | /* | |
81 | * Don't enable UDMA on disk devices for the moment | |
82 | */ | |
83 | if(drive->media == ide_disk) | |
84 | return 0; | |
85 | /* Check the OSB4 DMA33 enable bit */ | |
2d5eaa6d | 86 | return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0; |
44c10138 | 87 | } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) { |
2d5eaa6d | 88 | return 0x07; |
44c10138 | 89 | } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) { |
2d5eaa6d | 90 | u8 btr = 0, mode; |
1da177e4 LT |
91 | pci_read_config_byte(dev, 0x5A, &btr); |
92 | mode = btr & 0x3; | |
2d5eaa6d | 93 | |
1da177e4 LT |
94 | /* If someone decides to do UDMA133 on CSB5 the same |
95 | issue will bite so be inclusive */ | |
96 | if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100)) | |
97 | mode = 2; | |
2d5eaa6d BZ |
98 | |
99 | switch(mode) { | |
100 | case 2: mask = 0x1f; break; | |
101 | case 1: mask = 0x07; break; | |
102 | default: mask = 0x00; break; | |
103 | } | |
1da177e4 LT |
104 | } |
105 | if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
106 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) && | |
107 | (!(PCI_FUNC(dev->devfn) & 1))) | |
2d5eaa6d BZ |
108 | mask = 0x1f; |
109 | ||
110 | return mask; | |
1da177e4 LT |
111 | } |
112 | ||
113 | static u8 svwks_csb_check (struct pci_dev *dev) | |
114 | { | |
115 | switch (dev->device) { | |
116 | case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: | |
117 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: | |
118 | case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: | |
84f57fbc | 119 | case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: |
1da177e4 LT |
120 | return 1; |
121 | default: | |
122 | break; | |
123 | } | |
124 | return 0; | |
125 | } | |
126 | static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed) | |
127 | { | |
f201f504 AC |
128 | static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 }; |
129 | static const u8 dma_modes[] = { 0x77, 0x21, 0x20 }; | |
130 | static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; | |
131 | static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 }; | |
132 | static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 }; | |
1da177e4 LT |
133 | |
134 | ide_hwif_t *hwif = HWIF(drive); | |
135 | struct pci_dev *dev = hwif->pci_dev; | |
9445de76 BZ |
136 | u8 speed = ide_rate_filter(drive, xferspeed); |
137 | u8 pio = ide_get_best_pio_mode(drive, 255, 4, NULL); | |
1da177e4 LT |
138 | u8 unit = (drive->select.b.unit & 0x01); |
139 | u8 csb5 = svwks_csb_check(dev); | |
140 | u8 ultra_enable = 0, ultra_timing = 0; | |
141 | u8 dma_timing = 0, pio_timing = 0; | |
142 | u16 csb5_pio = 0; | |
143 | ||
1da177e4 LT |
144 | /* If we are about to put a disk into UDMA mode we screwed up. |
145 | Our code assumes we never _ever_ do this on an OSB4 */ | |
146 | ||
147 | if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 && | |
148 | drive->media == ide_disk && speed >= XFER_UDMA_0) | |
149 | BUG(); | |
b740d884 | 150 | |
1da177e4 LT |
151 | pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing); |
152 | pci_read_config_word(dev, 0x4A, &csb5_pio); | |
153 | pci_read_config_byte(dev, 0x54, &ultra_enable); | |
154 | ||
1da177e4 LT |
155 | ultra_timing &= ~(0x0F << (4*unit)); |
156 | ultra_enable &= ~(0x01 << drive->dn); | |
157 | csb5_pio &= ~(0x0F << (4*drive->dn)); | |
158 | ||
159 | switch(speed) { | |
160 | case XFER_PIO_4: | |
161 | case XFER_PIO_3: | |
162 | case XFER_PIO_2: | |
163 | case XFER_PIO_1: | |
164 | case XFER_PIO_0: | |
165 | pio_timing |= pio_modes[speed - XFER_PIO_0]; | |
166 | csb5_pio |= ((speed - XFER_PIO_0) << (4*drive->dn)); | |
167 | break; | |
168 | ||
169 | case XFER_MW_DMA_2: | |
170 | case XFER_MW_DMA_1: | |
171 | case XFER_MW_DMA_0: | |
9445de76 BZ |
172 | /* |
173 | * TODO: always setup PIO mode so this won't be needed | |
174 | */ | |
1da177e4 LT |
175 | pio_timing |= pio_modes[pio]; |
176 | csb5_pio |= (pio << (4*drive->dn)); | |
177 | dma_timing |= dma_modes[speed - XFER_MW_DMA_0]; | |
178 | break; | |
179 | ||
180 | case XFER_UDMA_5: | |
181 | case XFER_UDMA_4: | |
182 | case XFER_UDMA_3: | |
183 | case XFER_UDMA_2: | |
184 | case XFER_UDMA_1: | |
185 | case XFER_UDMA_0: | |
9445de76 BZ |
186 | /* |
187 | * TODO: always setup PIO mode so this won't be needed | |
188 | */ | |
1da177e4 LT |
189 | pio_timing |= pio_modes[pio]; |
190 | csb5_pio |= (pio << (4*drive->dn)); | |
191 | dma_timing |= dma_modes[2]; | |
192 | ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit)); | |
193 | ultra_enable |= (0x01 << drive->dn); | |
194 | default: | |
195 | break; | |
196 | } | |
197 | ||
198 | pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing); | |
199 | if (csb5) | |
200 | pci_write_config_word(dev, 0x4A, csb5_pio); | |
201 | ||
202 | pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing); | |
203 | pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing); | |
204 | pci_write_config_byte(dev, 0x54, ultra_enable); | |
205 | ||
206 | return (ide_config_drive_speed(drive, speed)); | |
207 | } | |
208 | ||
1da177e4 LT |
209 | static void svwks_tune_drive (ide_drive_t *drive, u8 pio) |
210 | { | |
9445de76 BZ |
211 | pio = ide_get_best_pio_mode(drive, pio, 4, NULL); |
212 | (void)svwks_tune_chipset(drive, XFER_PIO_0 + pio); | |
1da177e4 LT |
213 | } |
214 | ||
1da177e4 LT |
215 | static int svwks_config_drive_xfer_rate (ide_drive_t *drive) |
216 | { | |
1da177e4 LT |
217 | drive->init_speed = 0; |
218 | ||
bd203b57 | 219 | if (ide_tune_dma(drive)) |
3608b5d7 | 220 | return 0; |
1da177e4 | 221 | |
d8f4469d | 222 | if (ide_use_fast_pio(drive)) |
9445de76 | 223 | svwks_tune_drive(drive, 255); |
d8f4469d | 224 | |
3608b5d7 | 225 | return -1; |
1da177e4 LT |
226 | } |
227 | ||
1da177e4 LT |
228 | static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name) |
229 | { | |
230 | unsigned int reg; | |
231 | u8 btr; | |
232 | ||
1da177e4 LT |
233 | /* force Master Latency Timer value to 64 PCICLKs */ |
234 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40); | |
235 | ||
236 | /* OSB4 : South Bridge and IDE */ | |
237 | if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { | |
970a6136 | 238 | isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
239 | PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); |
240 | if (isa_dev) { | |
241 | pci_read_config_dword(isa_dev, 0x64, ®); | |
242 | reg &= ~0x00002000; /* disable 600ns interrupt mask */ | |
243 | if(!(reg & 0x00004000)) | |
244 | printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name); | |
245 | reg |= 0x00004000; /* enable UDMA/33 support */ | |
246 | pci_write_config_dword(isa_dev, 0x64, reg); | |
247 | } | |
248 | } | |
249 | ||
250 | /* setup CSB5/CSB6 : South Bridge and IDE option RAID */ | |
251 | else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || | |
252 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
253 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { | |
254 | ||
255 | /* Third Channel Test */ | |
256 | if (!(PCI_FUNC(dev->devfn) & 1)) { | |
257 | struct pci_dev * findev = NULL; | |
258 | u32 reg4c = 0; | |
970a6136 | 259 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
260 | PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); |
261 | if (findev) { | |
262 | pci_read_config_dword(findev, 0x4C, ®4c); | |
263 | reg4c &= ~0x000007FF; | |
264 | reg4c |= 0x00000040; | |
265 | reg4c |= 0x00000020; | |
266 | pci_write_config_dword(findev, 0x4C, reg4c); | |
970a6136 | 267 | pci_dev_put(findev); |
1da177e4 LT |
268 | } |
269 | outb_p(0x06, 0x0c00); | |
270 | dev->irq = inb_p(0x0c01); | |
1da177e4 LT |
271 | } else { |
272 | struct pci_dev * findev = NULL; | |
273 | u8 reg41 = 0; | |
274 | ||
970a6136 | 275 | findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
1da177e4 LT |
276 | PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); |
277 | if (findev) { | |
278 | pci_read_config_byte(findev, 0x41, ®41); | |
279 | reg41 &= ~0x40; | |
280 | pci_write_config_byte(findev, 0x41, reg41); | |
970a6136 | 281 | pci_dev_put(findev); |
1da177e4 LT |
282 | } |
283 | /* | |
284 | * This is a device pin issue on CSB6. | |
285 | * Since there will be a future raid mode, | |
286 | * early versions of the chipset require the | |
287 | * interrupt pin to be set, and it is a compatibility | |
288 | * mode issue. | |
289 | */ | |
290 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
291 | dev->irq = 0; | |
292 | } | |
293 | // pci_read_config_dword(dev, 0x40, &pioreg) | |
294 | // pci_write_config_dword(dev, 0x40, 0x99999999); | |
295 | // pci_read_config_dword(dev, 0x44, &dmareg); | |
296 | // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF); | |
297 | /* setup the UDMA Control register | |
298 | * | |
299 | * 1. clear bit 6 to enable DMA | |
300 | * 2. enable DMA modes with bits 0-1 | |
301 | * 00 : legacy | |
302 | * 01 : udma2 | |
303 | * 10 : udma2/udma4 | |
304 | * 11 : udma2/udma4/udma5 | |
305 | */ | |
306 | pci_read_config_byte(dev, 0x5A, &btr); | |
307 | btr &= ~0x40; | |
308 | if (!(PCI_FUNC(dev->devfn) & 1)) | |
309 | btr |= 0x2; | |
310 | else | |
44c10138 | 311 | btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; |
1da177e4 LT |
312 | pci_write_config_byte(dev, 0x5A, btr); |
313 | } | |
84f57fbc NS |
314 | /* Setup HT1000 SouthBridge Controller - Single Channel Only */ |
315 | else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) { | |
316 | pci_read_config_byte(dev, 0x5A, &btr); | |
317 | btr &= ~0x40; | |
318 | btr |= 0x3; | |
319 | pci_write_config_byte(dev, 0x5A, btr); | |
320 | } | |
1da177e4 | 321 | |
f201f504 | 322 | return dev->irq; |
1da177e4 LT |
323 | } |
324 | ||
49521f97 | 325 | static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif) |
1da177e4 | 326 | { |
49521f97 | 327 | return ATA_CBL_PATA80; |
1da177e4 LT |
328 | } |
329 | ||
330 | /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits | |
331 | * of the subsystem device ID indicate presence of an 80-pin cable. | |
332 | * Bit 15 clear = secondary IDE channel does not have 80-pin cable. | |
333 | * Bit 15 set = secondary IDE channel has 80-pin cable. | |
334 | * Bit 14 clear = primary IDE channel does not have 80-pin cable. | |
335 | * Bit 14 set = primary IDE channel has 80-pin cable. | |
336 | */ | |
49521f97 | 337 | static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif) |
1da177e4 LT |
338 | { |
339 | struct pci_dev *dev = hwif->pci_dev; | |
340 | if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
341 | dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
342 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE || | |
343 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE)) | |
344 | return ((1 << (hwif->channel + 14)) & | |
49521f97 BZ |
345 | dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
346 | return ATA_CBL_PATA40; | |
1da177e4 LT |
347 | } |
348 | ||
349 | /* Sun Cobalt Alpine hardware avoids the 80-pin cable | |
350 | * detect issue by attaching the drives directly to the board. | |
351 | * This check follows the Dell precedent (how scary is that?!) | |
352 | * | |
353 | * WARNING: this only works on Alpine hardware! | |
354 | */ | |
49521f97 | 355 | static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif) |
1da177e4 LT |
356 | { |
357 | struct pci_dev *dev = hwif->pci_dev; | |
358 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN && | |
359 | dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
360 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) | |
361 | return ((1 << (hwif->channel + 14)) & | |
49521f97 BZ |
362 | dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
363 | return ATA_CBL_PATA40; | |
1da177e4 LT |
364 | } |
365 | ||
49521f97 | 366 | static u8 __devinit ata66_svwks(ide_hwif_t *hwif) |
1da177e4 LT |
367 | { |
368 | struct pci_dev *dev = hwif->pci_dev; | |
369 | ||
1da177e4 LT |
370 | /* Server Works */ |
371 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS) | |
372 | return ata66_svwks_svwks (hwif); | |
373 | ||
374 | /* Dell PowerEdge */ | |
375 | if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
376 | return ata66_svwks_dell (hwif); | |
377 | ||
378 | /* Cobalt Alpine */ | |
379 | if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN) | |
380 | return ata66_svwks_cobalt (hwif); | |
381 | ||
f201f504 AC |
382 | /* Per Specified Design by OEM, and ASIC Architect */ |
383 | if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || | |
384 | (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) | |
49521f97 | 385 | return ATA_CBL_PATA80; |
f201f504 | 386 | |
49521f97 | 387 | return ATA_CBL_PATA40; |
1da177e4 LT |
388 | } |
389 | ||
1da177e4 LT |
390 | static void __devinit init_hwif_svwks (ide_hwif_t *hwif) |
391 | { | |
392 | u8 dma_stat = 0; | |
393 | ||
394 | if (!hwif->irq) | |
395 | hwif->irq = hwif->channel ? 15 : 14; | |
396 | ||
397 | hwif->tuneproc = &svwks_tune_drive; | |
398 | hwif->speedproc = &svwks_tune_chipset; | |
2d5eaa6d | 399 | hwif->udma_filter = &svwks_udma_filter; |
1da177e4 LT |
400 | |
401 | hwif->atapi_dma = 1; | |
402 | ||
403 | if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) | |
404 | hwif->ultra_mask = 0x3f; | |
405 | ||
406 | hwif->mwdma_mask = 0x07; | |
1da177e4 LT |
407 | |
408 | hwif->autodma = 0; | |
409 | ||
410 | if (!hwif->dma_base) { | |
411 | hwif->drives[0].autotune = 1; | |
412 | hwif->drives[1].autotune = 1; | |
413 | return; | |
414 | } | |
415 | ||
416 | hwif->ide_dma_check = &svwks_config_drive_xfer_rate; | |
946f8e4a | 417 | if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { |
49521f97 BZ |
418 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
419 | hwif->cbl = ata66_svwks(hwif); | |
946f8e4a | 420 | } |
1da177e4 LT |
421 | if (!noautodma) |
422 | hwif->autodma = 1; | |
423 | ||
0ecdca26 | 424 | dma_stat = inb(hwif->dma_status); |
1da177e4 LT |
425 | hwif->drives[0].autodma = (dma_stat & 0x20); |
426 | hwif->drives[1].autodma = (dma_stat & 0x40); | |
427 | hwif->drives[0].autotune = (!(dma_stat & 0x20)); | |
428 | hwif->drives[1].autotune = (!(dma_stat & 0x40)); | |
1da177e4 LT |
429 | } |
430 | ||
1da177e4 LT |
431 | static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d) |
432 | { | |
433 | return ide_setup_pci_device(dev, d); | |
434 | } | |
435 | ||
bb732d7b | 436 | static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d) |
1da177e4 LT |
437 | { |
438 | if (!(PCI_FUNC(dev->devfn) & 1)) { | |
439 | d->bootable = NEVER_BOARD; | |
440 | if (dev->resource[0].start == 0x01f1) | |
441 | d->bootable = ON_BOARD; | |
442 | } | |
1da177e4 | 443 | |
a5d8c5c8 BZ |
444 | if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE || |
445 | dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) && | |
446 | (!(PCI_FUNC(dev->devfn) & 1))) | |
447 | d->host_flags |= IDE_HFLAG_SINGLE; | |
448 | else | |
449 | d->host_flags &= ~IDE_HFLAG_SINGLE; | |
1da177e4 LT |
450 | |
451 | return ide_setup_pci_device(dev, d); | |
452 | } | |
453 | ||
454 | static ide_pci_device_t serverworks_chipsets[] __devinitdata = { | |
455 | { /* 0 */ | |
456 | .name = "SvrWks OSB4", | |
457 | .init_setup = init_setup_svwks, | |
458 | .init_chipset = init_chipset_svwks, | |
459 | .init_hwif = init_hwif_svwks, | |
1da177e4 LT |
460 | .autodma = AUTODMA, |
461 | .bootable = ON_BOARD, | |
462 | },{ /* 1 */ | |
463 | .name = "SvrWks CSB5", | |
464 | .init_setup = init_setup_svwks, | |
465 | .init_chipset = init_chipset_svwks, | |
466 | .init_hwif = init_hwif_svwks, | |
1da177e4 LT |
467 | .autodma = AUTODMA, |
468 | .bootable = ON_BOARD, | |
469 | },{ /* 2 */ | |
470 | .name = "SvrWks CSB6", | |
471 | .init_setup = init_setup_csb6, | |
472 | .init_chipset = init_chipset_svwks, | |
473 | .init_hwif = init_hwif_svwks, | |
1da177e4 LT |
474 | .autodma = AUTODMA, |
475 | .bootable = ON_BOARD, | |
476 | },{ /* 3 */ | |
477 | .name = "SvrWks CSB6", | |
478 | .init_setup = init_setup_csb6, | |
479 | .init_chipset = init_chipset_svwks, | |
480 | .init_hwif = init_hwif_svwks, | |
1da177e4 LT |
481 | .autodma = AUTODMA, |
482 | .bootable = ON_BOARD, | |
a5d8c5c8 | 483 | .host_flags = IDE_HFLAG_SINGLE, |
84f57fbc NS |
484 | },{ /* 4 */ |
485 | .name = "SvrWks HT1000", | |
486 | .init_setup = init_setup_svwks, | |
487 | .init_chipset = init_chipset_svwks, | |
488 | .init_hwif = init_hwif_svwks, | |
84f57fbc NS |
489 | .autodma = AUTODMA, |
490 | .bootable = ON_BOARD, | |
a5d8c5c8 | 491 | .host_flags = IDE_HFLAG_SINGLE, |
1da177e4 LT |
492 | } |
493 | }; | |
494 | ||
495 | /** | |
496 | * svwks_init_one - called when a OSB/CSB is found | |
497 | * @dev: the svwks device | |
498 | * @id: the matching pci id | |
499 | * | |
500 | * Called when the PCI registration layer (or the IDE initialization) | |
501 | * finds a device matching our IDE device tables. | |
502 | */ | |
503 | ||
504 | static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
505 | { | |
506 | ide_pci_device_t *d = &serverworks_chipsets[id->driver_data]; | |
507 | ||
508 | return d->init_setup(dev, d); | |
509 | } | |
510 | ||
511 | static struct pci_device_id svwks_pci_tbl[] = { | |
28a2a3f5 AC |
512 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
513 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, | |
514 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
515 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, | |
516 | { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, | |
1da177e4 LT |
517 | { 0, }, |
518 | }; | |
519 | MODULE_DEVICE_TABLE(pci, svwks_pci_tbl); | |
520 | ||
521 | static struct pci_driver driver = { | |
522 | .name = "Serverworks_IDE", | |
523 | .id_table = svwks_pci_tbl, | |
524 | .probe = svwks_init_one, | |
525 | }; | |
526 | ||
82ab1eec | 527 | static int __init svwks_ide_init(void) |
1da177e4 LT |
528 | { |
529 | return ide_pci_register_driver(&driver); | |
530 | } | |
531 | ||
532 | module_init(svwks_ide_init); | |
533 | ||
534 | MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick"); | |
535 | MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE"); | |
536 | MODULE_LICENSE("GPL"); |