]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0271fc2d | 2 | * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved. |
1da177e4 LT |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of version 2 of the GNU General Public License | |
6 | * as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it would be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public | |
13 | * License along with this program; if not, write the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
15 | * | |
1da177e4 LT |
16 | * For further information regarding this notice, see: |
17 | * | |
18 | * http://oss.sgi.com/projects/GenInfo/NoticeExplan | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/hdreg.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/timer.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/blkdev.h> | |
55c16a70 | 32 | #include <linux/scatterlist.h> |
22329b51 | 33 | #include <linux/ioc4.h> |
1da177e4 LT |
34 | #include <asm/io.h> |
35 | ||
36 | #include <linux/ide.h> | |
37 | ||
ca1997c1 BZ |
38 | #define DRV_NAME "SGIIOC4" |
39 | ||
1da177e4 LT |
40 | /* IOC4 Specific Definitions */ |
41 | #define IOC4_CMD_OFFSET 0x100 | |
42 | #define IOC4_CTRL_OFFSET 0x120 | |
43 | #define IOC4_DMA_OFFSET 0x140 | |
44 | #define IOC4_INTR_OFFSET 0x0 | |
45 | ||
46 | #define IOC4_TIMING 0x00 | |
47 | #define IOC4_DMA_PTR_L 0x01 | |
48 | #define IOC4_DMA_PTR_H 0x02 | |
49 | #define IOC4_DMA_ADDR_L 0x03 | |
50 | #define IOC4_DMA_ADDR_H 0x04 | |
51 | #define IOC4_BC_DEV 0x05 | |
52 | #define IOC4_BC_MEM 0x06 | |
53 | #define IOC4_DMA_CTRL 0x07 | |
54 | #define IOC4_DMA_END_ADDR 0x08 | |
55 | ||
56 | /* Bits in the IOC4 Control/Status Register */ | |
57 | #define IOC4_S_DMA_START 0x01 | |
58 | #define IOC4_S_DMA_STOP 0x02 | |
59 | #define IOC4_S_DMA_DIR 0x04 | |
60 | #define IOC4_S_DMA_ACTIVE 0x08 | |
61 | #define IOC4_S_DMA_ERROR 0x10 | |
62 | #define IOC4_ATA_MEMERR 0x02 | |
63 | ||
64 | /* Read/Write Directions */ | |
65 | #define IOC4_DMA_WRITE 0x04 | |
66 | #define IOC4_DMA_READ 0x00 | |
67 | ||
68 | /* Interrupt Register Offsets */ | |
69 | #define IOC4_INTR_REG 0x03 | |
70 | #define IOC4_INTR_SET 0x05 | |
71 | #define IOC4_INTR_CLEAR 0x07 | |
72 | ||
73 | #define IOC4_IDE_CACHELINE_SIZE 128 | |
74 | #define IOC4_CMD_CTL_BLK_SIZE 0x20 | |
75 | #define IOC4_SUPPORTED_FIRMWARE_REV 46 | |
76 | ||
77 | typedef struct { | |
78 | u32 timing_reg0; | |
79 | u32 timing_reg1; | |
80 | u32 low_mem_ptr; | |
81 | u32 high_mem_ptr; | |
82 | u32 low_mem_addr; | |
83 | u32 high_mem_addr; | |
84 | u32 dev_byte_count; | |
85 | u32 mem_byte_count; | |
86 | u32 status; | |
87 | } ioc4_dma_regs_t; | |
88 | ||
89 | /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */ | |
90 | /* IOC4 has only 1 IDE channel */ | |
91 | #define IOC4_PRD_BYTES 16 | |
92 | #define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES)) | |
93 | ||
94 | ||
95 | static void | |
96 | sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port, | |
97 | unsigned long ctrl_port, unsigned long irq_port) | |
98 | { | |
99 | unsigned long reg = data_port; | |
100 | int i; | |
101 | ||
102 | /* Registers are word (32 bit) aligned */ | |
103 | for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) | |
104 | hw->io_ports[i] = reg + i * 4; | |
105 | ||
106 | if (ctrl_port) | |
107 | hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; | |
108 | ||
109 | if (irq_port) | |
110 | hw->io_ports[IDE_IRQ_OFFSET] = irq_port; | |
111 | } | |
112 | ||
113 | static void | |
114 | sgiioc4_maskproc(ide_drive_t * drive, int mask) | |
115 | { | |
0ecdca26 BZ |
116 | writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), |
117 | (void __iomem *)IDE_CONTROL_REG); | |
1da177e4 LT |
118 | } |
119 | ||
120 | ||
121 | static int | |
122 | sgiioc4_checkirq(ide_hwif_t * hwif) | |
123 | { | |
0ecdca26 BZ |
124 | unsigned long intr_addr = |
125 | hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4; | |
1da177e4 | 126 | |
0ecdca26 | 127 | if ((u8)readl((void __iomem *)intr_addr) & 0x03) |
1da177e4 LT |
128 | return 1; |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
0ecdca26 | 133 | static u8 sgiioc4_INB(unsigned long); |
1da177e4 LT |
134 | |
135 | static int | |
136 | sgiioc4_clearirq(ide_drive_t * drive) | |
137 | { | |
138 | u32 intr_reg; | |
139 | ide_hwif_t *hwif = HWIF(drive); | |
140 | unsigned long other_ir = | |
141 | hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2); | |
142 | ||
143 | /* Code to check for PCI error conditions */ | |
0ecdca26 | 144 | intr_reg = readl((void __iomem *)other_ir); |
1da177e4 LT |
145 | if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */ |
146 | /* | |
0ecdca26 | 147 | * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect |
1da177e4 LT |
148 | * of clearing the interrupt. The first read should clear it |
149 | * if it is set. The second read should return a "clear" status | |
150 | * if it got cleared. If not, then spin for a bit trying to | |
151 | * clear it. | |
152 | */ | |
0ecdca26 | 153 | u8 stat = sgiioc4_INB(IDE_STATUS_REG); |
1da177e4 | 154 | int count = 0; |
0ecdca26 | 155 | stat = sgiioc4_INB(IDE_STATUS_REG); |
1da177e4 LT |
156 | while ((stat & 0x80) && (count++ < 100)) { |
157 | udelay(1); | |
0ecdca26 | 158 | stat = sgiioc4_INB(IDE_STATUS_REG); |
1da177e4 LT |
159 | } |
160 | ||
161 | if (intr_reg & 0x02) { | |
162 | /* Error when transferring DMA data on PCI bus */ | |
163 | u32 pci_err_addr_low, pci_err_addr_high, | |
164 | pci_stat_cmd_reg; | |
165 | ||
166 | pci_err_addr_low = | |
0ecdca26 | 167 | readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]); |
1da177e4 | 168 | pci_err_addr_high = |
0ecdca26 | 169 | readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4)); |
1da177e4 LT |
170 | pci_read_config_dword(hwif->pci_dev, PCI_COMMAND, |
171 | &pci_stat_cmd_reg); | |
172 | printk(KERN_ERR | |
173 | "%s(%s) : PCI Bus Error when doing DMA:" | |
174 | " status-cmd reg is 0x%x\n", | |
175 | __FUNCTION__, drive->name, pci_stat_cmd_reg); | |
176 | printk(KERN_ERR | |
177 | "%s(%s) : PCI Error Address is 0x%x%x\n", | |
178 | __FUNCTION__, drive->name, | |
179 | pci_err_addr_high, pci_err_addr_low); | |
180 | /* Clear the PCI Error indicator */ | |
181 | pci_write_config_dword(hwif->pci_dev, PCI_COMMAND, | |
182 | 0x00000146); | |
183 | } | |
184 | ||
185 | /* Clear the Interrupt, Error bits on the IOC4 */ | |
0ecdca26 | 186 | writel(0x03, (void __iomem *)other_ir); |
1da177e4 | 187 | |
0ecdca26 | 188 | intr_reg = readl((void __iomem *)other_ir); |
1da177e4 LT |
189 | } |
190 | ||
191 | return intr_reg & 3; | |
192 | } | |
193 | ||
194 | static void sgiioc4_ide_dma_start(ide_drive_t * drive) | |
195 | { | |
196 | ide_hwif_t *hwif = HWIF(drive); | |
0ecdca26 BZ |
197 | unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4; |
198 | unsigned int reg = readl((void __iomem *)ioc4_dma_addr); | |
1da177e4 LT |
199 | unsigned int temp_reg = reg | IOC4_S_DMA_START; |
200 | ||
0ecdca26 | 201 | writel(temp_reg, (void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
202 | } |
203 | ||
204 | static u32 | |
205 | sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base) | |
206 | { | |
0ecdca26 | 207 | unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4; |
1da177e4 LT |
208 | u32 ioc4_dma; |
209 | int count; | |
210 | ||
211 | count = 0; | |
0ecdca26 | 212 | ioc4_dma = readl((void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
213 | while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) { |
214 | udelay(1); | |
0ecdca26 | 215 | ioc4_dma = readl((void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
216 | } |
217 | return ioc4_dma; | |
218 | } | |
219 | ||
220 | /* Stops the IOC4 DMA Engine */ | |
221 | static int | |
222 | sgiioc4_ide_dma_end(ide_drive_t * drive) | |
223 | { | |
224 | u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0; | |
225 | ide_hwif_t *hwif = HWIF(drive); | |
0ecdca26 | 226 | unsigned long dma_base = hwif->dma_base; |
1da177e4 | 227 | int dma_stat = 0; |
3f63c5e8 | 228 | unsigned long *ending_dma = ide_get_hwifdata(hwif); |
1da177e4 | 229 | |
0ecdca26 | 230 | writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4)); |
1da177e4 LT |
231 | |
232 | ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); | |
233 | ||
234 | if (ioc4_dma & IOC4_S_DMA_STOP) { | |
235 | printk(KERN_ERR | |
236 | "%s(%s): IOC4 DMA STOP bit is still 1 :" | |
237 | "ioc4_dma_reg 0x%x\n", | |
238 | __FUNCTION__, drive->name, ioc4_dma); | |
239 | dma_stat = 1; | |
240 | } | |
241 | ||
242 | /* | |
243 | * The IOC4 will DMA 1's to the ending dma area to indicate that | |
244 | * previous data DMA is complete. This is necessary because of relaxed | |
245 | * ordering between register reads and DMA writes on the Altix. | |
246 | */ | |
247 | while ((cnt++ < 200) && (!valid)) { | |
248 | for (num = 0; num < 16; num++) { | |
249 | if (ending_dma[num]) { | |
250 | valid = 1; | |
251 | break; | |
252 | } | |
253 | } | |
254 | udelay(1); | |
255 | } | |
256 | if (!valid) { | |
257 | printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__, | |
258 | drive->name); | |
259 | dma_stat = 1; | |
260 | } | |
261 | ||
0ecdca26 BZ |
262 | bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4)); |
263 | bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4)); | |
1da177e4 LT |
264 | |
265 | if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) { | |
266 | if (bc_dev > bc_mem + 8) { | |
267 | printk(KERN_ERR | |
268 | "%s(%s): WARNING!! byte_count_dev %d " | |
269 | "!= byte_count_mem %d\n", | |
270 | __FUNCTION__, drive->name, bc_dev, bc_mem); | |
271 | } | |
272 | } | |
273 | ||
274 | drive->waiting_for_dma = 0; | |
275 | ide_destroy_dmatable(drive); | |
276 | ||
277 | return dma_stat; | |
278 | } | |
279 | ||
1da177e4 LT |
280 | static int |
281 | sgiioc4_ide_dma_on(ide_drive_t * drive) | |
282 | { | |
283 | drive->using_dma = 1; | |
284 | ||
ccf35289 | 285 | return 0; |
1da177e4 LT |
286 | } |
287 | ||
7469aaf6 | 288 | static void sgiioc4_dma_off_quietly(ide_drive_t *drive) |
1da177e4 LT |
289 | { |
290 | drive->using_dma = 0; | |
291 | ||
7469aaf6 | 292 | drive->hwif->dma_host_off(drive); |
1da177e4 LT |
293 | } |
294 | ||
88b2b32b | 295 | static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed) |
ca1997c1 | 296 | { |
ca1997c1 BZ |
297 | } |
298 | ||
1da177e4 LT |
299 | /* returns 1 if dma irq issued, 0 otherwise */ |
300 | static int | |
301 | sgiioc4_ide_dma_test_irq(ide_drive_t * drive) | |
302 | { | |
303 | return sgiioc4_checkirq(HWIF(drive)); | |
304 | } | |
305 | ||
ccf35289 | 306 | static void sgiioc4_dma_host_on(ide_drive_t * drive) |
1da177e4 | 307 | { |
1da177e4 LT |
308 | } |
309 | ||
7469aaf6 | 310 | static void sgiioc4_dma_host_off(ide_drive_t * drive) |
1da177e4 LT |
311 | { |
312 | sgiioc4_clearirq(drive); | |
1da177e4 LT |
313 | } |
314 | ||
1da177e4 LT |
315 | static void |
316 | sgiioc4_resetproc(ide_drive_t * drive) | |
317 | { | |
318 | sgiioc4_ide_dma_end(drive); | |
319 | sgiioc4_clearirq(drive); | |
320 | } | |
321 | ||
841d2a9b SS |
322 | static void |
323 | sgiioc4_dma_lost_irq(ide_drive_t * drive) | |
324 | { | |
325 | sgiioc4_resetproc(drive); | |
326 | ||
327 | ide_dma_lost_irq(drive); | |
328 | } | |
329 | ||
1da177e4 LT |
330 | static u8 |
331 | sgiioc4_INB(unsigned long port) | |
332 | { | |
a835fa79 | 333 | u8 reg = (u8) readb((void __iomem *) port); |
1da177e4 LT |
334 | |
335 | if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */ | |
336 | if (reg & 0x51) { /* Not busy...check for interrupt */ | |
337 | unsigned long other_ir = port - 0x110; | |
a835fa79 | 338 | unsigned int intr_reg = (u32) readl((void __iomem *) other_ir); |
1da177e4 LT |
339 | |
340 | /* Clear the Interrupt, Error bits on the IOC4 */ | |
341 | if (intr_reg & 0x03) { | |
a835fa79 JH |
342 | writel(0x03, (void __iomem *) other_ir); |
343 | intr_reg = (u32) readl((void __iomem *) other_ir); | |
1da177e4 LT |
344 | } |
345 | } | |
346 | } | |
347 | ||
348 | return reg; | |
349 | } | |
350 | ||
351 | /* Creates a dma map for the scatter-gather list entries */ | |
ca1997c1 | 352 | static int __devinit |
1da177e4 LT |
353 | ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base) |
354 | { | |
1678df37 | 355 | void __iomem *virt_dma_base; |
1da177e4 | 356 | int num_ports = sizeof (ioc4_dma_regs_t); |
3f63c5e8 | 357 | void *pad; |
1da177e4 LT |
358 | |
359 | printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name, | |
360 | dma_base, dma_base + num_ports - 1); | |
361 | ||
1678df37 | 362 | if (!request_mem_region(dma_base, num_ports, hwif->name)) { |
1da177e4 LT |
363 | printk(KERN_ERR |
364 | "%s(%s) -- ERROR, Addresses 0x%p to 0x%p " | |
365 | "ALREADY in use\n", | |
366 | __FUNCTION__, hwif->name, (void *) dma_base, | |
367 | (void *) dma_base + num_ports - 1); | |
ca1997c1 | 368 | return -1; |
1da177e4 LT |
369 | } |
370 | ||
1678df37 JK |
371 | virt_dma_base = ioremap(dma_base, num_ports); |
372 | if (virt_dma_base == NULL) { | |
373 | printk(KERN_ERR | |
374 | "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n", | |
375 | __FUNCTION__, hwif->name, dma_base, dma_base + num_ports - 1); | |
376 | goto dma_remap_failure; | |
377 | } | |
378 | hwif->dma_base = (unsigned long) virt_dma_base; | |
379 | ||
1da177e4 LT |
380 | hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev, |
381 | IOC4_PRD_ENTRIES * IOC4_PRD_BYTES, | |
382 | &hwif->dmatable_dma); | |
383 | ||
384 | if (!hwif->dmatable_cpu) | |
1678df37 | 385 | goto dma_pci_alloc_failure; |
1da177e4 LT |
386 | |
387 | hwif->sg_max_nents = IOC4_PRD_ENTRIES; | |
388 | ||
3f63c5e8 SS |
389 | pad = pci_alloc_consistent(hwif->pci_dev, IOC4_IDE_CACHELINE_SIZE, |
390 | (dma_addr_t *) &(hwif->dma_status)); | |
1da177e4 | 391 | |
3f63c5e8 SS |
392 | if (pad) { |
393 | ide_set_hwifdata(hwif, pad); | |
ca1997c1 | 394 | return 0; |
3f63c5e8 | 395 | } |
1da177e4 | 396 | |
1da177e4 LT |
397 | pci_free_consistent(hwif->pci_dev, |
398 | IOC4_PRD_ENTRIES * IOC4_PRD_BYTES, | |
399 | hwif->dmatable_cpu, hwif->dmatable_dma); | |
400 | printk(KERN_INFO | |
401 | "%s() -- Error! Unable to allocate DMA Maps for drive %s\n", | |
402 | __FUNCTION__, hwif->name); | |
403 | printk(KERN_INFO | |
404 | "Changing from DMA to PIO mode for Drive %s\n", hwif->name); | |
405 | ||
1678df37 JK |
406 | dma_pci_alloc_failure: |
407 | iounmap(virt_dma_base); | |
408 | ||
409 | dma_remap_failure: | |
410 | release_mem_region(dma_base, num_ports); | |
411 | ||
ca1997c1 | 412 | return -1; |
1da177e4 LT |
413 | } |
414 | ||
415 | /* Initializes the IOC4 DMA Engine */ | |
416 | static void | |
417 | sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive) | |
418 | { | |
419 | u32 ioc4_dma; | |
420 | ide_hwif_t *hwif = HWIF(drive); | |
0ecdca26 BZ |
421 | unsigned long dma_base = hwif->dma_base; |
422 | unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4; | |
1da177e4 LT |
423 | u32 dma_addr, ending_dma_addr; |
424 | ||
0ecdca26 | 425 | ioc4_dma = readl((void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
426 | |
427 | if (ioc4_dma & IOC4_S_DMA_ACTIVE) { | |
428 | printk(KERN_WARNING | |
429 | "%s(%s):Warning!! DMA from previous transfer was still active\n", | |
430 | __FUNCTION__, drive->name); | |
0ecdca26 | 431 | writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
432 | ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); |
433 | ||
434 | if (ioc4_dma & IOC4_S_DMA_STOP) | |
435 | printk(KERN_ERR | |
436 | "%s(%s) : IOC4 Dma STOP bit is still 1\n", | |
437 | __FUNCTION__, drive->name); | |
438 | } | |
439 | ||
0ecdca26 | 440 | ioc4_dma = readl((void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
441 | if (ioc4_dma & IOC4_S_DMA_ERROR) { |
442 | printk(KERN_WARNING | |
443 | "%s(%s) : Warning!! - DMA Error during Previous" | |
444 | " transfer | status 0x%x\n", | |
445 | __FUNCTION__, drive->name, ioc4_dma); | |
0ecdca26 | 446 | writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
447 | ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); |
448 | ||
449 | if (ioc4_dma & IOC4_S_DMA_STOP) | |
450 | printk(KERN_ERR | |
451 | "%s(%s) : IOC4 DMA STOP bit is still 1\n", | |
452 | __FUNCTION__, drive->name); | |
453 | } | |
454 | ||
455 | /* Address of the Scatter Gather List */ | |
456 | dma_addr = cpu_to_le32(hwif->dmatable_dma); | |
0ecdca26 | 457 | writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4)); |
1da177e4 LT |
458 | |
459 | /* Address of the Ending DMA */ | |
3f63c5e8 | 460 | memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE); |
1da177e4 | 461 | ending_dma_addr = cpu_to_le32(hwif->dma_status); |
0ecdca26 | 462 | writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4)); |
1da177e4 | 463 | |
0ecdca26 | 464 | writel(dma_direction, (void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
465 | drive->waiting_for_dma = 1; |
466 | } | |
467 | ||
468 | /* IOC4 Scatter Gather list Format */ | |
469 | /* 128 Bit entries to support 64 bit addresses in the future */ | |
470 | /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */ | |
471 | /* --------------------------------------------------------------------- */ | |
472 | /* | Upper 32 bits - Zero | Lower 32 bits- address | */ | |
473 | /* --------------------------------------------------------------------- */ | |
474 | /* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */ | |
475 | /* --------------------------------------------------------------------- */ | |
476 | /* Creates the scatter gather list, DMA Table */ | |
477 | static unsigned int | |
478 | sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir) | |
479 | { | |
480 | ide_hwif_t *hwif = HWIF(drive); | |
481 | unsigned int *table = hwif->dmatable_cpu; | |
482 | unsigned int count = 0, i = 1; | |
483 | struct scatterlist *sg; | |
484 | ||
485 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
486 | ||
487 | if (!i) | |
488 | return 0; /* sglist of length Zero */ | |
489 | ||
490 | sg = hwif->sg_table; | |
491 | while (i && sg_dma_len(sg)) { | |
492 | dma_addr_t cur_addr; | |
493 | int cur_len; | |
494 | cur_addr = sg_dma_address(sg); | |
495 | cur_len = sg_dma_len(sg); | |
496 | ||
497 | while (cur_len) { | |
498 | if (count++ >= IOC4_PRD_ENTRIES) { | |
499 | printk(KERN_WARNING | |
500 | "%s: DMA table too small\n", | |
501 | drive->name); | |
502 | goto use_pio_instead; | |
503 | } else { | |
0271fc2d | 504 | u32 bcount = |
1da177e4 LT |
505 | 0x10000 - (cur_addr & 0xffff); |
506 | ||
507 | if (bcount > cur_len) | |
508 | bcount = cur_len; | |
509 | ||
510 | /* put the addr, length in | |
511 | * the IOC4 dma-table format */ | |
512 | *table = 0x0; | |
513 | table++; | |
514 | *table = cpu_to_be32(cur_addr); | |
515 | table++; | |
516 | *table = 0x0; | |
517 | table++; | |
518 | ||
0271fc2d | 519 | *table = cpu_to_be32(bcount); |
1da177e4 LT |
520 | table++; |
521 | ||
522 | cur_addr += bcount; | |
523 | cur_len -= bcount; | |
524 | } | |
525 | } | |
526 | ||
55c16a70 | 527 | sg = sg_next(sg); |
1da177e4 LT |
528 | i--; |
529 | } | |
530 | ||
531 | if (count) { | |
532 | table--; | |
533 | *table |= cpu_to_be32(0x80000000); | |
534 | return count; | |
535 | } | |
536 | ||
537 | use_pio_instead: | |
538 | pci_unmap_sg(hwif->pci_dev, hwif->sg_table, hwif->sg_nents, | |
539 | hwif->sg_dma_direction); | |
540 | ||
541 | return 0; /* revert to PIO for this request */ | |
542 | } | |
543 | ||
544 | static int sgiioc4_ide_dma_setup(ide_drive_t *drive) | |
545 | { | |
546 | struct request *rq = HWGROUP(drive)->rq; | |
547 | unsigned int count = 0; | |
548 | int ddir; | |
549 | ||
550 | if (rq_data_dir(rq)) | |
551 | ddir = PCI_DMA_TODEVICE; | |
552 | else | |
553 | ddir = PCI_DMA_FROMDEVICE; | |
554 | ||
555 | if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) { | |
556 | /* try PIO instead of DMA */ | |
557 | ide_map_sg(drive, rq); | |
558 | return 1; | |
559 | } | |
560 | ||
561 | if (rq_data_dir(rq)) | |
562 | /* Writes TO the IOC4 FROM Main Memory */ | |
563 | ddir = IOC4_DMA_READ; | |
564 | else | |
565 | /* Writes FROM the IOC4 TO Main Memory */ | |
566 | ddir = IOC4_DMA_WRITE; | |
567 | ||
568 | sgiioc4_configure_for_dma(ddir, drive); | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
573 | static void __devinit | |
574 | ide_init_sgiioc4(ide_hwif_t * hwif) | |
575 | { | |
2ad1e558 | 576 | hwif->mmio = 1; |
4099d143 | 577 | hwif->pio_mask = 0x00; |
26bcb879 | 578 | hwif->set_pio_mode = NULL; /* Sets timing for PIO mode */ |
88b2b32b | 579 | hwif->set_dma_mode = &sgiioc4_set_dma_mode; |
1da177e4 LT |
580 | hwif->selectproc = NULL;/* Use the default routine to select drive */ |
581 | hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */ | |
582 | hwif->pre_reset = NULL; /* No HBA specific pre_set needed */ | |
583 | hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine, | |
584 | clear interrupts */ | |
585 | hwif->intrproc = NULL; /* Enable or Disable interrupt from drive */ | |
586 | hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */ | |
587 | hwif->quirkproc = NULL; | |
588 | hwif->busproc = NULL; | |
589 | ||
b9d9e61a BZ |
590 | hwif->INB = &sgiioc4_INB; |
591 | ||
592 | if (hwif->dma_base == 0) | |
593 | return; | |
594 | ||
5f8b6c34 | 595 | hwif->mwdma_mask = ATA_MWDMA2_ONLY; |
b9d9e61a | 596 | |
1da177e4 LT |
597 | hwif->dma_setup = &sgiioc4_ide_dma_setup; |
598 | hwif->dma_start = &sgiioc4_ide_dma_start; | |
599 | hwif->ide_dma_end = &sgiioc4_ide_dma_end; | |
1da177e4 | 600 | hwif->ide_dma_on = &sgiioc4_ide_dma_on; |
7469aaf6 | 601 | hwif->dma_off_quietly = &sgiioc4_dma_off_quietly; |
1da177e4 | 602 | hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq; |
ccf35289 | 603 | hwif->dma_host_on = &sgiioc4_dma_host_on; |
7469aaf6 | 604 | hwif->dma_host_off = &sgiioc4_dma_host_off; |
841d2a9b | 605 | hwif->dma_lost_irq = &sgiioc4_dma_lost_irq; |
c283f5db | 606 | hwif->dma_timeout = &ide_dma_timeout; |
1da177e4 LT |
607 | } |
608 | ||
609 | static int __devinit | |
ca1997c1 | 610 | sgiioc4_ide_setup_pci_device(struct pci_dev *dev) |
1da177e4 | 611 | { |
1678df37 JK |
612 | unsigned long cmd_base, dma_base, irqport; |
613 | unsigned long bar0, cmd_phys_base, ctl; | |
614 | void __iomem *virt_base; | |
1da177e4 LT |
615 | ide_hwif_t *hwif; |
616 | int h; | |
8447d9d5 | 617 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 | 618 | |
deb5e5c0 JH |
619 | /* |
620 | * Find an empty HWIF; if none available, return -ENOMEM. | |
621 | */ | |
1da177e4 LT |
622 | for (h = 0; h < MAX_HWIFS; ++h) { |
623 | hwif = &ide_hwifs[h]; | |
1da177e4 LT |
624 | if (hwif->chipset == ide_unknown) |
625 | break; | |
626 | } | |
deb5e5c0 | 627 | if (h == MAX_HWIFS) { |
ca1997c1 BZ |
628 | printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", |
629 | DRV_NAME); | |
deb5e5c0 JH |
630 | return -ENOMEM; |
631 | } | |
1da177e4 LT |
632 | |
633 | /* Get the CmdBlk and CtrlBlk Base Registers */ | |
1678df37 JK |
634 | bar0 = pci_resource_start(dev, 0); |
635 | virt_base = ioremap(bar0, pci_resource_len(dev, 0)); | |
636 | if (virt_base == NULL) { | |
637 | printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n", | |
ca1997c1 | 638 | DRV_NAME, bar0); |
1678df37 JK |
639 | return -ENOMEM; |
640 | } | |
641 | cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET; | |
642 | ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET; | |
643 | irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET; | |
1da177e4 LT |
644 | dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET; |
645 | ||
1678df37 JK |
646 | cmd_phys_base = bar0 + IOC4_CMD_OFFSET; |
647 | if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE, | |
648 | hwif->name)) { | |
1da177e4 | 649 | printk(KERN_ERR |
1678df37 | 650 | "%s : %s -- ERROR, Addresses " |
1da177e4 | 651 | "0x%p to 0x%p ALREADY in use\n", |
1678df37 JK |
652 | __FUNCTION__, hwif->name, (void *) cmd_phys_base, |
653 | (void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE); | |
1da177e4 LT |
654 | return -ENOMEM; |
655 | } | |
656 | ||
1678df37 | 657 | if (hwif->io_ports[IDE_DATA_OFFSET] != cmd_base) { |
9239b333 BZ |
658 | hw_regs_t hw; |
659 | ||
1da177e4 | 660 | /* Initialize the IO registers */ |
9239b333 BZ |
661 | memset(&hw, 0, sizeof(hw)); |
662 | sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport); | |
663 | memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports)); | |
1da177e4 LT |
664 | hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET]; |
665 | } | |
666 | ||
667 | hwif->irq = dev->irq; | |
668 | hwif->chipset = ide_pci; | |
669 | hwif->pci_dev = dev; | |
670 | hwif->channel = 0; /* Single Channel chip */ | |
1da177e4 LT |
671 | hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */ |
672 | ||
1678df37 JK |
673 | /* The IOC4 uses MMIO rather than Port IO. */ |
674 | default_hwif_mmiops(hwif); | |
675 | ||
1da177e4 | 676 | /* Initializing chipset IRQ Registers */ |
0ecdca26 | 677 | writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4)); |
1da177e4 | 678 | |
9ff6f72f | 679 | if (dma_base == 0 || ide_dma_sgiioc4(hwif, dma_base)) |
1da177e4 | 680 | printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n", |
ca1997c1 | 681 | hwif->name, DRV_NAME); |
1da177e4 | 682 | |
b9d9e61a BZ |
683 | ide_init_sgiioc4(hwif); |
684 | ||
8447d9d5 | 685 | idx[0] = hwif->index; |
1da177e4 | 686 | |
8447d9d5 BZ |
687 | if (ide_device_add(idx)) |
688 | return -EIO; | |
1da177e4 LT |
689 | |
690 | return 0; | |
691 | } | |
692 | ||
693 | static unsigned int __devinit | |
ca1997c1 | 694 | pci_init_sgiioc4(struct pci_dev *dev) |
1da177e4 | 695 | { |
1da177e4 LT |
696 | int ret; |
697 | ||
1da177e4 | 698 | printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n", |
fc212bb1 BZ |
699 | DRV_NAME, pci_name(dev), dev->revision); |
700 | ||
701 | if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) { | |
1da177e4 | 702 | printk(KERN_ERR "Skipping %s IDE controller in slot %s: " |
ca1997c1 BZ |
703 | "firmware is obsolete - please upgrade to " |
704 | "revision46 or higher\n", | |
705 | DRV_NAME, pci_name(dev)); | |
1da177e4 LT |
706 | ret = -EAGAIN; |
707 | goto out; | |
708 | } | |
ca1997c1 | 709 | ret = sgiioc4_ide_setup_pci_device(dev); |
1da177e4 LT |
710 | out: |
711 | return ret; | |
712 | } | |
713 | ||
1da177e4 | 714 | int |
22329b51 | 715 | ioc4_ide_attach_one(struct ioc4_driver_data *idd) |
1da177e4 | 716 | { |
f5befceb BC |
717 | /* PCI-RT does not bring out IDE connection. |
718 | * Do not attach to this particular IOC4. | |
719 | */ | |
720 | if (idd->idd_variant == IOC4_VARIANT_PCI_RT) | |
721 | return 0; | |
722 | ||
ca1997c1 | 723 | return pci_init_sgiioc4(idd->idd_pdev); |
1da177e4 LT |
724 | } |
725 | ||
22329b51 BC |
726 | static struct ioc4_submodule ioc4_ide_submodule = { |
727 | .is_name = "IOC4_ide", | |
728 | .is_owner = THIS_MODULE, | |
729 | .is_probe = ioc4_ide_attach_one, | |
730 | /* .is_remove = ioc4_ide_remove_one, */ | |
731 | }; | |
732 | ||
82ab1eec | 733 | static int __init ioc4_ide_init(void) |
22329b51 BC |
734 | { |
735 | return ioc4_register_submodule(&ioc4_ide_submodule); | |
736 | } | |
737 | ||
59f14800 | 738 | late_initcall(ioc4_ide_init); /* Call only after IDE init is done */ |
1da177e4 | 739 | |
a835fa79 | 740 | MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon"); |
1da177e4 LT |
741 | MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card"); |
742 | MODULE_LICENSE("GPL"); |