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1da177e4 | 1 | /* |
8e60d376 | 2 | * linux/drivers/ide/pci/siimage.c Version 1.12 Mar 10 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> | |
5 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
075cb655 | 6 | * Copyright (C) 2007 MontaVista Software, Inc. |
1da177e4 LT |
7 | * |
8 | * May be copied or modified under the terms of the GNU General Public License | |
9 | * | |
bf4c796d JG |
10 | * Documentation for CMD680: |
11 | * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 | |
12 | * | |
13 | * Documentation for SiI 3112: | |
14 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
15 | * | |
16 | * Errata and other documentation only available under NDA. | |
1da177e4 LT |
17 | * |
18 | * | |
19 | * FAQ Items: | |
20 | * If you are using Marvell SATA-IDE adapters with Maxtor drives | |
21 | * ensure the system is set up for ATA100/UDMA5 not UDMA6. | |
22 | * | |
23 | * If you are using WD drives with SATA bridges you must set the | |
24 | * drive to "Single". "Master" will hang | |
25 | * | |
26 | * If you have strange problems with nVidia chipset systems please | |
27 | * see the SI support documentation and update your system BIOS | |
28 | * if neccessary | |
8693d3e4 AC |
29 | * |
30 | * The Dell DRAC4 has some interesting features including effectively hot | |
31 | * unplugging/replugging the virtual CD interface when the DRAC is reset. | |
32 | * This often causes drivers/ide/siimage to panic but is ok with the rather | |
33 | * smarter code in libata. | |
1da177e4 LT |
34 | */ |
35 | ||
1da177e4 LT |
36 | #include <linux/types.h> |
37 | #include <linux/module.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/hdreg.h> | |
41 | #include <linux/ide.h> | |
42 | #include <linux/init.h> | |
43 | ||
44 | #include <asm/io.h> | |
45 | ||
1da177e4 LT |
46 | /** |
47 | * pdev_is_sata - check if device is SATA | |
48 | * @pdev: PCI device to check | |
49 | * | |
50 | * Returns true if this is a SATA controller | |
51 | */ | |
52 | ||
53 | static int pdev_is_sata(struct pci_dev *pdev) | |
54 | { | |
55 | switch(pdev->device) | |
56 | { | |
57 | case PCI_DEVICE_ID_SII_3112: | |
58 | case PCI_DEVICE_ID_SII_1210SA: | |
59 | return 1; | |
60 | case PCI_DEVICE_ID_SII_680: | |
61 | return 0; | |
62 | } | |
63 | BUG(); | |
64 | return 0; | |
65 | } | |
66 | ||
67 | /** | |
68 | * is_sata - check if hwif is SATA | |
69 | * @hwif: interface to check | |
70 | * | |
71 | * Returns true if this is a SATA controller | |
72 | */ | |
73 | ||
74 | static inline int is_sata(ide_hwif_t *hwif) | |
75 | { | |
76 | return pdev_is_sata(hwif->pci_dev); | |
77 | } | |
78 | ||
79 | /** | |
80 | * siimage_selreg - return register base | |
81 | * @hwif: interface | |
82 | * @r: config offset | |
83 | * | |
84 | * Turn a config register offset into the right address in either | |
85 | * PCI space or MMIO space to access the control register in question | |
86 | * Thankfully this is a configuration operation so isnt performance | |
87 | * criticial. | |
88 | */ | |
89 | ||
90 | static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) | |
91 | { | |
92 | unsigned long base = (unsigned long)hwif->hwif_data; | |
93 | base += 0xA0 + r; | |
94 | if(hwif->mmio) | |
95 | base += (hwif->channel << 6); | |
96 | else | |
97 | base += (hwif->channel << 4); | |
98 | return base; | |
99 | } | |
100 | ||
101 | /** | |
102 | * siimage_seldev - return register base | |
103 | * @hwif: interface | |
104 | * @r: config offset | |
105 | * | |
106 | * Turn a config register offset into the right address in either | |
107 | * PCI space or MMIO space to access the control register in question | |
108 | * including accounting for the unit shift. | |
109 | */ | |
110 | ||
111 | static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) | |
112 | { | |
113 | ide_hwif_t *hwif = HWIF(drive); | |
114 | unsigned long base = (unsigned long)hwif->hwif_data; | |
115 | base += 0xA0 + r; | |
116 | if(hwif->mmio) | |
117 | base += (hwif->channel << 6); | |
118 | else | |
119 | base += (hwif->channel << 4); | |
120 | base |= drive->select.b.unit << drive->select.b.unit; | |
121 | return base; | |
122 | } | |
123 | ||
124 | /** | |
125 | * siimage_ratemask - Compute available modes | |
126 | * @drive: IDE drive | |
127 | * | |
128 | * Compute the available speeds for the devices on the interface. | |
129 | * For the CMD680 this depends on the clocking mode (scsc), for the | |
130 | * SI3312 SATA controller life is a bit simpler. Enforce UDMA33 | |
131 | * as a limit if there is no 80pin cable present. | |
132 | */ | |
133 | ||
134 | static byte siimage_ratemask (ide_drive_t *drive) | |
135 | { | |
136 | ide_hwif_t *hwif = HWIF(drive); | |
137 | u8 mode = 0, scsc = 0; | |
138 | unsigned long base = (unsigned long) hwif->hwif_data; | |
139 | ||
140 | if (hwif->mmio) | |
141 | scsc = hwif->INB(base + 0x4A); | |
142 | else | |
143 | pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc); | |
144 | ||
145 | if(is_sata(hwif)) | |
146 | { | |
147 | if(strstr(drive->id->model, "Maxtor")) | |
148 | return 3; | |
149 | return 4; | |
150 | } | |
151 | ||
152 | if ((scsc & 0x30) == 0x10) /* 133 */ | |
153 | mode = 4; | |
154 | else if ((scsc & 0x30) == 0x20) /* 2xPCI */ | |
155 | mode = 4; | |
156 | else if ((scsc & 0x30) == 0x00) /* 100 */ | |
157 | mode = 3; | |
158 | else /* Disabled ? */ | |
159 | BUG(); | |
160 | ||
161 | if (!eighty_ninty_three(drive)) | |
162 | mode = min(mode, (u8)1); | |
163 | return mode; | |
164 | } | |
165 | ||
166 | /** | |
167 | * siimage_taskfile_timing - turn timing data to a mode | |
168 | * @hwif: interface to query | |
169 | * | |
170 | * Read the timing data for the interface and return the | |
171 | * mode that is being used. | |
172 | */ | |
173 | ||
174 | static byte siimage_taskfile_timing (ide_hwif_t *hwif) | |
175 | { | |
176 | u16 timing = 0x328a; | |
177 | unsigned long addr = siimage_selreg(hwif, 2); | |
178 | ||
179 | if (hwif->mmio) | |
180 | timing = hwif->INW(addr); | |
181 | else | |
182 | pci_read_config_word(hwif->pci_dev, addr, &timing); | |
183 | ||
184 | switch (timing) { | |
185 | case 0x10c1: return 4; | |
186 | case 0x10c3: return 3; | |
187 | case 0x1104: | |
188 | case 0x1281: return 2; | |
189 | case 0x2283: return 1; | |
190 | case 0x328a: | |
191 | default: return 0; | |
192 | } | |
193 | } | |
194 | ||
195 | /** | |
196 | * simmage_tuneproc - tune a drive | |
197 | * @drive: drive to tune | |
198 | * @mode_wanted: the target operating mode | |
199 | * | |
200 | * Load the timing settings for this device mode into the | |
201 | * controller. If we are in PIO mode 3 or 4 turn on IORDY | |
202 | * monitoring (bit 9). The TF timing is bits 31:16 | |
203 | */ | |
204 | ||
205 | static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted) | |
206 | { | |
207 | ide_hwif_t *hwif = HWIF(drive); | |
208 | u32 speedt = 0; | |
209 | u16 speedp = 0; | |
210 | unsigned long addr = siimage_seldev(drive, 0x04); | |
211 | unsigned long tfaddr = siimage_selreg(hwif, 0x02); | |
212 | ||
213 | /* cheat for now and use the docs */ | |
075cb655 SS |
214 | switch (mode_wanted) { |
215 | case 4: | |
216 | speedp = 0x10c1; | |
217 | speedt = 0x10c1; | |
218 | break; | |
219 | case 3: | |
220 | speedp = 0x10c3; | |
221 | speedt = 0x10c3; | |
222 | break; | |
223 | case 2: | |
224 | speedp = 0x1104; | |
225 | speedt = 0x1281; | |
226 | break; | |
227 | case 1: | |
228 | speedp = 0x2283; | |
229 | speedt = 0x2283; | |
230 | break; | |
231 | case 0: | |
232 | default: | |
233 | speedp = 0x328a; | |
234 | speedt = 0x328a; | |
235 | break; | |
1da177e4 | 236 | } |
075cb655 SS |
237 | |
238 | if (hwif->mmio) { | |
239 | hwif->OUTW(speedp, addr); | |
240 | hwif->OUTW(speedt, tfaddr); | |
1da177e4 LT |
241 | /* Now set up IORDY */ |
242 | if(mode_wanted == 3 || mode_wanted == 4) | |
243 | hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2); | |
244 | else | |
245 | hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2); | |
075cb655 | 246 | } else { |
1da177e4 LT |
247 | pci_write_config_word(hwif->pci_dev, addr, speedp); |
248 | pci_write_config_word(hwif->pci_dev, tfaddr, speedt); | |
249 | pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp); | |
250 | speedp &= ~0x200; | |
251 | /* Set IORDY for mode 3 or 4 */ | |
252 | if(mode_wanted == 3 || mode_wanted == 4) | |
253 | speedp |= 0x200; | |
254 | pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp); | |
255 | } | |
256 | } | |
257 | ||
258 | /** | |
259 | * config_siimage_chipset_for_pio - set drive timings | |
260 | * @drive: drive to tune | |
261 | * @speed we want | |
262 | * | |
263 | * Compute the best pio mode we can for a given device. Also honour | |
264 | * the timings for the driver when dealing with mixed devices. Some | |
265 | * of this is ugly but its all wrapped up here | |
266 | * | |
267 | * The SI680 can also do VDMA - we need to start using that | |
268 | * | |
269 | * FIXME: we use the BIOS channel timings to avoid driving the task | |
270 | * files too fast at the disk. We need to compute the master/slave | |
271 | * drive PIO mode properly so that we can up the speed on a hotplug | |
272 | * system. | |
273 | */ | |
274 | ||
275 | static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed) | |
276 | { | |
277 | u8 channel_timings = siimage_taskfile_timing(HWIF(drive)); | |
278 | u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL); | |
279 | ||
280 | /* WARNING PIO timing mess is going to happen b/w devices, argh */ | |
281 | if ((channel_timings != set_pio) && (set_pio > channel_timings)) | |
282 | set_pio = channel_timings; | |
283 | ||
284 | siimage_tuneproc(drive, set_pio); | |
285 | speed = XFER_PIO_0 + set_pio; | |
286 | if (set_speed) | |
287 | (void) ide_config_drive_speed(drive, speed); | |
288 | } | |
289 | ||
1da177e4 LT |
290 | /** |
291 | * siimage_tune_chipset - set controller timings | |
292 | * @drive: Drive to set up | |
293 | * @xferspeed: speed we want to achieve | |
294 | * | |
295 | * Tune the SII chipset for the desired mode. If we can't achieve | |
296 | * the desired mode then tune for a lower one, but ultimately | |
297 | * make the thing work. | |
298 | */ | |
299 | ||
300 | static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed) | |
301 | { | |
302 | u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; | |
303 | u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
304 | u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
305 | ||
306 | ide_hwif_t *hwif = HWIF(drive); | |
307 | u16 ultra = 0, multi = 0; | |
308 | u8 mode = 0, unit = drive->select.b.unit; | |
309 | u8 speed = ide_rate_filter(siimage_ratemask(drive), xferspeed); | |
310 | unsigned long base = (unsigned long)hwif->hwif_data; | |
311 | u8 scsc = 0, addr_mask = ((hwif->channel) ? | |
312 | ((hwif->mmio) ? 0xF4 : 0x84) : | |
313 | ((hwif->mmio) ? 0xB4 : 0x80)); | |
314 | ||
315 | unsigned long ma = siimage_seldev(drive, 0x08); | |
316 | unsigned long ua = siimage_seldev(drive, 0x0C); | |
317 | ||
318 | if (hwif->mmio) { | |
319 | scsc = hwif->INB(base + 0x4A); | |
320 | mode = hwif->INB(base + addr_mask); | |
321 | multi = hwif->INW(ma); | |
322 | ultra = hwif->INW(ua); | |
323 | } else { | |
324 | pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc); | |
325 | pci_read_config_byte(hwif->pci_dev, addr_mask, &mode); | |
326 | pci_read_config_word(hwif->pci_dev, ma, &multi); | |
327 | pci_read_config_word(hwif->pci_dev, ua, &ultra); | |
328 | } | |
329 | ||
330 | mode &= ~((unit) ? 0x30 : 0x03); | |
331 | ultra &= ~0x3F; | |
332 | scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; | |
333 | ||
334 | scsc = is_sata(hwif) ? 1 : scsc; | |
335 | ||
336 | switch(speed) { | |
337 | case XFER_PIO_4: | |
338 | case XFER_PIO_3: | |
339 | case XFER_PIO_2: | |
340 | case XFER_PIO_1: | |
341 | case XFER_PIO_0: | |
342 | siimage_tuneproc(drive, (speed - XFER_PIO_0)); | |
343 | mode |= ((unit) ? 0x10 : 0x01); | |
344 | break; | |
345 | case XFER_MW_DMA_2: | |
346 | case XFER_MW_DMA_1: | |
347 | case XFER_MW_DMA_0: | |
348 | multi = dma[speed - XFER_MW_DMA_0]; | |
349 | mode |= ((unit) ? 0x20 : 0x02); | |
350 | config_siimage_chipset_for_pio(drive, 0); | |
351 | break; | |
352 | case XFER_UDMA_6: | |
353 | case XFER_UDMA_5: | |
354 | case XFER_UDMA_4: | |
355 | case XFER_UDMA_3: | |
356 | case XFER_UDMA_2: | |
357 | case XFER_UDMA_1: | |
358 | case XFER_UDMA_0: | |
359 | multi = dma[2]; | |
360 | ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) : | |
361 | (ultra5[speed - XFER_UDMA_0])); | |
362 | mode |= ((unit) ? 0x30 : 0x03); | |
363 | config_siimage_chipset_for_pio(drive, 0); | |
364 | break; | |
365 | default: | |
366 | return 1; | |
367 | } | |
368 | ||
369 | if (hwif->mmio) { | |
370 | hwif->OUTB(mode, base + addr_mask); | |
371 | hwif->OUTW(multi, ma); | |
372 | hwif->OUTW(ultra, ua); | |
373 | } else { | |
374 | pci_write_config_byte(hwif->pci_dev, addr_mask, mode); | |
375 | pci_write_config_word(hwif->pci_dev, ma, multi); | |
376 | pci_write_config_word(hwif->pci_dev, ua, ultra); | |
377 | } | |
378 | return (ide_config_drive_speed(drive, speed)); | |
379 | } | |
380 | ||
381 | /** | |
382 | * config_chipset_for_dma - configure for DMA | |
383 | * @drive: drive to configure | |
384 | * | |
385 | * Called by the IDE layer when it wants the timings set up. | |
386 | * For the CMD680 we also need to set up the PIO timings and | |
387 | * enable DMA. | |
388 | */ | |
389 | ||
390 | static int config_chipset_for_dma (ide_drive_t *drive) | |
391 | { | |
392 | u8 speed = ide_dma_speed(drive, siimage_ratemask(drive)); | |
393 | ||
1da177e4 LT |
394 | if (!speed) |
395 | return 0; | |
396 | ||
056a697b | 397 | if (siimage_tune_chipset(drive, speed)) |
1da177e4 LT |
398 | return 0; |
399 | ||
1da177e4 LT |
400 | return ide_dma_enable(drive); |
401 | } | |
402 | ||
403 | /** | |
404 | * siimage_configure_drive_for_dma - set up for DMA transfers | |
405 | * @drive: drive we are going to set up | |
406 | * | |
407 | * Set up the drive for DMA, tune the controller and drive as | |
408 | * required. If the drive isn't suitable for DMA or we hit | |
409 | * other problems then we will drop down to PIO and set up | |
410 | * PIO appropriately | |
411 | */ | |
412 | ||
413 | static int siimage_config_drive_for_dma (ide_drive_t *drive) | |
414 | { | |
7569e8dc | 415 | if (ide_use_dma(drive) && config_chipset_for_dma(drive)) |
3608b5d7 | 416 | return 0; |
1da177e4 | 417 | |
d8f4469d | 418 | if (ide_use_fast_pio(drive)) |
8e60d376 | 419 | config_siimage_chipset_for_pio(drive, 1); |
d8f4469d | 420 | |
3608b5d7 | 421 | return -1; |
1da177e4 LT |
422 | } |
423 | ||
424 | /* returns 1 if dma irq issued, 0 otherwise */ | |
425 | static int siimage_io_ide_dma_test_irq (ide_drive_t *drive) | |
426 | { | |
427 | ide_hwif_t *hwif = HWIF(drive); | |
428 | u8 dma_altstat = 0; | |
429 | unsigned long addr = siimage_selreg(hwif, 1); | |
430 | ||
431 | /* return 1 if INTR asserted */ | |
432 | if ((hwif->INB(hwif->dma_status) & 4) == 4) | |
433 | return 1; | |
434 | ||
435 | /* return 1 if Device INTR asserted */ | |
436 | pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat); | |
437 | if (dma_altstat & 8) | |
438 | return 0; //return 1; | |
439 | return 0; | |
440 | } | |
441 | ||
1da177e4 LT |
442 | /** |
443 | * siimage_mmio_ide_dma_test_irq - check we caused an IRQ | |
444 | * @drive: drive we are testing | |
445 | * | |
446 | * Check if we caused an IDE DMA interrupt. We may also have caused | |
447 | * SATA status interrupts, if so we clean them up and continue. | |
448 | */ | |
449 | ||
450 | static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive) | |
451 | { | |
452 | ide_hwif_t *hwif = HWIF(drive); | |
453 | unsigned long base = (unsigned long)hwif->hwif_data; | |
454 | unsigned long addr = siimage_selreg(hwif, 0x1); | |
455 | ||
456 | if (SATA_ERROR_REG) { | |
0ecdca26 | 457 | u32 ext_stat = readl((void __iomem *)(base + 0x10)); |
1da177e4 LT |
458 | u8 watchdog = 0; |
459 | if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { | |
0ecdca26 BZ |
460 | u32 sata_error = readl((void __iomem *)SATA_ERROR_REG); |
461 | writel(sata_error, (void __iomem *)SATA_ERROR_REG); | |
1da177e4 | 462 | watchdog = (sata_error & 0x00680000) ? 1 : 0; |
1da177e4 LT |
463 | printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
464 | "watchdog = %d, %s\n", | |
465 | drive->name, sata_error, watchdog, | |
466 | __FUNCTION__); | |
1da177e4 LT |
467 | |
468 | } else { | |
469 | watchdog = (ext_stat & 0x8000) ? 1 : 0; | |
470 | } | |
471 | ext_stat >>= 16; | |
472 | ||
473 | if (!(ext_stat & 0x0404) && !watchdog) | |
474 | return 0; | |
475 | } | |
476 | ||
477 | /* return 1 if INTR asserted */ | |
0ecdca26 | 478 | if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04) |
1da177e4 LT |
479 | return 1; |
480 | ||
481 | /* return 1 if Device INTR asserted */ | |
0ecdca26 | 482 | if ((readb((void __iomem *)addr) & 8) == 8) |
1da177e4 LT |
483 | return 0; //return 1; |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | /** | |
489 | * siimage_busproc - bus isolation ioctl | |
490 | * @drive: drive to isolate/restore | |
491 | * @state: bus state to set | |
492 | * | |
493 | * Used by the SII3112 to handle bus isolation. As this is a | |
494 | * SATA controller the work required is quite limited, we | |
495 | * just have to clean up the statistics | |
496 | */ | |
497 | ||
498 | static int siimage_busproc (ide_drive_t * drive, int state) | |
499 | { | |
500 | ide_hwif_t *hwif = HWIF(drive); | |
501 | u32 stat_config = 0; | |
502 | unsigned long addr = siimage_selreg(hwif, 0); | |
503 | ||
0ecdca26 BZ |
504 | if (hwif->mmio) |
505 | stat_config = readl((void __iomem *)addr); | |
506 | else | |
1da177e4 LT |
507 | pci_read_config_dword(hwif->pci_dev, addr, &stat_config); |
508 | ||
509 | switch (state) { | |
510 | case BUSSTATE_ON: | |
511 | hwif->drives[0].failures = 0; | |
512 | hwif->drives[1].failures = 0; | |
513 | break; | |
514 | case BUSSTATE_OFF: | |
515 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
516 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
517 | break; | |
518 | case BUSSTATE_TRISTATE: | |
519 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
520 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
521 | break; | |
522 | default: | |
523 | return -EINVAL; | |
524 | } | |
525 | hwif->bus_state = state; | |
526 | return 0; | |
527 | } | |
528 | ||
529 | /** | |
530 | * siimage_reset_poll - wait for sata reset | |
531 | * @drive: drive we are resetting | |
532 | * | |
533 | * Poll the SATA phy and see whether it has come back from the dead | |
534 | * yet. | |
535 | */ | |
536 | ||
537 | static int siimage_reset_poll (ide_drive_t *drive) | |
538 | { | |
539 | if (SATA_STATUS_REG) { | |
540 | ide_hwif_t *hwif = HWIF(drive); | |
541 | ||
0ecdca26 BZ |
542 | /* SATA_STATUS_REG is valid only when in MMIO mode */ |
543 | if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) { | |
1da177e4 | 544 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", |
0ecdca26 | 545 | hwif->name, readl((void __iomem *)SATA_STATUS_REG)); |
1da177e4 LT |
546 | HWGROUP(drive)->polling = 0; |
547 | return ide_started; | |
548 | } | |
549 | return 0; | |
550 | } else { | |
551 | return 0; | |
552 | } | |
553 | } | |
554 | ||
555 | /** | |
556 | * siimage_pre_reset - reset hook | |
557 | * @drive: IDE device being reset | |
558 | * | |
559 | * For the SATA devices we need to handle recalibration/geometry | |
560 | * differently | |
561 | */ | |
562 | ||
563 | static void siimage_pre_reset (ide_drive_t *drive) | |
564 | { | |
565 | if (drive->media != ide_disk) | |
566 | return; | |
567 | ||
568 | if (is_sata(HWIF(drive))) | |
569 | { | |
570 | drive->special.b.set_geometry = 0; | |
571 | drive->special.b.recalibrate = 0; | |
572 | } | |
573 | } | |
574 | ||
575 | /** | |
576 | * siimage_reset - reset a device on an siimage controller | |
577 | * @drive: drive to reset | |
578 | * | |
579 | * Perform a controller level reset fo the device. For | |
580 | * SATA we must also check the PHY. | |
581 | */ | |
582 | ||
583 | static void siimage_reset (ide_drive_t *drive) | |
584 | { | |
585 | ide_hwif_t *hwif = HWIF(drive); | |
586 | u8 reset = 0; | |
587 | unsigned long addr = siimage_selreg(hwif, 0); | |
588 | ||
589 | if (hwif->mmio) { | |
590 | reset = hwif->INB(addr); | |
591 | hwif->OUTB((reset|0x03), addr); | |
592 | /* FIXME:posting */ | |
593 | udelay(25); | |
594 | hwif->OUTB(reset, addr); | |
595 | (void) hwif->INB(addr); | |
596 | } else { | |
597 | pci_read_config_byte(hwif->pci_dev, addr, &reset); | |
598 | pci_write_config_byte(hwif->pci_dev, addr, reset|0x03); | |
599 | udelay(25); | |
600 | pci_write_config_byte(hwif->pci_dev, addr, reset); | |
601 | pci_read_config_byte(hwif->pci_dev, addr, &reset); | |
602 | } | |
603 | ||
604 | if (SATA_STATUS_REG) { | |
0ecdca26 BZ |
605 | /* SATA_STATUS_REG is valid only when in MMIO mode */ |
606 | u32 sata_stat = readl((void __iomem *)SATA_STATUS_REG); | |
1da177e4 LT |
607 | printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n", |
608 | hwif->name, sata_stat, __FUNCTION__); | |
609 | if (!(sata_stat)) { | |
610 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", | |
611 | hwif->name, sata_stat); | |
612 | drive->failures++; | |
613 | } | |
614 | } | |
615 | ||
616 | } | |
617 | ||
618 | /** | |
619 | * proc_reports_siimage - add siimage controller to proc | |
620 | * @dev: PCI device | |
621 | * @clocking: SCSC value | |
622 | * @name: controller name | |
623 | * | |
624 | * Report the clocking mode of the controller and add it to | |
625 | * the /proc interface layer | |
626 | */ | |
627 | ||
628 | static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name) | |
629 | { | |
630 | if (!pdev_is_sata(dev)) { | |
631 | printk(KERN_INFO "%s: BASE CLOCK ", name); | |
632 | clocking &= 0x03; | |
633 | switch (clocking) { | |
634 | case 0x03: printk("DISABLED!\n"); break; | |
635 | case 0x02: printk("== 2X PCI\n"); break; | |
636 | case 0x01: printk("== 133\n"); break; | |
637 | case 0x00: printk("== 100\n"); break; | |
638 | } | |
639 | } | |
640 | } | |
641 | ||
642 | /** | |
643 | * setup_mmio_siimage - switch an SI controller into MMIO | |
644 | * @dev: PCI device we are configuring | |
645 | * @name: device name | |
646 | * | |
647 | * Attempt to put the device into mmio mode. There are some slight | |
648 | * complications here with certain systems where the mmio bar isnt | |
649 | * mapped so we have to be sure we can fall back to I/O. | |
650 | */ | |
651 | ||
652 | static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name) | |
653 | { | |
654 | unsigned long bar5 = pci_resource_start(dev, 5); | |
655 | unsigned long barsize = pci_resource_len(dev, 5); | |
656 | u8 tmpbyte = 0; | |
657 | void __iomem *ioaddr; | |
d868dd19 | 658 | u32 tmp, irq_mask; |
1da177e4 LT |
659 | |
660 | /* | |
661 | * Drop back to PIO if we can't map the mmio. Some | |
662 | * systems seem to get terminally confused in the PCI | |
663 | * spaces. | |
664 | */ | |
665 | ||
666 | if(!request_mem_region(bar5, barsize, name)) | |
667 | { | |
668 | printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n"); | |
669 | return 0; | |
670 | } | |
671 | ||
672 | ioaddr = ioremap(bar5, barsize); | |
673 | ||
674 | if (ioaddr == NULL) | |
675 | { | |
676 | release_mem_region(bar5, barsize); | |
677 | return 0; | |
678 | } | |
679 | ||
680 | pci_set_master(dev); | |
681 | pci_set_drvdata(dev, (void *) ioaddr); | |
682 | ||
683 | if (pdev_is_sata(dev)) { | |
d868dd19 JL |
684 | /* make sure IDE0/1 interrupts are not masked */ |
685 | irq_mask = (1 << 22) | (1 << 23); | |
686 | tmp = readl(ioaddr + 0x48); | |
687 | if (tmp & irq_mask) { | |
688 | tmp &= ~irq_mask; | |
689 | writel(tmp, ioaddr + 0x48); | |
690 | readl(ioaddr + 0x48); /* flush */ | |
691 | } | |
1da177e4 LT |
692 | writel(0, ioaddr + 0x148); |
693 | writel(0, ioaddr + 0x1C8); | |
694 | } | |
695 | ||
696 | writeb(0, ioaddr + 0xB4); | |
697 | writeb(0, ioaddr + 0xF4); | |
698 | tmpbyte = readb(ioaddr + 0x4A); | |
699 | ||
700 | switch(tmpbyte & 0x30) { | |
701 | case 0x00: | |
702 | /* In 100 MHz clocking, try and switch to 133 */ | |
703 | writeb(tmpbyte|0x10, ioaddr + 0x4A); | |
704 | break; | |
705 | case 0x10: | |
706 | /* On 133Mhz clocking */ | |
707 | break; | |
708 | case 0x20: | |
709 | /* On PCIx2 clocking */ | |
710 | break; | |
711 | case 0x30: | |
712 | /* Clocking is disabled */ | |
713 | /* 133 clock attempt to force it on */ | |
714 | writeb(tmpbyte & ~0x20, ioaddr + 0x4A); | |
715 | break; | |
716 | } | |
717 | ||
718 | writeb( 0x72, ioaddr + 0xA1); | |
719 | writew( 0x328A, ioaddr + 0xA2); | |
720 | writel(0x62DD62DD, ioaddr + 0xA4); | |
721 | writel(0x43924392, ioaddr + 0xA8); | |
722 | writel(0x40094009, ioaddr + 0xAC); | |
723 | writeb( 0x72, ioaddr + 0xE1); | |
724 | writew( 0x328A, ioaddr + 0xE2); | |
725 | writel(0x62DD62DD, ioaddr + 0xE4); | |
726 | writel(0x43924392, ioaddr + 0xE8); | |
727 | writel(0x40094009, ioaddr + 0xEC); | |
728 | ||
729 | if (pdev_is_sata(dev)) { | |
730 | writel(0xFFFF0000, ioaddr + 0x108); | |
731 | writel(0xFFFF0000, ioaddr + 0x188); | |
732 | writel(0x00680000, ioaddr + 0x148); | |
733 | writel(0x00680000, ioaddr + 0x1C8); | |
734 | } | |
735 | ||
736 | tmpbyte = readb(ioaddr + 0x4A); | |
737 | ||
738 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
739 | return 1; | |
740 | } | |
741 | ||
742 | /** | |
743 | * init_chipset_siimage - set up an SI device | |
744 | * @dev: PCI device | |
745 | * @name: device name | |
746 | * | |
747 | * Perform the initial PCI set up for this device. Attempt to switch | |
748 | * to 133MHz clocking if the system isn't already set up to do it. | |
749 | */ | |
750 | ||
751 | static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name) | |
752 | { | |
753 | u32 class_rev = 0; | |
754 | u8 tmpbyte = 0; | |
755 | u8 BA5_EN = 0; | |
756 | ||
757 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
758 | class_rev &= 0xff; | |
759 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255); | |
760 | ||
761 | pci_read_config_byte(dev, 0x8A, &BA5_EN); | |
762 | if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) { | |
763 | if (setup_mmio_siimage(dev, name)) { | |
764 | return 0; | |
765 | } | |
766 | } | |
767 | ||
768 | pci_write_config_byte(dev, 0x80, 0x00); | |
769 | pci_write_config_byte(dev, 0x84, 0x00); | |
770 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
771 | switch(tmpbyte & 0x30) { | |
772 | case 0x00: | |
773 | /* 133 clock attempt to force it on */ | |
774 | pci_write_config_byte(dev, 0x8A, tmpbyte|0x10); | |
775 | case 0x30: | |
776 | /* if clocking is disabled */ | |
777 | /* 133 clock attempt to force it on */ | |
778 | pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20); | |
779 | case 0x10: | |
780 | /* 133 already */ | |
781 | break; | |
782 | case 0x20: | |
783 | /* BIOS set PCI x2 clocking */ | |
784 | break; | |
785 | } | |
786 | ||
787 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
788 | ||
789 | pci_write_config_byte(dev, 0xA1, 0x72); | |
790 | pci_write_config_word(dev, 0xA2, 0x328A); | |
791 | pci_write_config_dword(dev, 0xA4, 0x62DD62DD); | |
792 | pci_write_config_dword(dev, 0xA8, 0x43924392); | |
793 | pci_write_config_dword(dev, 0xAC, 0x40094009); | |
794 | pci_write_config_byte(dev, 0xB1, 0x72); | |
795 | pci_write_config_word(dev, 0xB2, 0x328A); | |
796 | pci_write_config_dword(dev, 0xB4, 0x62DD62DD); | |
797 | pci_write_config_dword(dev, 0xB8, 0x43924392); | |
798 | pci_write_config_dword(dev, 0xBC, 0x40094009); | |
799 | ||
800 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
801 | return 0; | |
802 | } | |
803 | ||
804 | /** | |
805 | * init_mmio_iops_siimage - set up the iops for MMIO | |
806 | * @hwif: interface to set up | |
807 | * | |
808 | * The basic setup here is fairly simple, we can use standard MMIO | |
809 | * operations. However we do have to set the taskfile register offsets | |
810 | * by hand as there isnt a standard defined layout for them this | |
811 | * time. | |
812 | * | |
813 | * The hardware supports buffered taskfiles and also some rather nice | |
19c1ef5f | 814 | * extended PRD tables. For better SI3112 support use the libata driver |
1da177e4 LT |
815 | */ |
816 | ||
817 | static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) | |
818 | { | |
819 | struct pci_dev *dev = hwif->pci_dev; | |
820 | void *addr = pci_get_drvdata(dev); | |
821 | u8 ch = hwif->channel; | |
822 | hw_regs_t hw; | |
823 | unsigned long base; | |
824 | ||
825 | /* | |
826 | * Fill in the basic HWIF bits | |
827 | */ | |
828 | ||
829 | default_hwif_mmiops(hwif); | |
830 | hwif->hwif_data = addr; | |
831 | ||
832 | /* | |
833 | * Now set up the hw. We have to do this ourselves as | |
834 | * the MMIO layout isnt the same as the the standard port | |
835 | * based I/O | |
836 | */ | |
837 | ||
838 | memset(&hw, 0, sizeof(hw_regs_t)); | |
839 | ||
840 | base = (unsigned long)addr; | |
841 | if (ch) | |
842 | base += 0xC0; | |
843 | else | |
844 | base += 0x80; | |
845 | ||
846 | /* | |
847 | * The buffered task file doesn't have status/control | |
848 | * so we can't currently use it sanely since we want to | |
849 | * use LBA48 mode. | |
850 | */ | |
1da177e4 LT |
851 | hw.io_ports[IDE_DATA_OFFSET] = base; |
852 | hw.io_ports[IDE_ERROR_OFFSET] = base + 1; | |
853 | hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2; | |
854 | hw.io_ports[IDE_SECTOR_OFFSET] = base + 3; | |
855 | hw.io_ports[IDE_LCYL_OFFSET] = base + 4; | |
856 | hw.io_ports[IDE_HCYL_OFFSET] = base + 5; | |
857 | hw.io_ports[IDE_SELECT_OFFSET] = base + 6; | |
858 | hw.io_ports[IDE_STATUS_OFFSET] = base + 7; | |
859 | hw.io_ports[IDE_CONTROL_OFFSET] = base + 10; | |
860 | ||
861 | hw.io_ports[IDE_IRQ_OFFSET] = 0; | |
862 | ||
863 | if (pdev_is_sata(dev)) { | |
864 | base = (unsigned long)addr; | |
865 | if (ch) | |
866 | base += 0x80; | |
867 | hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; | |
868 | hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; | |
869 | hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; | |
870 | hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140; | |
871 | hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144; | |
872 | hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148; | |
873 | } | |
874 | ||
875 | hw.irq = hwif->pci_dev->irq; | |
876 | ||
877 | memcpy(&hwif->hw, &hw, sizeof(hw)); | |
878 | memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports)); | |
879 | ||
880 | hwif->irq = hw.irq; | |
881 | ||
882 | base = (unsigned long) addr; | |
883 | ||
1da177e4 | 884 | hwif->dma_base = base + (ch ? 0x08 : 0x00); |
2ad1e558 BZ |
885 | |
886 | hwif->mmio = 1; | |
1da177e4 LT |
887 | } |
888 | ||
889 | static int is_dev_seagate_sata(ide_drive_t *drive) | |
890 | { | |
891 | const char *s = &drive->id->model[0]; | |
892 | unsigned len; | |
893 | ||
894 | if (!drive->present) | |
895 | return 0; | |
896 | ||
897 | len = strnlen(s, sizeof(drive->id->model)); | |
898 | ||
899 | if ((len > 4) && (!memcmp(s, "ST", 2))) { | |
900 | if ((!memcmp(s + len - 2, "AS", 2)) || | |
901 | (!memcmp(s + len - 3, "ASL", 3))) { | |
902 | printk(KERN_INFO "%s: applying pessimistic Seagate " | |
903 | "errata fix\n", drive->name); | |
904 | return 1; | |
905 | } | |
906 | } | |
907 | return 0; | |
908 | } | |
909 | ||
910 | /** | |
911 | * siimage_fixup - post probe fixups | |
912 | * @hwif: interface to fix up | |
913 | * | |
914 | * Called after drive probe we use this to decide whether the | |
915 | * Seagate fixup must be applied. This used to be in init_iops but | |
916 | * that can occur before we know what drives are present. | |
917 | */ | |
918 | ||
919 | static void __devinit siimage_fixup(ide_hwif_t *hwif) | |
920 | { | |
921 | /* Try and raise the rqsize */ | |
922 | if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0])) | |
923 | hwif->rqsize = 128; | |
924 | } | |
925 | ||
926 | /** | |
927 | * init_iops_siimage - set up iops | |
928 | * @hwif: interface to set up | |
929 | * | |
930 | * Do the basic setup for the SIIMAGE hardware interface | |
931 | * and then do the MMIO setup if we can. This is the first | |
932 | * look in we get for setting up the hwif so that we | |
933 | * can get the iops right before using them. | |
934 | */ | |
935 | ||
936 | static void __devinit init_iops_siimage(ide_hwif_t *hwif) | |
937 | { | |
938 | struct pci_dev *dev = hwif->pci_dev; | |
939 | u32 class_rev = 0; | |
940 | ||
941 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
942 | class_rev &= 0xff; | |
943 | ||
944 | hwif->hwif_data = NULL; | |
945 | ||
946 | /* Pessimal until we finish probing */ | |
947 | hwif->rqsize = 15; | |
948 | ||
949 | if (pci_get_drvdata(dev) == NULL) | |
950 | return; | |
951 | init_mmio_iops_siimage(hwif); | |
952 | } | |
953 | ||
954 | /** | |
955 | * ata66_siimage - check for 80 pin cable | |
956 | * @hwif: interface to check | |
957 | * | |
958 | * Check for the presence of an ATA66 capable cable on the | |
959 | * interface. | |
960 | */ | |
961 | ||
962 | static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif) | |
963 | { | |
964 | unsigned long addr = siimage_selreg(hwif, 0); | |
965 | if (pci_get_drvdata(hwif->pci_dev) == NULL) { | |
966 | u8 ata66 = 0; | |
967 | pci_read_config_byte(hwif->pci_dev, addr, &ata66); | |
968 | return (ata66 & 0x01) ? 1 : 0; | |
969 | } | |
970 | ||
971 | return (hwif->INB(addr) & 0x01) ? 1 : 0; | |
972 | } | |
973 | ||
974 | /** | |
975 | * init_hwif_siimage - set up hwif structs | |
976 | * @hwif: interface to set up | |
977 | * | |
978 | * We do the basic set up of the interface structure. The SIIMAGE | |
979 | * requires several custom handlers so we override the default | |
980 | * ide DMA handlers appropriately | |
981 | */ | |
982 | ||
983 | static void __devinit init_hwif_siimage(ide_hwif_t *hwif) | |
984 | { | |
985 | hwif->autodma = 0; | |
986 | ||
987 | hwif->resetproc = &siimage_reset; | |
988 | hwif->speedproc = &siimage_tune_chipset; | |
989 | hwif->tuneproc = &siimage_tuneproc; | |
990 | hwif->reset_poll = &siimage_reset_poll; | |
991 | hwif->pre_reset = &siimage_pre_reset; | |
992 | ||
19c1ef5f AC |
993 | if(is_sata(hwif)) { |
994 | static int first = 1; | |
995 | ||
1da177e4 LT |
996 | hwif->busproc = &siimage_busproc; |
997 | ||
19c1ef5f AC |
998 | if (first) { |
999 | printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n"); | |
1000 | first = 0; | |
1001 | } | |
1002 | } | |
1da177e4 LT |
1003 | if (!hwif->dma_base) { |
1004 | hwif->drives[0].autotune = 1; | |
1005 | hwif->drives[1].autotune = 1; | |
1006 | return; | |
1007 | } | |
1008 | ||
1009 | hwif->ultra_mask = 0x7f; | |
1010 | hwif->mwdma_mask = 0x07; | |
1da177e4 LT |
1011 | |
1012 | if (!is_sata(hwif)) | |
1013 | hwif->atapi_dma = 1; | |
1014 | ||
1015 | hwif->ide_dma_check = &siimage_config_drive_for_dma; | |
1016 | if (!(hwif->udma_four)) | |
1017 | hwif->udma_four = ata66_siimage(hwif); | |
1018 | ||
1019 | if (hwif->mmio) { | |
1020 | hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq; | |
1021 | } else { | |
1022 | hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq; | |
1023 | } | |
1024 | ||
1025 | /* | |
1026 | * The BIOS often doesn't set up DMA on this controller | |
1027 | * so we always do it. | |
1028 | */ | |
1029 | ||
1030 | hwif->autodma = 1; | |
1031 | hwif->drives[0].autodma = hwif->autodma; | |
1032 | hwif->drives[1].autodma = hwif->autodma; | |
1033 | } | |
1034 | ||
1035 | #define DECLARE_SII_DEV(name_str) \ | |
1036 | { \ | |
1037 | .name = name_str, \ | |
1038 | .init_chipset = init_chipset_siimage, \ | |
1039 | .init_iops = init_iops_siimage, \ | |
1040 | .init_hwif = init_hwif_siimage, \ | |
1041 | .fixup = siimage_fixup, \ | |
1042 | .channels = 2, \ | |
1043 | .autodma = AUTODMA, \ | |
1044 | .bootable = ON_BOARD, \ | |
1045 | } | |
1046 | ||
1047 | static ide_pci_device_t siimage_chipsets[] __devinitdata = { | |
1048 | /* 0 */ DECLARE_SII_DEV("SiI680"), | |
1049 | /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"), | |
1050 | /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA") | |
1051 | }; | |
1052 | ||
1053 | /** | |
1054 | * siimage_init_one - pci layer discovery entry | |
1055 | * @dev: PCI device | |
1056 | * @id: ident table entry | |
1057 | * | |
1058 | * Called by the PCI code when it finds an SI680 or SI3112 controller. | |
1059 | * We then use the IDE PCI generic helper to do most of the work. | |
1060 | */ | |
1061 | ||
1062 | static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
1063 | { | |
1064 | return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]); | |
1065 | } | |
1066 | ||
1067 | static struct pci_device_id siimage_pci_tbl[] = { | |
28a2a3f5 | 1068 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1da177e4 | 1069 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
28a2a3f5 AC |
1070 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
1071 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
1da177e4 LT |
1072 | #endif |
1073 | { 0, }, | |
1074 | }; | |
1075 | MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); | |
1076 | ||
1077 | static struct pci_driver driver = { | |
1078 | .name = "SiI_IDE", | |
1079 | .id_table = siimage_pci_tbl, | |
1080 | .probe = siimage_init_one, | |
1081 | }; | |
1082 | ||
82ab1eec | 1083 | static int __init siimage_ide_init(void) |
1da177e4 LT |
1084 | { |
1085 | return ide_pci_register_driver(&driver); | |
1086 | } | |
1087 | ||
1088 | module_init(siimage_ide_init); | |
1089 | ||
1090 | MODULE_AUTHOR("Andre Hedrick, Alan Cox"); | |
1091 | MODULE_DESCRIPTION("PCI driver module for SiI IDE"); | |
1092 | MODULE_LICENSE("GPL"); |