]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
7b255436 | 4 | * Copyright (C) 2007-2008 MontaVista Software, Inc. |
165701d9 | 5 | * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
6 | * |
7 | * May be copied or modified under the terms of the GNU General Public License | |
8 | * | |
bf4c796d JG |
9 | * Documentation for CMD680: |
10 | * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 | |
11 | * | |
12 | * Documentation for SiI 3112: | |
13 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
14 | * | |
15 | * Errata and other documentation only available under NDA. | |
1da177e4 LT |
16 | * |
17 | * | |
18 | * FAQ Items: | |
19 | * If you are using Marvell SATA-IDE adapters with Maxtor drives | |
7b255436 | 20 | * ensure the system is set up for ATA100/UDMA5, not UDMA6. |
1da177e4 LT |
21 | * |
22 | * If you are using WD drives with SATA bridges you must set the | |
7b255436 | 23 | * drive to "Single". "Master" will hang. |
1da177e4 LT |
24 | * |
25 | * If you have strange problems with nVidia chipset systems please | |
26 | * see the SI support documentation and update your system BIOS | |
3a4fa0a2 | 27 | * if necessary |
8693d3e4 AC |
28 | * |
29 | * The Dell DRAC4 has some interesting features including effectively hot | |
30 | * unplugging/replugging the virtual CD interface when the DRAC is reset. | |
31 | * This often causes drivers/ide/siimage to panic but is ok with the rather | |
32 | * smarter code in libata. | |
328dcbb6 BZ |
33 | * |
34 | * TODO: | |
35 | * - IORDY fixes | |
36 | * - VDMA support | |
1da177e4 LT |
37 | */ |
38 | ||
1da177e4 LT |
39 | #include <linux/types.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/pci.h> | |
1da177e4 LT |
42 | #include <linux/ide.h> |
43 | #include <linux/init.h> | |
7b255436 | 44 | #include <linux/io.h> |
1da177e4 | 45 | |
ced3ec8a BZ |
46 | #define DRV_NAME "siimage" |
47 | ||
1da177e4 LT |
48 | /** |
49 | * pdev_is_sata - check if device is SATA | |
50 | * @pdev: PCI device to check | |
7b255436 | 51 | * |
1da177e4 LT |
52 | * Returns true if this is a SATA controller |
53 | */ | |
7b255436 | 54 | |
1da177e4 LT |
55 | static int pdev_is_sata(struct pci_dev *pdev) |
56 | { | |
438c4702 | 57 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
7b255436 SS |
58 | switch (pdev->device) { |
59 | case PCI_DEVICE_ID_SII_3112: | |
60 | case PCI_DEVICE_ID_SII_1210SA: | |
61 | return 1; | |
62 | case PCI_DEVICE_ID_SII_680: | |
63 | return 0; | |
1da177e4 LT |
64 | } |
65 | BUG(); | |
438c4702 | 66 | #endif |
1da177e4 LT |
67 | return 0; |
68 | } | |
438c4702 | 69 | |
1da177e4 LT |
70 | /** |
71 | * is_sata - check if hwif is SATA | |
72 | * @hwif: interface to check | |
7b255436 | 73 | * |
1da177e4 LT |
74 | * Returns true if this is a SATA controller |
75 | */ | |
7b255436 | 76 | |
1da177e4 LT |
77 | static inline int is_sata(ide_hwif_t *hwif) |
78 | { | |
36501650 | 79 | return pdev_is_sata(to_pci_dev(hwif->dev)); |
1da177e4 LT |
80 | } |
81 | ||
82 | /** | |
83 | * siimage_selreg - return register base | |
84 | * @hwif: interface | |
85 | * @r: config offset | |
86 | * | |
87 | * Turn a config register offset into the right address in either | |
88 | * PCI space or MMIO space to access the control register in question | |
7b255436 SS |
89 | * Thankfully this is a configuration operation, so isn't performance |
90 | * critical. | |
1da177e4 | 91 | */ |
7b255436 | 92 | |
1da177e4 LT |
93 | static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) |
94 | { | |
95 | unsigned long base = (unsigned long)hwif->hwif_data; | |
7b255436 | 96 | |
1da177e4 | 97 | base += 0xA0 + r; |
13572144 | 98 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
7b255436 | 99 | base += hwif->channel << 6; |
1da177e4 | 100 | else |
7b255436 | 101 | base += hwif->channel << 4; |
1da177e4 LT |
102 | return base; |
103 | } | |
7b255436 | 104 | |
1da177e4 LT |
105 | /** |
106 | * siimage_seldev - return register base | |
107 | * @hwif: interface | |
108 | * @r: config offset | |
109 | * | |
110 | * Turn a config register offset into the right address in either | |
111 | * PCI space or MMIO space to access the control register in question | |
112 | * including accounting for the unit shift. | |
113 | */ | |
7b255436 | 114 | |
1da177e4 LT |
115 | static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) |
116 | { | |
117 | ide_hwif_t *hwif = HWIF(drive); | |
7b255436 SS |
118 | unsigned long base = (unsigned long)hwif->hwif_data; |
119 | ||
1da177e4 | 120 | base += 0xA0 + r; |
13572144 | 121 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
7b255436 | 122 | base += hwif->channel << 6; |
1da177e4 | 123 | else |
7b255436 | 124 | base += hwif->channel << 4; |
1da177e4 LT |
125 | base |= drive->select.b.unit << drive->select.b.unit; |
126 | return base; | |
127 | } | |
128 | ||
165701d9 BZ |
129 | static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr) |
130 | { | |
4c674235 | 131 | struct ide_host *host = pci_get_drvdata(dev); |
165701d9 BZ |
132 | u8 tmp = 0; |
133 | ||
4c674235 | 134 | if (host->host_priv) |
165701d9 BZ |
135 | tmp = readb((void __iomem *)addr); |
136 | else | |
137 | pci_read_config_byte(dev, addr, &tmp); | |
138 | ||
139 | return tmp; | |
140 | } | |
141 | ||
142 | static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr) | |
143 | { | |
4c674235 | 144 | struct ide_host *host = pci_get_drvdata(dev); |
165701d9 BZ |
145 | u16 tmp = 0; |
146 | ||
4c674235 | 147 | if (host->host_priv) |
165701d9 BZ |
148 | tmp = readw((void __iomem *)addr); |
149 | else | |
150 | pci_read_config_word(dev, addr, &tmp); | |
151 | ||
152 | return tmp; | |
153 | } | |
154 | ||
155 | static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr) | |
156 | { | |
4c674235 BZ |
157 | struct ide_host *host = pci_get_drvdata(dev); |
158 | ||
159 | if (host->host_priv) | |
165701d9 BZ |
160 | writeb(val, (void __iomem *)addr); |
161 | else | |
162 | pci_write_config_byte(dev, addr, val); | |
163 | } | |
164 | ||
165 | static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr) | |
166 | { | |
4c674235 BZ |
167 | struct ide_host *host = pci_get_drvdata(dev); |
168 | ||
169 | if (host->host_priv) | |
165701d9 BZ |
170 | writew(val, (void __iomem *)addr); |
171 | else | |
172 | pci_write_config_word(dev, addr, val); | |
173 | } | |
174 | ||
175 | static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr) | |
176 | { | |
4c674235 BZ |
177 | struct ide_host *host = pci_get_drvdata(dev); |
178 | ||
179 | if (host->host_priv) | |
165701d9 BZ |
180 | writel(val, (void __iomem *)addr); |
181 | else | |
182 | pci_write_config_dword(dev, addr, val); | |
183 | } | |
184 | ||
1da177e4 | 185 | /** |
2d5eaa6d BZ |
186 | * sil_udma_filter - compute UDMA mask |
187 | * @drive: IDE device | |
188 | * | |
189 | * Compute the available UDMA speeds for the device on the interface. | |
1da177e4 | 190 | * |
1da177e4 | 191 | * For the CMD680 this depends on the clocking mode (scsc), for the |
2d5eaa6d | 192 | * SI3112 SATA controller life is a bit simpler. |
1da177e4 | 193 | */ |
2d5eaa6d | 194 | |
438c4702 | 195 | static u8 sil_pata_udma_filter(ide_drive_t *drive) |
1da177e4 | 196 | { |
7b255436 SS |
197 | ide_hwif_t *hwif = drive->hwif; |
198 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
199 | unsigned long base = (unsigned long)hwif->hwif_data; | |
200 | u8 scsc, mask = 0; | |
1da177e4 | 201 | |
13572144 BZ |
202 | base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A; |
203 | ||
204 | scsc = sil_ioread8(dev, base); | |
1da177e4 | 205 | |
7b255436 SS |
206 | switch (scsc & 0x30) { |
207 | case 0x10: /* 133 */ | |
438c4702 | 208 | mask = ATA_UDMA6; |
7b255436 SS |
209 | break; |
210 | case 0x20: /* 2xPCI */ | |
438c4702 | 211 | mask = ATA_UDMA6; |
7b255436 SS |
212 | break; |
213 | case 0x00: /* 100 */ | |
438c4702 | 214 | mask = ATA_UDMA5; |
7b255436 SS |
215 | break; |
216 | default: /* Disabled ? */ | |
1da177e4 | 217 | BUG(); |
7b255436 | 218 | } |
438c4702 | 219 | |
2d5eaa6d | 220 | return mask; |
1da177e4 LT |
221 | } |
222 | ||
438c4702 BZ |
223 | static u8 sil_sata_udma_filter(ide_drive_t *drive) |
224 | { | |
4dde4492 BZ |
225 | char *m = (char *)&drive->id[ATA_ID_PROD]; |
226 | ||
227 | return strstr(m, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6; | |
438c4702 BZ |
228 | } |
229 | ||
1da177e4 | 230 | /** |
88b2b32b BZ |
231 | * sil_set_pio_mode - set host controller for PIO mode |
232 | * @drive: drive | |
233 | * @pio: PIO mode number | |
1da177e4 LT |
234 | * |
235 | * Load the timing settings for this device mode into the | |
236 | * controller. If we are in PIO mode 3 or 4 turn on IORDY | |
237 | * monitoring (bit 9). The TF timing is bits 31:16 | |
238 | */ | |
328dcbb6 | 239 | |
88b2b32b | 240 | static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) |
1da177e4 | 241 | { |
7b255436 SS |
242 | static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; |
243 | static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; | |
328dcbb6 | 244 | |
1da177e4 | 245 | ide_hwif_t *hwif = HWIF(drive); |
165701d9 | 246 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
7e59ea21 | 247 | ide_drive_t *pair = ide_get_pair_dev(drive); |
1da177e4 LT |
248 | u32 speedt = 0; |
249 | u16 speedp = 0; | |
250 | unsigned long addr = siimage_seldev(drive, 0x04); | |
7b255436 | 251 | unsigned long tfaddr = siimage_selreg(hwif, 0x02); |
ffe5415c | 252 | unsigned long base = (unsigned long)hwif->hwif_data; |
328dcbb6 | 253 | u8 tf_pio = pio; |
13572144 BZ |
254 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
255 | u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) | |
256 | : (mmio ? 0xB4 : 0x80); | |
ffe5415c BZ |
257 | u8 mode = 0; |
258 | u8 unit = drive->select.b.unit; | |
328dcbb6 BZ |
259 | |
260 | /* trim *taskfile* PIO to the slowest of the master/slave */ | |
7e59ea21 | 261 | if (pair) { |
2134758d | 262 | u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); |
328dcbb6 BZ |
263 | |
264 | if (pair_pio < tf_pio) | |
265 | tf_pio = pair_pio; | |
1da177e4 | 266 | } |
075cb655 | 267 | |
328dcbb6 BZ |
268 | /* cheat for now and use the docs */ |
269 | speedp = data_speed[pio]; | |
270 | speedt = tf_speed[tf_pio]; | |
271 | ||
165701d9 BZ |
272 | sil_iowrite16(dev, speedp, addr); |
273 | sil_iowrite16(dev, speedt, tfaddr); | |
274 | ||
275 | /* now set up IORDY */ | |
276 | speedp = sil_ioread16(dev, tfaddr - 2); | |
277 | speedp &= ~0x200; | |
278 | if (pio > 2) | |
279 | speedp |= 0x200; | |
280 | sil_iowrite16(dev, speedp, tfaddr - 2); | |
281 | ||
282 | mode = sil_ioread8(dev, base + addr_mask); | |
283 | mode &= ~(unit ? 0x30 : 0x03); | |
7b255436 | 284 | mode |= unit ? 0x10 : 0x01; |
165701d9 | 285 | sil_iowrite8(dev, mode, base + addr_mask); |
1da177e4 LT |
286 | } |
287 | ||
1da177e4 | 288 | /** |
88b2b32b BZ |
289 | * sil_set_dma_mode - set host controller for DMA mode |
290 | * @drive: drive | |
291 | * @speed: DMA mode | |
1da177e4 | 292 | * |
88b2b32b | 293 | * Tune the SiI chipset for the desired DMA mode. |
1da177e4 | 294 | */ |
f212ff28 | 295 | |
88b2b32b | 296 | static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 297 | { |
7b255436 SS |
298 | static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; |
299 | static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
300 | static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
1da177e4 LT |
301 | |
302 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 303 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
304 | u16 ultra = 0, multi = 0; |
305 | u8 mode = 0, unit = drive->select.b.unit; | |
1da177e4 | 306 | unsigned long base = (unsigned long)hwif->hwif_data; |
13572144 BZ |
307 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
308 | u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) | |
309 | : (mmio ? 0xB4 : 0x80); | |
1da177e4 LT |
310 | unsigned long ma = siimage_seldev(drive, 0x08); |
311 | unsigned long ua = siimage_seldev(drive, 0x0C); | |
312 | ||
13572144 | 313 | scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A)); |
7b255436 | 314 | mode = sil_ioread8 (dev, base + addr_mask); |
165701d9 BZ |
315 | multi = sil_ioread16(dev, ma); |
316 | ultra = sil_ioread16(dev, ua); | |
1da177e4 | 317 | |
7b255436 | 318 | mode &= ~(unit ? 0x30 : 0x03); |
1da177e4 LT |
319 | ultra &= ~0x3F; |
320 | scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; | |
321 | ||
322 | scsc = is_sata(hwif) ? 1 : scsc; | |
323 | ||
4db90a14 | 324 | if (speed >= XFER_UDMA_0) { |
7b255436 SS |
325 | multi = dma[2]; |
326 | ultra |= scsc ? ultra6[speed - XFER_UDMA_0] : | |
327 | ultra5[speed - XFER_UDMA_0]; | |
328 | mode |= unit ? 0x30 : 0x03; | |
4db90a14 BZ |
329 | } else { |
330 | multi = dma[speed - XFER_MW_DMA_0]; | |
7b255436 | 331 | mode |= unit ? 0x20 : 0x02; |
1da177e4 LT |
332 | } |
333 | ||
7b255436 | 334 | sil_iowrite8 (dev, mode, base + addr_mask); |
165701d9 BZ |
335 | sil_iowrite16(dev, multi, ma); |
336 | sil_iowrite16(dev, ultra, ua); | |
1da177e4 LT |
337 | } |
338 | ||
1da177e4 | 339 | /* returns 1 if dma irq issued, 0 otherwise */ |
5e37bdc0 | 340 | static int siimage_io_dma_test_irq(ide_drive_t *drive) |
1da177e4 LT |
341 | { |
342 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 343 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
344 | u8 dma_altstat = 0; |
345 | unsigned long addr = siimage_selreg(hwif, 1); | |
346 | ||
347 | /* return 1 if INTR asserted */ | |
cab7f8ed | 348 | if (inb(hwif->dma_base + ATA_DMA_STATUS) & 4) |
1da177e4 LT |
349 | return 1; |
350 | ||
351 | /* return 1 if Device INTR asserted */ | |
36501650 | 352 | pci_read_config_byte(dev, addr, &dma_altstat); |
1da177e4 | 353 | if (dma_altstat & 8) |
7b255436 SS |
354 | return 0; /* return 1; */ |
355 | ||
1da177e4 LT |
356 | return 0; |
357 | } | |
358 | ||
1da177e4 | 359 | /** |
5e37bdc0 | 360 | * siimage_mmio_dma_test_irq - check we caused an IRQ |
1da177e4 LT |
361 | * @drive: drive we are testing |
362 | * | |
363 | * Check if we caused an IDE DMA interrupt. We may also have caused | |
364 | * SATA status interrupts, if so we clean them up and continue. | |
365 | */ | |
5e37bdc0 BZ |
366 | |
367 | static int siimage_mmio_dma_test_irq(ide_drive_t *drive) | |
1da177e4 LT |
368 | { |
369 | ide_hwif_t *hwif = HWIF(drive); | |
1da177e4 | 370 | unsigned long addr = siimage_selreg(hwif, 0x1); |
835457de BZ |
371 | void __iomem *sata_error_addr |
372 | = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET]; | |
1da177e4 | 373 | |
835457de | 374 | if (sata_error_addr) { |
7b255436 SS |
375 | unsigned long base = (unsigned long)hwif->hwif_data; |
376 | u32 ext_stat = readl((void __iomem *)(base + 0x10)); | |
377 | u8 watchdog = 0; | |
835457de | 378 | |
1da177e4 | 379 | if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { |
835457de BZ |
380 | u32 sata_error = readl(sata_error_addr); |
381 | ||
382 | writel(sata_error, sata_error_addr); | |
1da177e4 | 383 | watchdog = (sata_error & 0x00680000) ? 1 : 0; |
1da177e4 LT |
384 | printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
385 | "watchdog = %d, %s\n", | |
7b255436 SS |
386 | drive->name, sata_error, watchdog, __func__); |
387 | } else | |
1da177e4 | 388 | watchdog = (ext_stat & 0x8000) ? 1 : 0; |
1da177e4 | 389 | |
7b255436 | 390 | ext_stat >>= 16; |
1da177e4 LT |
391 | if (!(ext_stat & 0x0404) && !watchdog) |
392 | return 0; | |
393 | } | |
394 | ||
395 | /* return 1 if INTR asserted */ | |
cab7f8ed | 396 | if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4) |
1da177e4 LT |
397 | return 1; |
398 | ||
399 | /* return 1 if Device INTR asserted */ | |
7b255436 SS |
400 | if (readb((void __iomem *)addr) & 8) |
401 | return 0; /* return 1; */ | |
1da177e4 LT |
402 | |
403 | return 0; | |
404 | } | |
405 | ||
5e37bdc0 BZ |
406 | static int siimage_dma_test_irq(ide_drive_t *drive) |
407 | { | |
13572144 | 408 | if (drive->hwif->host_flags & IDE_HFLAG_MMIO) |
5e37bdc0 BZ |
409 | return siimage_mmio_dma_test_irq(drive); |
410 | else | |
411 | return siimage_io_dma_test_irq(drive); | |
412 | } | |
413 | ||
1da177e4 | 414 | /** |
438c4702 | 415 | * sil_sata_reset_poll - wait for SATA reset |
1da177e4 LT |
416 | * @drive: drive we are resetting |
417 | * | |
418 | * Poll the SATA phy and see whether it has come back from the dead | |
419 | * yet. | |
420 | */ | |
438c4702 BZ |
421 | |
422 | static int sil_sata_reset_poll(ide_drive_t *drive) | |
1da177e4 | 423 | { |
835457de BZ |
424 | ide_hwif_t *hwif = drive->hwif; |
425 | void __iomem *sata_status_addr | |
426 | = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET]; | |
427 | ||
428 | if (sata_status_addr) { | |
429 | /* SATA Status is available only when in MMIO mode */ | |
430 | u32 sata_stat = readl(sata_status_addr); | |
1da177e4 | 431 | |
835457de | 432 | if ((sata_stat & 0x03) != 0x03) { |
1da177e4 | 433 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", |
835457de | 434 | hwif->name, sata_stat); |
64a8f00f | 435 | return -ENXIO; |
1da177e4 | 436 | } |
1da177e4 | 437 | } |
438c4702 BZ |
438 | |
439 | return 0; | |
1da177e4 LT |
440 | } |
441 | ||
442 | /** | |
438c4702 | 443 | * sil_sata_pre_reset - reset hook |
1da177e4 LT |
444 | * @drive: IDE device being reset |
445 | * | |
446 | * For the SATA devices we need to handle recalibration/geometry | |
447 | * differently | |
448 | */ | |
1da177e4 | 449 | |
438c4702 BZ |
450 | static void sil_sata_pre_reset(ide_drive_t *drive) |
451 | { | |
452 | if (drive->media == ide_disk) { | |
1da177e4 LT |
453 | drive->special.b.set_geometry = 0; |
454 | drive->special.b.recalibrate = 0; | |
455 | } | |
456 | } | |
457 | ||
1da177e4 LT |
458 | /** |
459 | * init_chipset_siimage - set up an SI device | |
460 | * @dev: PCI device | |
1da177e4 LT |
461 | * |
462 | * Perform the initial PCI set up for this device. Attempt to switch | |
7b255436 | 463 | * to 133 MHz clocking if the system isn't already set up to do it. |
1da177e4 LT |
464 | */ |
465 | ||
a326b02b | 466 | static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev) |
1da177e4 | 467 | { |
4c674235 BZ |
468 | struct ide_host *host = pci_get_drvdata(dev); |
469 | void __iomem *ioaddr = host->host_priv; | |
165701d9 | 470 | unsigned long base, scsc_addr; |
4c674235 | 471 | u8 rev = dev->revision, tmp; |
1da177e4 | 472 | |
fc212bb1 | 473 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255); |
1da177e4 | 474 | |
4c674235 BZ |
475 | if (ioaddr) |
476 | pci_set_master(dev); | |
165701d9 BZ |
477 | |
478 | base = (unsigned long)ioaddr; | |
479 | ||
480 | if (ioaddr && pdev_is_sata(dev)) { | |
481 | u32 tmp32, irq_mask; | |
482 | ||
483 | /* make sure IDE0/1 interrupts are not masked */ | |
484 | irq_mask = (1 << 22) | (1 << 23); | |
485 | tmp32 = readl(ioaddr + 0x48); | |
486 | if (tmp32 & irq_mask) { | |
487 | tmp32 &= ~irq_mask; | |
488 | writel(tmp32, ioaddr + 0x48); | |
489 | readl(ioaddr + 0x48); /* flush */ | |
1da177e4 | 490 | } |
165701d9 BZ |
491 | writel(0, ioaddr + 0x148); |
492 | writel(0, ioaddr + 0x1C8); | |
1da177e4 LT |
493 | } |
494 | ||
165701d9 BZ |
495 | sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80); |
496 | sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84); | |
497 | ||
498 | scsc_addr = base ? (base + 0x4A) : 0x8A; | |
499 | tmp = sil_ioread8(dev, scsc_addr); | |
500 | ||
501 | switch (tmp & 0x30) { | |
502 | case 0x00: | |
7b255436 | 503 | /* On 100 MHz clocking, try and switch to 133 MHz */ |
165701d9 BZ |
504 | sil_iowrite8(dev, tmp | 0x10, scsc_addr); |
505 | break; | |
506 | case 0x30: | |
507 | /* Clocking is disabled, attempt to force 133MHz clocking. */ | |
508 | sil_iowrite8(dev, tmp & ~0x20, scsc_addr); | |
509 | case 0x10: | |
510 | /* On 133Mhz clocking. */ | |
511 | break; | |
512 | case 0x20: | |
513 | /* On PCIx2 clocking. */ | |
514 | break; | |
1da177e4 LT |
515 | } |
516 | ||
165701d9 | 517 | tmp = sil_ioread8(dev, scsc_addr); |
1da177e4 | 518 | |
7b255436 | 519 | sil_iowrite8 (dev, 0x72, base + 0xA1); |
165701d9 BZ |
520 | sil_iowrite16(dev, 0x328A, base + 0xA2); |
521 | sil_iowrite32(dev, 0x62DD62DD, base + 0xA4); | |
522 | sil_iowrite32(dev, 0x43924392, base + 0xA8); | |
523 | sil_iowrite32(dev, 0x40094009, base + 0xAC); | |
7b255436 | 524 | sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1); |
165701d9 BZ |
525 | sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2); |
526 | sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4); | |
527 | sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8); | |
528 | sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC); | |
529 | ||
530 | if (base && pdev_is_sata(dev)) { | |
531 | writel(0xFFFF0000, ioaddr + 0x108); | |
532 | writel(0xFFFF0000, ioaddr + 0x188); | |
533 | writel(0x00680000, ioaddr + 0x148); | |
534 | writel(0x00680000, ioaddr + 0x1C8); | |
535 | } | |
536 | ||
24cc434a BZ |
537 | /* report the clocking mode of the controller */ |
538 | if (!pdev_is_sata(dev)) { | |
539 | static const char *clk_str[] = | |
540 | { "== 100", "== 133", "== 2X PCI", "DISABLED!" }; | |
541 | ||
542 | tmp >>= 4; | |
a326b02b BZ |
543 | printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n", |
544 | pci_name(dev), clk_str[tmp & 3]); | |
24cc434a | 545 | } |
1da177e4 | 546 | |
1da177e4 LT |
547 | return 0; |
548 | } | |
549 | ||
550 | /** | |
551 | * init_mmio_iops_siimage - set up the iops for MMIO | |
552 | * @hwif: interface to set up | |
553 | * | |
554 | * The basic setup here is fairly simple, we can use standard MMIO | |
555 | * operations. However we do have to set the taskfile register offsets | |
7b255436 | 556 | * by hand as there isn't a standard defined layout for them this time. |
1da177e4 LT |
557 | * |
558 | * The hardware supports buffered taskfiles and also some rather nice | |
19c1ef5f | 559 | * extended PRD tables. For better SI3112 support use the libata driver |
1da177e4 LT |
560 | */ |
561 | ||
562 | static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) | |
563 | { | |
36501650 | 564 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
4c674235 BZ |
565 | struct ide_host *host = pci_get_drvdata(dev); |
566 | void *addr = host->host_priv; | |
1da177e4 | 567 | u8 ch = hwif->channel; |
4c3032d8 | 568 | struct ide_io_ports *io_ports = &hwif->io_ports; |
7b255436 | 569 | unsigned long base; |
4c3032d8 | 570 | |
1da177e4 | 571 | /* |
7b255436 | 572 | * Fill in the basic hwif bits |
1da177e4 | 573 | */ |
c5dd43ec | 574 | hwif->host_flags |= IDE_HFLAG_MMIO; |
761052e6 | 575 | |
7b255436 | 576 | hwif->hwif_data = addr; |
1da177e4 LT |
577 | |
578 | /* | |
7b255436 SS |
579 | * Now set up the hw. We have to do this ourselves as the |
580 | * MMIO layout isn't the same as the standard port based I/O. | |
1da177e4 | 581 | */ |
4c3032d8 | 582 | memset(io_ports, 0, sizeof(*io_ports)); |
1da177e4 LT |
583 | |
584 | base = (unsigned long)addr; | |
585 | if (ch) | |
586 | base += 0xC0; | |
587 | else | |
588 | base += 0x80; | |
589 | ||
590 | /* | |
7b255436 SS |
591 | * The buffered task file doesn't have status/control, so we |
592 | * can't currently use it sanely since we want to use LBA48 mode. | |
593 | */ | |
4c3032d8 BZ |
594 | io_ports->data_addr = base; |
595 | io_ports->error_addr = base + 1; | |
596 | io_ports->nsect_addr = base + 2; | |
597 | io_ports->lbal_addr = base + 3; | |
598 | io_ports->lbam_addr = base + 4; | |
599 | io_ports->lbah_addr = base + 5; | |
600 | io_ports->device_addr = base + 6; | |
601 | io_ports->status_addr = base + 7; | |
602 | io_ports->ctl_addr = base + 10; | |
1da177e4 LT |
603 | |
604 | if (pdev_is_sata(dev)) { | |
605 | base = (unsigned long)addr; | |
606 | if (ch) | |
607 | base += 0x80; | |
608 | hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; | |
609 | hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; | |
610 | hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; | |
1da177e4 LT |
611 | } |
612 | ||
9239b333 | 613 | hwif->irq = dev->irq; |
1da177e4 | 614 | |
9239b333 | 615 | hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00); |
1da177e4 LT |
616 | } |
617 | ||
618 | static int is_dev_seagate_sata(ide_drive_t *drive) | |
619 | { | |
4dde4492 BZ |
620 | const char *s = (const char *)&drive->id[ATA_ID_PROD]; |
621 | unsigned len = strnlen(s, ATA_ID_PROD_LEN); | |
1da177e4 | 622 | |
7b255436 | 623 | if ((len > 4) && (!memcmp(s, "ST", 2))) |
1da177e4 LT |
624 | if ((!memcmp(s + len - 2, "AS", 2)) || |
625 | (!memcmp(s + len - 3, "ASL", 3))) { | |
626 | printk(KERN_INFO "%s: applying pessimistic Seagate " | |
627 | "errata fix\n", drive->name); | |
628 | return 1; | |
629 | } | |
7b255436 | 630 | |
1da177e4 LT |
631 | return 0; |
632 | } | |
633 | ||
634 | /** | |
f01393e4 BZ |
635 | * sil_quirkproc - post probe fixups |
636 | * @drive: drive | |
1da177e4 LT |
637 | * |
638 | * Called after drive probe we use this to decide whether the | |
639 | * Seagate fixup must be applied. This used to be in init_iops but | |
640 | * that can occur before we know what drives are present. | |
641 | */ | |
642 | ||
36de9948 | 643 | static void sil_quirkproc(ide_drive_t *drive) |
1da177e4 | 644 | { |
f01393e4 BZ |
645 | ide_hwif_t *hwif = drive->hwif; |
646 | ||
7b255436 | 647 | /* Try and rise the rqsize */ |
f01393e4 | 648 | if (!is_sata(hwif) || !is_dev_seagate_sata(drive)) |
1da177e4 LT |
649 | hwif->rqsize = 128; |
650 | } | |
651 | ||
652 | /** | |
653 | * init_iops_siimage - set up iops | |
654 | * @hwif: interface to set up | |
655 | * | |
656 | * Do the basic setup for the SIIMAGE hardware interface | |
657 | * and then do the MMIO setup if we can. This is the first | |
658 | * look in we get for setting up the hwif so that we | |
659 | * can get the iops right before using them. | |
660 | */ | |
661 | ||
662 | static void __devinit init_iops_siimage(ide_hwif_t *hwif) | |
663 | { | |
36501650 | 664 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
4c674235 | 665 | struct ide_host *host = pci_get_drvdata(dev); |
36501650 | 666 | |
1da177e4 LT |
667 | hwif->hwif_data = NULL; |
668 | ||
669 | /* Pessimal until we finish probing */ | |
670 | hwif->rqsize = 15; | |
671 | ||
4c674235 BZ |
672 | if (host->host_priv) |
673 | init_mmio_iops_siimage(hwif); | |
1da177e4 LT |
674 | } |
675 | ||
676 | /** | |
ac95beed | 677 | * sil_cable_detect - cable detection |
1da177e4 LT |
678 | * @hwif: interface to check |
679 | * | |
7b255436 | 680 | * Check for the presence of an ATA66 capable cable on the interface. |
1da177e4 LT |
681 | */ |
682 | ||
f454cbe8 | 683 | static u8 sil_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 684 | { |
7b255436 SS |
685 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
686 | unsigned long addr = siimage_selreg(hwif, 0); | |
687 | u8 ata66 = sil_ioread8(dev, addr); | |
1da177e4 | 688 | |
49521f97 | 689 | return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
1da177e4 LT |
690 | } |
691 | ||
ac95beed BZ |
692 | static const struct ide_port_ops sil_pata_port_ops = { |
693 | .set_pio_mode = sil_set_pio_mode, | |
694 | .set_dma_mode = sil_set_dma_mode, | |
695 | .quirkproc = sil_quirkproc, | |
696 | .udma_filter = sil_pata_udma_filter, | |
697 | .cable_detect = sil_cable_detect, | |
698 | }; | |
699 | ||
700 | static const struct ide_port_ops sil_sata_port_ops = { | |
701 | .set_pio_mode = sil_set_pio_mode, | |
702 | .set_dma_mode = sil_set_dma_mode, | |
703 | .reset_poll = sil_sata_reset_poll, | |
704 | .pre_reset = sil_sata_pre_reset, | |
705 | .quirkproc = sil_quirkproc, | |
706 | .udma_filter = sil_sata_udma_filter, | |
707 | .cable_detect = sil_cable_detect, | |
708 | }; | |
709 | ||
b26b0c59 BH |
710 | static const struct ide_dma_ops sil_dma_ops = { |
711 | .dma_host_set = ide_dma_host_set, | |
712 | .dma_setup = ide_dma_setup, | |
713 | .dma_exec_cmd = ide_dma_exec_cmd, | |
714 | .dma_start = ide_dma_start, | |
715 | .dma_end = __ide_dma_end, | |
5e37bdc0 | 716 | .dma_test_irq = siimage_dma_test_irq, |
b26b0c59 BH |
717 | .dma_timeout = ide_dma_timeout, |
718 | .dma_lost_irq = ide_dma_lost_irq, | |
5e37bdc0 BZ |
719 | }; |
720 | ||
ced3ec8a | 721 | #define DECLARE_SII_DEV(p_ops) \ |
1da177e4 | 722 | { \ |
ced3ec8a | 723 | .name = DRV_NAME, \ |
1da177e4 LT |
724 | .init_chipset = init_chipset_siimage, \ |
725 | .init_iops = init_iops_siimage, \ | |
ac95beed | 726 | .port_ops = p_ops, \ |
5e37bdc0 | 727 | .dma_ops = &sil_dma_ops, \ |
4099d143 | 728 | .pio_mask = ATA_PIO4, \ |
5f8b6c34 BZ |
729 | .mwdma_mask = ATA_MWDMA2, \ |
730 | .udma_mask = ATA_UDMA6, \ | |
1da177e4 LT |
731 | } |
732 | ||
85620436 | 733 | static const struct ide_port_info siimage_chipsets[] __devinitdata = { |
ced3ec8a BZ |
734 | /* 0: SiI680 */ DECLARE_SII_DEV(&sil_pata_port_ops), |
735 | /* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops) | |
1da177e4 LT |
736 | }; |
737 | ||
738 | /** | |
7b255436 | 739 | * siimage_init_one - PCI layer discovery entry |
1da177e4 LT |
740 | * @dev: PCI device |
741 | * @id: ident table entry | |
742 | * | |
7b255436 | 743 | * Called by the PCI code when it finds an SiI680 or SiI3112 controller. |
1da177e4 LT |
744 | * We then use the IDE PCI generic helper to do most of the work. |
745 | */ | |
7b255436 SS |
746 | |
747 | static int __devinit siimage_init_one(struct pci_dev *dev, | |
748 | const struct pci_device_id *id) | |
1da177e4 | 749 | { |
4c674235 BZ |
750 | void __iomem *ioaddr = NULL; |
751 | resource_size_t bar5 = pci_resource_start(dev, 5); | |
752 | unsigned long barsize = pci_resource_len(dev, 5); | |
753 | int rc; | |
5e37bdc0 BZ |
754 | struct ide_port_info d; |
755 | u8 idx = id->driver_data; | |
4c674235 | 756 | u8 BA5_EN; |
5e37bdc0 BZ |
757 | |
758 | d = siimage_chipsets[idx]; | |
759 | ||
760 | if (idx) { | |
761 | static int first = 1; | |
762 | ||
763 | if (first) { | |
ced3ec8a | 764 | printk(KERN_INFO DRV_NAME ": For full SATA support you " |
5e37bdc0 BZ |
765 | "should use the libata sata_sil module.\n"); |
766 | first = 0; | |
767 | } | |
768 | ||
769 | d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA; | |
770 | } | |
771 | ||
4c674235 BZ |
772 | rc = pci_enable_device(dev); |
773 | if (rc) | |
774 | return rc; | |
775 | ||
776 | pci_read_config_byte(dev, 0x8A, &BA5_EN); | |
777 | if ((BA5_EN & 0x01) || bar5) { | |
778 | /* | |
779 | * Drop back to PIO if we can't map the MMIO. Some systems | |
780 | * seem to get terminally confused in the PCI spaces. | |
781 | */ | |
782 | if (!request_mem_region(bar5, barsize, d.name)) { | |
ced3ec8a | 783 | printk(KERN_WARNING DRV_NAME " %s: MMIO ports not " |
28cfd8af | 784 | "available\n", pci_name(dev)); |
4c674235 BZ |
785 | } else { |
786 | ioaddr = ioremap(bar5, barsize); | |
787 | if (ioaddr == NULL) | |
788 | release_mem_region(bar5, barsize); | |
789 | } | |
790 | } | |
791 | ||
792 | rc = ide_pci_init_one(dev, &d, ioaddr); | |
793 | if (rc) { | |
794 | if (ioaddr) { | |
795 | iounmap(ioaddr); | |
796 | release_mem_region(bar5, barsize); | |
797 | } | |
798 | pci_disable_device(dev); | |
799 | } | |
800 | ||
801 | return rc; | |
1da177e4 LT |
802 | } |
803 | ||
fe382580 BZ |
804 | static void __devexit siimage_remove(struct pci_dev *dev) |
805 | { | |
806 | struct ide_host *host = pci_get_drvdata(dev); | |
807 | void __iomem *ioaddr = host->host_priv; | |
808 | ||
809 | ide_pci_remove(dev); | |
810 | ||
811 | if (ioaddr) { | |
812 | resource_size_t bar5 = pci_resource_start(dev, 5); | |
813 | unsigned long barsize = pci_resource_len(dev, 5); | |
814 | ||
815 | iounmap(ioaddr); | |
816 | release_mem_region(bar5, barsize); | |
817 | } | |
818 | ||
819 | pci_disable_device(dev); | |
820 | } | |
821 | ||
9cbcc5e3 BZ |
822 | static const struct pci_device_id siimage_pci_tbl[] = { |
823 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 }, | |
1da177e4 | 824 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
9cbcc5e3 | 825 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 }, |
ced3ec8a | 826 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 1 }, |
1da177e4 LT |
827 | #endif |
828 | { 0, }, | |
829 | }; | |
830 | MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); | |
831 | ||
832 | static struct pci_driver driver = { | |
833 | .name = "SiI_IDE", | |
834 | .id_table = siimage_pci_tbl, | |
835 | .probe = siimage_init_one, | |
a69999e2 | 836 | .remove = __devexit_p(siimage_remove), |
1da177e4 LT |
837 | }; |
838 | ||
82ab1eec | 839 | static int __init siimage_ide_init(void) |
1da177e4 LT |
840 | { |
841 | return ide_pci_register_driver(&driver); | |
842 | } | |
843 | ||
fe382580 BZ |
844 | static void __exit siimage_ide_exit(void) |
845 | { | |
846 | pci_unregister_driver(&driver); | |
847 | } | |
848 | ||
1da177e4 | 849 | module_init(siimage_ide_init); |
fe382580 | 850 | module_exit(siimage_ide_exit); |
1da177e4 LT |
851 | |
852 | MODULE_AUTHOR("Andre Hedrick, Alan Cox"); | |
853 | MODULE_DESCRIPTION("PCI driver module for SiI IDE"); | |
854 | MODULE_LICENSE("GPL"); |