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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
075cb655 | 4 | * Copyright (C) 2007 MontaVista Software, Inc. |
328dcbb6 | 5 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
6 | * |
7 | * May be copied or modified under the terms of the GNU General Public License | |
8 | * | |
bf4c796d JG |
9 | * Documentation for CMD680: |
10 | * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 | |
11 | * | |
12 | * Documentation for SiI 3112: | |
13 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
14 | * | |
15 | * Errata and other documentation only available under NDA. | |
1da177e4 LT |
16 | * |
17 | * | |
18 | * FAQ Items: | |
19 | * If you are using Marvell SATA-IDE adapters with Maxtor drives | |
20 | * ensure the system is set up for ATA100/UDMA5 not UDMA6. | |
21 | * | |
22 | * If you are using WD drives with SATA bridges you must set the | |
23 | * drive to "Single". "Master" will hang | |
24 | * | |
25 | * If you have strange problems with nVidia chipset systems please | |
26 | * see the SI support documentation and update your system BIOS | |
3a4fa0a2 | 27 | * if necessary |
8693d3e4 AC |
28 | * |
29 | * The Dell DRAC4 has some interesting features including effectively hot | |
30 | * unplugging/replugging the virtual CD interface when the DRAC is reset. | |
31 | * This often causes drivers/ide/siimage to panic but is ok with the rather | |
32 | * smarter code in libata. | |
328dcbb6 BZ |
33 | * |
34 | * TODO: | |
35 | * - IORDY fixes | |
36 | * - VDMA support | |
1da177e4 LT |
37 | */ |
38 | ||
1da177e4 LT |
39 | #include <linux/types.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/pci.h> | |
1da177e4 LT |
42 | #include <linux/hdreg.h> |
43 | #include <linux/ide.h> | |
44 | #include <linux/init.h> | |
45 | ||
46 | #include <asm/io.h> | |
47 | ||
1da177e4 LT |
48 | /** |
49 | * pdev_is_sata - check if device is SATA | |
50 | * @pdev: PCI device to check | |
51 | * | |
52 | * Returns true if this is a SATA controller | |
53 | */ | |
54 | ||
55 | static int pdev_is_sata(struct pci_dev *pdev) | |
56 | { | |
438c4702 BZ |
57 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
58 | switch(pdev->device) { | |
1da177e4 LT |
59 | case PCI_DEVICE_ID_SII_3112: |
60 | case PCI_DEVICE_ID_SII_1210SA: | |
61 | return 1; | |
62 | case PCI_DEVICE_ID_SII_680: | |
63 | return 0; | |
64 | } | |
65 | BUG(); | |
438c4702 | 66 | #endif |
1da177e4 LT |
67 | return 0; |
68 | } | |
438c4702 | 69 | |
1da177e4 LT |
70 | /** |
71 | * is_sata - check if hwif is SATA | |
72 | * @hwif: interface to check | |
73 | * | |
74 | * Returns true if this is a SATA controller | |
75 | */ | |
76 | ||
77 | static inline int is_sata(ide_hwif_t *hwif) | |
78 | { | |
36501650 | 79 | return pdev_is_sata(to_pci_dev(hwif->dev)); |
1da177e4 LT |
80 | } |
81 | ||
82 | /** | |
83 | * siimage_selreg - return register base | |
84 | * @hwif: interface | |
85 | * @r: config offset | |
86 | * | |
87 | * Turn a config register offset into the right address in either | |
88 | * PCI space or MMIO space to access the control register in question | |
89 | * Thankfully this is a configuration operation so isnt performance | |
90 | * criticial. | |
91 | */ | |
92 | ||
93 | static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) | |
94 | { | |
95 | unsigned long base = (unsigned long)hwif->hwif_data; | |
96 | base += 0xA0 + r; | |
97 | if(hwif->mmio) | |
98 | base += (hwif->channel << 6); | |
99 | else | |
100 | base += (hwif->channel << 4); | |
101 | return base; | |
102 | } | |
103 | ||
104 | /** | |
105 | * siimage_seldev - return register base | |
106 | * @hwif: interface | |
107 | * @r: config offset | |
108 | * | |
109 | * Turn a config register offset into the right address in either | |
110 | * PCI space or MMIO space to access the control register in question | |
111 | * including accounting for the unit shift. | |
112 | */ | |
113 | ||
114 | static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) | |
115 | { | |
116 | ide_hwif_t *hwif = HWIF(drive); | |
117 | unsigned long base = (unsigned long)hwif->hwif_data; | |
118 | base += 0xA0 + r; | |
119 | if(hwif->mmio) | |
120 | base += (hwif->channel << 6); | |
121 | else | |
122 | base += (hwif->channel << 4); | |
123 | base |= drive->select.b.unit << drive->select.b.unit; | |
124 | return base; | |
125 | } | |
126 | ||
127 | /** | |
2d5eaa6d BZ |
128 | * sil_udma_filter - compute UDMA mask |
129 | * @drive: IDE device | |
130 | * | |
131 | * Compute the available UDMA speeds for the device on the interface. | |
1da177e4 | 132 | * |
1da177e4 | 133 | * For the CMD680 this depends on the clocking mode (scsc), for the |
2d5eaa6d | 134 | * SI3112 SATA controller life is a bit simpler. |
1da177e4 | 135 | */ |
2d5eaa6d | 136 | |
438c4702 | 137 | static u8 sil_pata_udma_filter(ide_drive_t *drive) |
1da177e4 | 138 | { |
2d5eaa6d | 139 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 140 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 141 | unsigned long base = (unsigned long) hwif->hwif_data; |
2d5eaa6d | 142 | u8 mask = 0, scsc = 0; |
1da177e4 LT |
143 | |
144 | if (hwif->mmio) | |
145 | scsc = hwif->INB(base + 0x4A); | |
146 | else | |
36501650 | 147 | pci_read_config_byte(dev, 0x8A, &scsc); |
1da177e4 | 148 | |
1da177e4 | 149 | if ((scsc & 0x30) == 0x10) /* 133 */ |
438c4702 | 150 | mask = ATA_UDMA6; |
1da177e4 | 151 | else if ((scsc & 0x30) == 0x20) /* 2xPCI */ |
438c4702 | 152 | mask = ATA_UDMA6; |
1da177e4 | 153 | else if ((scsc & 0x30) == 0x00) /* 100 */ |
438c4702 | 154 | mask = ATA_UDMA5; |
1da177e4 LT |
155 | else /* Disabled ? */ |
156 | BUG(); | |
438c4702 | 157 | |
2d5eaa6d | 158 | return mask; |
1da177e4 LT |
159 | } |
160 | ||
438c4702 BZ |
161 | static u8 sil_sata_udma_filter(ide_drive_t *drive) |
162 | { | |
163 | return strstr(drive->id->model, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6; | |
164 | } | |
165 | ||
1da177e4 | 166 | /** |
88b2b32b BZ |
167 | * sil_set_pio_mode - set host controller for PIO mode |
168 | * @drive: drive | |
169 | * @pio: PIO mode number | |
1da177e4 LT |
170 | * |
171 | * Load the timing settings for this device mode into the | |
172 | * controller. If we are in PIO mode 3 or 4 turn on IORDY | |
173 | * monitoring (bit 9). The TF timing is bits 31:16 | |
174 | */ | |
328dcbb6 | 175 | |
88b2b32b | 176 | static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) |
1da177e4 | 177 | { |
328dcbb6 BZ |
178 | const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; |
179 | const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; | |
180 | ||
1da177e4 | 181 | ide_hwif_t *hwif = HWIF(drive); |
a87a87cc | 182 | ide_drive_t *pair = ide_get_paired_drive(drive); |
1da177e4 LT |
183 | u32 speedt = 0; |
184 | u16 speedp = 0; | |
185 | unsigned long addr = siimage_seldev(drive, 0x04); | |
186 | unsigned long tfaddr = siimage_selreg(hwif, 0x02); | |
ffe5415c | 187 | unsigned long base = (unsigned long)hwif->hwif_data; |
328dcbb6 | 188 | u8 tf_pio = pio; |
ffe5415c BZ |
189 | u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84) |
190 | : (hwif->mmio ? 0xB4 : 0x80); | |
191 | u8 mode = 0; | |
192 | u8 unit = drive->select.b.unit; | |
328dcbb6 BZ |
193 | |
194 | /* trim *taskfile* PIO to the slowest of the master/slave */ | |
195 | if (pair->present) { | |
2134758d | 196 | u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); |
328dcbb6 BZ |
197 | |
198 | if (pair_pio < tf_pio) | |
199 | tf_pio = pair_pio; | |
1da177e4 | 200 | } |
075cb655 | 201 | |
328dcbb6 BZ |
202 | /* cheat for now and use the docs */ |
203 | speedp = data_speed[pio]; | |
204 | speedt = tf_speed[tf_pio]; | |
205 | ||
075cb655 SS |
206 | if (hwif->mmio) { |
207 | hwif->OUTW(speedp, addr); | |
208 | hwif->OUTW(speedt, tfaddr); | |
1da177e4 | 209 | /* Now set up IORDY */ |
328dcbb6 | 210 | if (pio > 2) |
1da177e4 LT |
211 | hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2); |
212 | else | |
213 | hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2); | |
ffe5415c BZ |
214 | |
215 | mode = hwif->INB(base + addr_mask); | |
216 | mode &= ~(unit ? 0x30 : 0x03); | |
217 | mode |= (unit ? 0x10 : 0x01); | |
218 | hwif->OUTB(mode, base + addr_mask); | |
075cb655 | 219 | } else { |
36501650 BZ |
220 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
221 | ||
222 | pci_write_config_word(dev, addr, speedp); | |
223 | pci_write_config_word(dev, tfaddr, speedt); | |
224 | pci_read_config_word(dev, tfaddr - 2, &speedp); | |
1da177e4 LT |
225 | speedp &= ~0x200; |
226 | /* Set IORDY for mode 3 or 4 */ | |
328dcbb6 | 227 | if (pio > 2) |
1da177e4 | 228 | speedp |= 0x200; |
36501650 | 229 | pci_write_config_word(dev, tfaddr - 2, speedp); |
ffe5415c | 230 | |
36501650 | 231 | pci_read_config_byte(dev, addr_mask, &mode); |
ffe5415c BZ |
232 | mode &= ~(unit ? 0x30 : 0x03); |
233 | mode |= (unit ? 0x10 : 0x01); | |
36501650 | 234 | pci_write_config_byte(dev, addr_mask, mode); |
1da177e4 LT |
235 | } |
236 | } | |
237 | ||
1da177e4 | 238 | /** |
88b2b32b BZ |
239 | * sil_set_dma_mode - set host controller for DMA mode |
240 | * @drive: drive | |
241 | * @speed: DMA mode | |
1da177e4 | 242 | * |
88b2b32b | 243 | * Tune the SiI chipset for the desired DMA mode. |
1da177e4 | 244 | */ |
f212ff28 | 245 | |
88b2b32b | 246 | static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
247 | { |
248 | u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; | |
249 | u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
250 | u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
251 | ||
252 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 253 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
254 | u16 ultra = 0, multi = 0; |
255 | u8 mode = 0, unit = drive->select.b.unit; | |
1da177e4 LT |
256 | unsigned long base = (unsigned long)hwif->hwif_data; |
257 | u8 scsc = 0, addr_mask = ((hwif->channel) ? | |
258 | ((hwif->mmio) ? 0xF4 : 0x84) : | |
259 | ((hwif->mmio) ? 0xB4 : 0x80)); | |
260 | ||
261 | unsigned long ma = siimage_seldev(drive, 0x08); | |
262 | unsigned long ua = siimage_seldev(drive, 0x0C); | |
263 | ||
264 | if (hwif->mmio) { | |
265 | scsc = hwif->INB(base + 0x4A); | |
266 | mode = hwif->INB(base + addr_mask); | |
267 | multi = hwif->INW(ma); | |
268 | ultra = hwif->INW(ua); | |
269 | } else { | |
36501650 BZ |
270 | pci_read_config_byte(dev, 0x8A, &scsc); |
271 | pci_read_config_byte(dev, addr_mask, &mode); | |
272 | pci_read_config_word(dev, ma, &multi); | |
273 | pci_read_config_word(dev, ua, &ultra); | |
1da177e4 LT |
274 | } |
275 | ||
276 | mode &= ~((unit) ? 0x30 : 0x03); | |
277 | ultra &= ~0x3F; | |
278 | scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; | |
279 | ||
280 | scsc = is_sata(hwif) ? 1 : scsc; | |
281 | ||
4db90a14 BZ |
282 | if (speed >= XFER_UDMA_0) { |
283 | multi = dma[2]; | |
284 | ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] : | |
285 | ultra5[speed - XFER_UDMA_0]); | |
286 | mode |= (unit ? 0x30 : 0x03); | |
287 | } else { | |
288 | multi = dma[speed - XFER_MW_DMA_0]; | |
289 | mode |= (unit ? 0x20 : 0x02); | |
1da177e4 LT |
290 | } |
291 | ||
292 | if (hwif->mmio) { | |
293 | hwif->OUTB(mode, base + addr_mask); | |
294 | hwif->OUTW(multi, ma); | |
295 | hwif->OUTW(ultra, ua); | |
296 | } else { | |
36501650 BZ |
297 | pci_write_config_byte(dev, addr_mask, mode); |
298 | pci_write_config_word(dev, ma, multi); | |
299 | pci_write_config_word(dev, ua, ultra); | |
1da177e4 | 300 | } |
1da177e4 LT |
301 | } |
302 | ||
1da177e4 | 303 | /* returns 1 if dma irq issued, 0 otherwise */ |
5e37bdc0 | 304 | static int siimage_io_dma_test_irq(ide_drive_t *drive) |
1da177e4 LT |
305 | { |
306 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 307 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
308 | u8 dma_altstat = 0; |
309 | unsigned long addr = siimage_selreg(hwif, 1); | |
310 | ||
311 | /* return 1 if INTR asserted */ | |
312 | if ((hwif->INB(hwif->dma_status) & 4) == 4) | |
313 | return 1; | |
314 | ||
315 | /* return 1 if Device INTR asserted */ | |
36501650 | 316 | pci_read_config_byte(dev, addr, &dma_altstat); |
1da177e4 LT |
317 | if (dma_altstat & 8) |
318 | return 0; //return 1; | |
319 | return 0; | |
320 | } | |
321 | ||
1da177e4 | 322 | /** |
5e37bdc0 | 323 | * siimage_mmio_dma_test_irq - check we caused an IRQ |
1da177e4 LT |
324 | * @drive: drive we are testing |
325 | * | |
326 | * Check if we caused an IDE DMA interrupt. We may also have caused | |
327 | * SATA status interrupts, if so we clean them up and continue. | |
328 | */ | |
5e37bdc0 BZ |
329 | |
330 | static int siimage_mmio_dma_test_irq(ide_drive_t *drive) | |
1da177e4 LT |
331 | { |
332 | ide_hwif_t *hwif = HWIF(drive); | |
1da177e4 | 333 | unsigned long addr = siimage_selreg(hwif, 0x1); |
835457de BZ |
334 | void __iomem *sata_error_addr |
335 | = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET]; | |
1da177e4 | 336 | |
835457de | 337 | if (sata_error_addr) { |
438c4702 | 338 | unsigned long base = (unsigned long)hwif->hwif_data; |
0ecdca26 | 339 | u32 ext_stat = readl((void __iomem *)(base + 0x10)); |
1da177e4 | 340 | u8 watchdog = 0; |
835457de | 341 | |
1da177e4 | 342 | if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { |
835457de BZ |
343 | u32 sata_error = readl(sata_error_addr); |
344 | ||
345 | writel(sata_error, sata_error_addr); | |
1da177e4 | 346 | watchdog = (sata_error & 0x00680000) ? 1 : 0; |
1da177e4 LT |
347 | printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
348 | "watchdog = %d, %s\n", | |
349 | drive->name, sata_error, watchdog, | |
eb63963a | 350 | __func__); |
1da177e4 LT |
351 | |
352 | } else { | |
353 | watchdog = (ext_stat & 0x8000) ? 1 : 0; | |
354 | } | |
355 | ext_stat >>= 16; | |
356 | ||
357 | if (!(ext_stat & 0x0404) && !watchdog) | |
358 | return 0; | |
359 | } | |
360 | ||
361 | /* return 1 if INTR asserted */ | |
0ecdca26 | 362 | if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04) |
1da177e4 LT |
363 | return 1; |
364 | ||
365 | /* return 1 if Device INTR asserted */ | |
0ecdca26 | 366 | if ((readb((void __iomem *)addr) & 8) == 8) |
1da177e4 LT |
367 | return 0; //return 1; |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
5e37bdc0 BZ |
372 | static int siimage_dma_test_irq(ide_drive_t *drive) |
373 | { | |
374 | if (drive->hwif->mmio) | |
375 | return siimage_mmio_dma_test_irq(drive); | |
376 | else | |
377 | return siimage_io_dma_test_irq(drive); | |
378 | } | |
379 | ||
1da177e4 | 380 | /** |
438c4702 | 381 | * sil_sata_reset_poll - wait for SATA reset |
1da177e4 LT |
382 | * @drive: drive we are resetting |
383 | * | |
384 | * Poll the SATA phy and see whether it has come back from the dead | |
385 | * yet. | |
386 | */ | |
438c4702 BZ |
387 | |
388 | static int sil_sata_reset_poll(ide_drive_t *drive) | |
1da177e4 | 389 | { |
835457de BZ |
390 | ide_hwif_t *hwif = drive->hwif; |
391 | void __iomem *sata_status_addr | |
392 | = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET]; | |
393 | ||
394 | if (sata_status_addr) { | |
395 | /* SATA Status is available only when in MMIO mode */ | |
396 | u32 sata_stat = readl(sata_status_addr); | |
1da177e4 | 397 | |
835457de | 398 | if ((sata_stat & 0x03) != 0x03) { |
1da177e4 | 399 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", |
835457de | 400 | hwif->name, sata_stat); |
1da177e4 LT |
401 | HWGROUP(drive)->polling = 0; |
402 | return ide_started; | |
403 | } | |
1da177e4 | 404 | } |
438c4702 BZ |
405 | |
406 | return 0; | |
1da177e4 LT |
407 | } |
408 | ||
409 | /** | |
438c4702 | 410 | * sil_sata_pre_reset - reset hook |
1da177e4 LT |
411 | * @drive: IDE device being reset |
412 | * | |
413 | * For the SATA devices we need to handle recalibration/geometry | |
414 | * differently | |
415 | */ | |
1da177e4 | 416 | |
438c4702 BZ |
417 | static void sil_sata_pre_reset(ide_drive_t *drive) |
418 | { | |
419 | if (drive->media == ide_disk) { | |
1da177e4 LT |
420 | drive->special.b.set_geometry = 0; |
421 | drive->special.b.recalibrate = 0; | |
422 | } | |
423 | } | |
424 | ||
1da177e4 LT |
425 | /** |
426 | * proc_reports_siimage - add siimage controller to proc | |
427 | * @dev: PCI device | |
428 | * @clocking: SCSC value | |
429 | * @name: controller name | |
430 | * | |
431 | * Report the clocking mode of the controller and add it to | |
432 | * the /proc interface layer | |
433 | */ | |
434 | ||
435 | static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name) | |
436 | { | |
437 | if (!pdev_is_sata(dev)) { | |
438 | printk(KERN_INFO "%s: BASE CLOCK ", name); | |
439 | clocking &= 0x03; | |
440 | switch (clocking) { | |
441 | case 0x03: printk("DISABLED!\n"); break; | |
442 | case 0x02: printk("== 2X PCI\n"); break; | |
443 | case 0x01: printk("== 133\n"); break; | |
444 | case 0x00: printk("== 100\n"); break; | |
445 | } | |
446 | } | |
447 | } | |
448 | ||
449 | /** | |
450 | * setup_mmio_siimage - switch an SI controller into MMIO | |
451 | * @dev: PCI device we are configuring | |
452 | * @name: device name | |
453 | * | |
454 | * Attempt to put the device into mmio mode. There are some slight | |
455 | * complications here with certain systems where the mmio bar isnt | |
456 | * mapped so we have to be sure we can fall back to I/O. | |
457 | */ | |
458 | ||
459 | static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name) | |
460 | { | |
c976816b | 461 | resource_size_t bar5 = pci_resource_start(dev, 5); |
1da177e4 LT |
462 | unsigned long barsize = pci_resource_len(dev, 5); |
463 | u8 tmpbyte = 0; | |
464 | void __iomem *ioaddr; | |
d868dd19 | 465 | u32 tmp, irq_mask; |
1da177e4 LT |
466 | |
467 | /* | |
468 | * Drop back to PIO if we can't map the mmio. Some | |
469 | * systems seem to get terminally confused in the PCI | |
470 | * spaces. | |
471 | */ | |
472 | ||
473 | if(!request_mem_region(bar5, barsize, name)) | |
474 | { | |
475 | printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n"); | |
476 | return 0; | |
477 | } | |
478 | ||
479 | ioaddr = ioremap(bar5, barsize); | |
480 | ||
481 | if (ioaddr == NULL) | |
482 | { | |
483 | release_mem_region(bar5, barsize); | |
484 | return 0; | |
485 | } | |
486 | ||
487 | pci_set_master(dev); | |
488 | pci_set_drvdata(dev, (void *) ioaddr); | |
489 | ||
490 | if (pdev_is_sata(dev)) { | |
d868dd19 JL |
491 | /* make sure IDE0/1 interrupts are not masked */ |
492 | irq_mask = (1 << 22) | (1 << 23); | |
493 | tmp = readl(ioaddr + 0x48); | |
494 | if (tmp & irq_mask) { | |
495 | tmp &= ~irq_mask; | |
496 | writel(tmp, ioaddr + 0x48); | |
497 | readl(ioaddr + 0x48); /* flush */ | |
498 | } | |
1da177e4 LT |
499 | writel(0, ioaddr + 0x148); |
500 | writel(0, ioaddr + 0x1C8); | |
501 | } | |
502 | ||
503 | writeb(0, ioaddr + 0xB4); | |
504 | writeb(0, ioaddr + 0xF4); | |
505 | tmpbyte = readb(ioaddr + 0x4A); | |
506 | ||
507 | switch(tmpbyte & 0x30) { | |
508 | case 0x00: | |
509 | /* In 100 MHz clocking, try and switch to 133 */ | |
510 | writeb(tmpbyte|0x10, ioaddr + 0x4A); | |
511 | break; | |
512 | case 0x10: | |
513 | /* On 133Mhz clocking */ | |
514 | break; | |
515 | case 0x20: | |
516 | /* On PCIx2 clocking */ | |
517 | break; | |
518 | case 0x30: | |
519 | /* Clocking is disabled */ | |
520 | /* 133 clock attempt to force it on */ | |
521 | writeb(tmpbyte & ~0x20, ioaddr + 0x4A); | |
522 | break; | |
523 | } | |
524 | ||
525 | writeb( 0x72, ioaddr + 0xA1); | |
526 | writew( 0x328A, ioaddr + 0xA2); | |
527 | writel(0x62DD62DD, ioaddr + 0xA4); | |
528 | writel(0x43924392, ioaddr + 0xA8); | |
529 | writel(0x40094009, ioaddr + 0xAC); | |
530 | writeb( 0x72, ioaddr + 0xE1); | |
531 | writew( 0x328A, ioaddr + 0xE2); | |
532 | writel(0x62DD62DD, ioaddr + 0xE4); | |
533 | writel(0x43924392, ioaddr + 0xE8); | |
534 | writel(0x40094009, ioaddr + 0xEC); | |
535 | ||
536 | if (pdev_is_sata(dev)) { | |
537 | writel(0xFFFF0000, ioaddr + 0x108); | |
538 | writel(0xFFFF0000, ioaddr + 0x188); | |
539 | writel(0x00680000, ioaddr + 0x148); | |
540 | writel(0x00680000, ioaddr + 0x1C8); | |
541 | } | |
542 | ||
543 | tmpbyte = readb(ioaddr + 0x4A); | |
544 | ||
545 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
546 | return 1; | |
547 | } | |
548 | ||
549 | /** | |
550 | * init_chipset_siimage - set up an SI device | |
551 | * @dev: PCI device | |
552 | * @name: device name | |
553 | * | |
554 | * Perform the initial PCI set up for this device. Attempt to switch | |
555 | * to 133MHz clocking if the system isn't already set up to do it. | |
556 | */ | |
557 | ||
558 | static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name) | |
559 | { | |
fc212bb1 | 560 | u8 rev = dev->revision, tmpbyte = 0, BA5_EN = 0; |
1da177e4 | 561 | |
fc212bb1 | 562 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255); |
1da177e4 LT |
563 | |
564 | pci_read_config_byte(dev, 0x8A, &BA5_EN); | |
565 | if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) { | |
566 | if (setup_mmio_siimage(dev, name)) { | |
567 | return 0; | |
568 | } | |
569 | } | |
570 | ||
571 | pci_write_config_byte(dev, 0x80, 0x00); | |
572 | pci_write_config_byte(dev, 0x84, 0x00); | |
573 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
574 | switch(tmpbyte & 0x30) { | |
575 | case 0x00: | |
576 | /* 133 clock attempt to force it on */ | |
577 | pci_write_config_byte(dev, 0x8A, tmpbyte|0x10); | |
578 | case 0x30: | |
579 | /* if clocking is disabled */ | |
580 | /* 133 clock attempt to force it on */ | |
581 | pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20); | |
582 | case 0x10: | |
583 | /* 133 already */ | |
584 | break; | |
585 | case 0x20: | |
586 | /* BIOS set PCI x2 clocking */ | |
587 | break; | |
588 | } | |
589 | ||
590 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
591 | ||
592 | pci_write_config_byte(dev, 0xA1, 0x72); | |
593 | pci_write_config_word(dev, 0xA2, 0x328A); | |
594 | pci_write_config_dword(dev, 0xA4, 0x62DD62DD); | |
595 | pci_write_config_dword(dev, 0xA8, 0x43924392); | |
596 | pci_write_config_dword(dev, 0xAC, 0x40094009); | |
597 | pci_write_config_byte(dev, 0xB1, 0x72); | |
598 | pci_write_config_word(dev, 0xB2, 0x328A); | |
599 | pci_write_config_dword(dev, 0xB4, 0x62DD62DD); | |
600 | pci_write_config_dword(dev, 0xB8, 0x43924392); | |
601 | pci_write_config_dword(dev, 0xBC, 0x40094009); | |
602 | ||
603 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
604 | return 0; | |
605 | } | |
606 | ||
607 | /** | |
608 | * init_mmio_iops_siimage - set up the iops for MMIO | |
609 | * @hwif: interface to set up | |
610 | * | |
611 | * The basic setup here is fairly simple, we can use standard MMIO | |
612 | * operations. However we do have to set the taskfile register offsets | |
613 | * by hand as there isnt a standard defined layout for them this | |
614 | * time. | |
615 | * | |
616 | * The hardware supports buffered taskfiles and also some rather nice | |
19c1ef5f | 617 | * extended PRD tables. For better SI3112 support use the libata driver |
1da177e4 LT |
618 | */ |
619 | ||
620 | static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) | |
621 | { | |
36501650 | 622 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
623 | void *addr = pci_get_drvdata(dev); |
624 | u8 ch = hwif->channel; | |
625 | hw_regs_t hw; | |
626 | unsigned long base; | |
627 | ||
628 | /* | |
629 | * Fill in the basic HWIF bits | |
630 | */ | |
631 | ||
632 | default_hwif_mmiops(hwif); | |
633 | hwif->hwif_data = addr; | |
634 | ||
635 | /* | |
636 | * Now set up the hw. We have to do this ourselves as | |
59c51591 | 637 | * the MMIO layout isnt the same as the standard port |
1da177e4 LT |
638 | * based I/O |
639 | */ | |
640 | ||
641 | memset(&hw, 0, sizeof(hw_regs_t)); | |
642 | ||
643 | base = (unsigned long)addr; | |
644 | if (ch) | |
645 | base += 0xC0; | |
646 | else | |
647 | base += 0x80; | |
648 | ||
649 | /* | |
650 | * The buffered task file doesn't have status/control | |
651 | * so we can't currently use it sanely since we want to | |
652 | * use LBA48 mode. | |
653 | */ | |
1da177e4 LT |
654 | hw.io_ports[IDE_DATA_OFFSET] = base; |
655 | hw.io_ports[IDE_ERROR_OFFSET] = base + 1; | |
656 | hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2; | |
657 | hw.io_ports[IDE_SECTOR_OFFSET] = base + 3; | |
658 | hw.io_ports[IDE_LCYL_OFFSET] = base + 4; | |
659 | hw.io_ports[IDE_HCYL_OFFSET] = base + 5; | |
660 | hw.io_ports[IDE_SELECT_OFFSET] = base + 6; | |
661 | hw.io_ports[IDE_STATUS_OFFSET] = base + 7; | |
662 | hw.io_ports[IDE_CONTROL_OFFSET] = base + 10; | |
663 | ||
664 | hw.io_ports[IDE_IRQ_OFFSET] = 0; | |
665 | ||
666 | if (pdev_is_sata(dev)) { | |
667 | base = (unsigned long)addr; | |
668 | if (ch) | |
669 | base += 0x80; | |
670 | hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; | |
671 | hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; | |
672 | hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; | |
1da177e4 LT |
673 | } |
674 | ||
9239b333 | 675 | memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports)); |
1da177e4 | 676 | |
9239b333 | 677 | hwif->irq = dev->irq; |
1da177e4 | 678 | |
9239b333 | 679 | hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00); |
2ad1e558 BZ |
680 | |
681 | hwif->mmio = 1; | |
1da177e4 LT |
682 | } |
683 | ||
684 | static int is_dev_seagate_sata(ide_drive_t *drive) | |
685 | { | |
686 | const char *s = &drive->id->model[0]; | |
687 | unsigned len; | |
688 | ||
1da177e4 LT |
689 | len = strnlen(s, sizeof(drive->id->model)); |
690 | ||
691 | if ((len > 4) && (!memcmp(s, "ST", 2))) { | |
692 | if ((!memcmp(s + len - 2, "AS", 2)) || | |
693 | (!memcmp(s + len - 3, "ASL", 3))) { | |
694 | printk(KERN_INFO "%s: applying pessimistic Seagate " | |
695 | "errata fix\n", drive->name); | |
696 | return 1; | |
697 | } | |
698 | } | |
699 | return 0; | |
700 | } | |
701 | ||
702 | /** | |
f01393e4 BZ |
703 | * sil_quirkproc - post probe fixups |
704 | * @drive: drive | |
1da177e4 LT |
705 | * |
706 | * Called after drive probe we use this to decide whether the | |
707 | * Seagate fixup must be applied. This used to be in init_iops but | |
708 | * that can occur before we know what drives are present. | |
709 | */ | |
710 | ||
f01393e4 | 711 | static void __devinit sil_quirkproc(ide_drive_t *drive) |
1da177e4 | 712 | { |
f01393e4 BZ |
713 | ide_hwif_t *hwif = drive->hwif; |
714 | ||
1da177e4 | 715 | /* Try and raise the rqsize */ |
f01393e4 | 716 | if (!is_sata(hwif) || !is_dev_seagate_sata(drive)) |
1da177e4 LT |
717 | hwif->rqsize = 128; |
718 | } | |
719 | ||
720 | /** | |
721 | * init_iops_siimage - set up iops | |
722 | * @hwif: interface to set up | |
723 | * | |
724 | * Do the basic setup for the SIIMAGE hardware interface | |
725 | * and then do the MMIO setup if we can. This is the first | |
726 | * look in we get for setting up the hwif so that we | |
727 | * can get the iops right before using them. | |
728 | */ | |
729 | ||
730 | static void __devinit init_iops_siimage(ide_hwif_t *hwif) | |
731 | { | |
36501650 BZ |
732 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
733 | ||
1da177e4 LT |
734 | hwif->hwif_data = NULL; |
735 | ||
736 | /* Pessimal until we finish probing */ | |
737 | hwif->rqsize = 15; | |
738 | ||
36501650 | 739 | if (pci_get_drvdata(dev) == NULL) |
1da177e4 | 740 | return; |
fc212bb1 | 741 | |
1da177e4 LT |
742 | init_mmio_iops_siimage(hwif); |
743 | } | |
744 | ||
745 | /** | |
ac95beed | 746 | * sil_cable_detect - cable detection |
1da177e4 LT |
747 | * @hwif: interface to check |
748 | * | |
749 | * Check for the presence of an ATA66 capable cable on the | |
750 | * interface. | |
751 | */ | |
752 | ||
ac95beed | 753 | static u8 __devinit sil_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 754 | { |
36501650 | 755 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 756 | unsigned long addr = siimage_selreg(hwif, 0); |
49521f97 BZ |
757 | u8 ata66 = 0; |
758 | ||
36501650 BZ |
759 | if (pci_get_drvdata(dev) == NULL) |
760 | pci_read_config_byte(dev, addr, &ata66); | |
49521f97 BZ |
761 | else |
762 | ata66 = hwif->INB(addr); | |
1da177e4 | 763 | |
49521f97 | 764 | return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
1da177e4 LT |
765 | } |
766 | ||
ac95beed BZ |
767 | static const struct ide_port_ops sil_pata_port_ops = { |
768 | .set_pio_mode = sil_set_pio_mode, | |
769 | .set_dma_mode = sil_set_dma_mode, | |
770 | .quirkproc = sil_quirkproc, | |
771 | .udma_filter = sil_pata_udma_filter, | |
772 | .cable_detect = sil_cable_detect, | |
773 | }; | |
774 | ||
775 | static const struct ide_port_ops sil_sata_port_ops = { | |
776 | .set_pio_mode = sil_set_pio_mode, | |
777 | .set_dma_mode = sil_set_dma_mode, | |
778 | .reset_poll = sil_sata_reset_poll, | |
779 | .pre_reset = sil_sata_pre_reset, | |
780 | .quirkproc = sil_quirkproc, | |
781 | .udma_filter = sil_sata_udma_filter, | |
782 | .cable_detect = sil_cable_detect, | |
783 | }; | |
784 | ||
5e37bdc0 BZ |
785 | static struct ide_dma_ops sil_dma_ops = { |
786 | .dma_test_irq = siimage_dma_test_irq, | |
787 | }; | |
788 | ||
ac95beed | 789 | #define DECLARE_SII_DEV(name_str, p_ops) \ |
1da177e4 LT |
790 | { \ |
791 | .name = name_str, \ | |
792 | .init_chipset = init_chipset_siimage, \ | |
793 | .init_iops = init_iops_siimage, \ | |
ac95beed | 794 | .port_ops = p_ops, \ |
5e37bdc0 | 795 | .dma_ops = &sil_dma_ops, \ |
4099d143 | 796 | .pio_mask = ATA_PIO4, \ |
5f8b6c34 BZ |
797 | .mwdma_mask = ATA_MWDMA2, \ |
798 | .udma_mask = ATA_UDMA6, \ | |
1da177e4 LT |
799 | } |
800 | ||
85620436 | 801 | static const struct ide_port_info siimage_chipsets[] __devinitdata = { |
ac95beed BZ |
802 | /* 0 */ DECLARE_SII_DEV("SiI680", &sil_pata_port_ops), |
803 | /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA", &sil_sata_port_ops), | |
804 | /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA", &sil_sata_port_ops) | |
1da177e4 LT |
805 | }; |
806 | ||
807 | /** | |
808 | * siimage_init_one - pci layer discovery entry | |
809 | * @dev: PCI device | |
810 | * @id: ident table entry | |
811 | * | |
812 | * Called by the PCI code when it finds an SI680 or SI3112 controller. | |
813 | * We then use the IDE PCI generic helper to do most of the work. | |
814 | */ | |
815 | ||
816 | static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
817 | { | |
5e37bdc0 BZ |
818 | struct ide_port_info d; |
819 | u8 idx = id->driver_data; | |
820 | ||
821 | d = siimage_chipsets[idx]; | |
822 | ||
823 | if (idx) { | |
824 | static int first = 1; | |
825 | ||
826 | if (first) { | |
827 | printk(KERN_INFO "siimage: For full SATA support you " | |
828 | "should use the libata sata_sil module.\n"); | |
829 | first = 0; | |
830 | } | |
831 | ||
832 | d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA; | |
833 | } | |
834 | ||
835 | return ide_setup_pci_device(dev, &d); | |
1da177e4 LT |
836 | } |
837 | ||
9cbcc5e3 BZ |
838 | static const struct pci_device_id siimage_pci_tbl[] = { |
839 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 }, | |
1da177e4 | 840 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
9cbcc5e3 BZ |
841 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 }, |
842 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 2 }, | |
1da177e4 LT |
843 | #endif |
844 | { 0, }, | |
845 | }; | |
846 | MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); | |
847 | ||
848 | static struct pci_driver driver = { | |
849 | .name = "SiI_IDE", | |
850 | .id_table = siimage_pci_tbl, | |
851 | .probe = siimage_init_one, | |
852 | }; | |
853 | ||
82ab1eec | 854 | static int __init siimage_ide_init(void) |
1da177e4 LT |
855 | { |
856 | return ide_pci_register_driver(&driver); | |
857 | } | |
858 | ||
859 | module_init(siimage_ide_init); | |
860 | ||
861 | MODULE_AUTHOR("Andre Hedrick, Alan Cox"); | |
862 | MODULE_DESCRIPTION("PCI driver module for SiI IDE"); | |
863 | MODULE_LICENSE("GPL"); |