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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
7b255436 | 4 | * Copyright (C) 2007-2008 MontaVista Software, Inc. |
165701d9 | 5 | * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
6 | * |
7 | * May be copied or modified under the terms of the GNU General Public License | |
8 | * | |
bf4c796d JG |
9 | * Documentation for CMD680: |
10 | * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 | |
11 | * | |
12 | * Documentation for SiI 3112: | |
13 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
14 | * | |
15 | * Errata and other documentation only available under NDA. | |
1da177e4 LT |
16 | * |
17 | * | |
18 | * FAQ Items: | |
19 | * If you are using Marvell SATA-IDE adapters with Maxtor drives | |
7b255436 | 20 | * ensure the system is set up for ATA100/UDMA5, not UDMA6. |
1da177e4 LT |
21 | * |
22 | * If you are using WD drives with SATA bridges you must set the | |
7b255436 | 23 | * drive to "Single". "Master" will hang. |
1da177e4 LT |
24 | * |
25 | * If you have strange problems with nVidia chipset systems please | |
26 | * see the SI support documentation and update your system BIOS | |
3a4fa0a2 | 27 | * if necessary |
8693d3e4 AC |
28 | * |
29 | * The Dell DRAC4 has some interesting features including effectively hot | |
30 | * unplugging/replugging the virtual CD interface when the DRAC is reset. | |
31 | * This often causes drivers/ide/siimage to panic but is ok with the rather | |
32 | * smarter code in libata. | |
328dcbb6 BZ |
33 | * |
34 | * TODO: | |
35 | * - IORDY fixes | |
36 | * - VDMA support | |
1da177e4 LT |
37 | */ |
38 | ||
1da177e4 LT |
39 | #include <linux/types.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/pci.h> | |
1da177e4 LT |
42 | #include <linux/hdreg.h> |
43 | #include <linux/ide.h> | |
44 | #include <linux/init.h> | |
7b255436 | 45 | #include <linux/io.h> |
1da177e4 | 46 | |
1da177e4 LT |
47 | /** |
48 | * pdev_is_sata - check if device is SATA | |
49 | * @pdev: PCI device to check | |
7b255436 | 50 | * |
1da177e4 LT |
51 | * Returns true if this is a SATA controller |
52 | */ | |
7b255436 | 53 | |
1da177e4 LT |
54 | static int pdev_is_sata(struct pci_dev *pdev) |
55 | { | |
438c4702 | 56 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
7b255436 SS |
57 | switch (pdev->device) { |
58 | case PCI_DEVICE_ID_SII_3112: | |
59 | case PCI_DEVICE_ID_SII_1210SA: | |
60 | return 1; | |
61 | case PCI_DEVICE_ID_SII_680: | |
62 | return 0; | |
1da177e4 LT |
63 | } |
64 | BUG(); | |
438c4702 | 65 | #endif |
1da177e4 LT |
66 | return 0; |
67 | } | |
438c4702 | 68 | |
1da177e4 LT |
69 | /** |
70 | * is_sata - check if hwif is SATA | |
71 | * @hwif: interface to check | |
7b255436 | 72 | * |
1da177e4 LT |
73 | * Returns true if this is a SATA controller |
74 | */ | |
7b255436 | 75 | |
1da177e4 LT |
76 | static inline int is_sata(ide_hwif_t *hwif) |
77 | { | |
36501650 | 78 | return pdev_is_sata(to_pci_dev(hwif->dev)); |
1da177e4 LT |
79 | } |
80 | ||
81 | /** | |
82 | * siimage_selreg - return register base | |
83 | * @hwif: interface | |
84 | * @r: config offset | |
85 | * | |
86 | * Turn a config register offset into the right address in either | |
87 | * PCI space or MMIO space to access the control register in question | |
7b255436 SS |
88 | * Thankfully this is a configuration operation, so isn't performance |
89 | * critical. | |
1da177e4 | 90 | */ |
7b255436 | 91 | |
1da177e4 LT |
92 | static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) |
93 | { | |
94 | unsigned long base = (unsigned long)hwif->hwif_data; | |
7b255436 | 95 | |
1da177e4 | 96 | base += 0xA0 + r; |
13572144 | 97 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
7b255436 | 98 | base += hwif->channel << 6; |
1da177e4 | 99 | else |
7b255436 | 100 | base += hwif->channel << 4; |
1da177e4 LT |
101 | return base; |
102 | } | |
7b255436 | 103 | |
1da177e4 LT |
104 | /** |
105 | * siimage_seldev - return register base | |
106 | * @hwif: interface | |
107 | * @r: config offset | |
108 | * | |
109 | * Turn a config register offset into the right address in either | |
110 | * PCI space or MMIO space to access the control register in question | |
111 | * including accounting for the unit shift. | |
112 | */ | |
7b255436 | 113 | |
1da177e4 LT |
114 | static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) |
115 | { | |
116 | ide_hwif_t *hwif = HWIF(drive); | |
7b255436 SS |
117 | unsigned long base = (unsigned long)hwif->hwif_data; |
118 | ||
1da177e4 | 119 | base += 0xA0 + r; |
13572144 | 120 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
7b255436 | 121 | base += hwif->channel << 6; |
1da177e4 | 122 | else |
7b255436 | 123 | base += hwif->channel << 4; |
1da177e4 LT |
124 | base |= drive->select.b.unit << drive->select.b.unit; |
125 | return base; | |
126 | } | |
127 | ||
165701d9 BZ |
128 | static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr) |
129 | { | |
130 | u8 tmp = 0; | |
131 | ||
132 | if (pci_get_drvdata(dev)) | |
133 | tmp = readb((void __iomem *)addr); | |
134 | else | |
135 | pci_read_config_byte(dev, addr, &tmp); | |
136 | ||
137 | return tmp; | |
138 | } | |
139 | ||
140 | static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr) | |
141 | { | |
142 | u16 tmp = 0; | |
143 | ||
144 | if (pci_get_drvdata(dev)) | |
145 | tmp = readw((void __iomem *)addr); | |
146 | else | |
147 | pci_read_config_word(dev, addr, &tmp); | |
148 | ||
149 | return tmp; | |
150 | } | |
151 | ||
152 | static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr) | |
153 | { | |
154 | if (pci_get_drvdata(dev)) | |
155 | writeb(val, (void __iomem *)addr); | |
156 | else | |
157 | pci_write_config_byte(dev, addr, val); | |
158 | } | |
159 | ||
160 | static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr) | |
161 | { | |
162 | if (pci_get_drvdata(dev)) | |
163 | writew(val, (void __iomem *)addr); | |
164 | else | |
165 | pci_write_config_word(dev, addr, val); | |
166 | } | |
167 | ||
168 | static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr) | |
169 | { | |
170 | if (pci_get_drvdata(dev)) | |
171 | writel(val, (void __iomem *)addr); | |
172 | else | |
173 | pci_write_config_dword(dev, addr, val); | |
174 | } | |
175 | ||
1da177e4 | 176 | /** |
2d5eaa6d BZ |
177 | * sil_udma_filter - compute UDMA mask |
178 | * @drive: IDE device | |
179 | * | |
180 | * Compute the available UDMA speeds for the device on the interface. | |
1da177e4 | 181 | * |
1da177e4 | 182 | * For the CMD680 this depends on the clocking mode (scsc), for the |
2d5eaa6d | 183 | * SI3112 SATA controller life is a bit simpler. |
1da177e4 | 184 | */ |
2d5eaa6d | 185 | |
438c4702 | 186 | static u8 sil_pata_udma_filter(ide_drive_t *drive) |
1da177e4 | 187 | { |
7b255436 SS |
188 | ide_hwif_t *hwif = drive->hwif; |
189 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
190 | unsigned long base = (unsigned long)hwif->hwif_data; | |
191 | u8 scsc, mask = 0; | |
1da177e4 | 192 | |
13572144 BZ |
193 | base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A; |
194 | ||
195 | scsc = sil_ioread8(dev, base); | |
1da177e4 | 196 | |
7b255436 SS |
197 | switch (scsc & 0x30) { |
198 | case 0x10: /* 133 */ | |
438c4702 | 199 | mask = ATA_UDMA6; |
7b255436 SS |
200 | break; |
201 | case 0x20: /* 2xPCI */ | |
438c4702 | 202 | mask = ATA_UDMA6; |
7b255436 SS |
203 | break; |
204 | case 0x00: /* 100 */ | |
438c4702 | 205 | mask = ATA_UDMA5; |
7b255436 SS |
206 | break; |
207 | default: /* Disabled ? */ | |
1da177e4 | 208 | BUG(); |
7b255436 | 209 | } |
438c4702 | 210 | |
2d5eaa6d | 211 | return mask; |
1da177e4 LT |
212 | } |
213 | ||
438c4702 BZ |
214 | static u8 sil_sata_udma_filter(ide_drive_t *drive) |
215 | { | |
216 | return strstr(drive->id->model, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6; | |
217 | } | |
218 | ||
1da177e4 | 219 | /** |
88b2b32b BZ |
220 | * sil_set_pio_mode - set host controller for PIO mode |
221 | * @drive: drive | |
222 | * @pio: PIO mode number | |
1da177e4 LT |
223 | * |
224 | * Load the timing settings for this device mode into the | |
225 | * controller. If we are in PIO mode 3 or 4 turn on IORDY | |
226 | * monitoring (bit 9). The TF timing is bits 31:16 | |
227 | */ | |
328dcbb6 | 228 | |
88b2b32b | 229 | static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) |
1da177e4 | 230 | { |
7b255436 SS |
231 | static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; |
232 | static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; | |
328dcbb6 | 233 | |
1da177e4 | 234 | ide_hwif_t *hwif = HWIF(drive); |
165701d9 | 235 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
a87a87cc | 236 | ide_drive_t *pair = ide_get_paired_drive(drive); |
1da177e4 LT |
237 | u32 speedt = 0; |
238 | u16 speedp = 0; | |
239 | unsigned long addr = siimage_seldev(drive, 0x04); | |
7b255436 | 240 | unsigned long tfaddr = siimage_selreg(hwif, 0x02); |
ffe5415c | 241 | unsigned long base = (unsigned long)hwif->hwif_data; |
328dcbb6 | 242 | u8 tf_pio = pio; |
13572144 BZ |
243 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
244 | u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) | |
245 | : (mmio ? 0xB4 : 0x80); | |
ffe5415c BZ |
246 | u8 mode = 0; |
247 | u8 unit = drive->select.b.unit; | |
328dcbb6 BZ |
248 | |
249 | /* trim *taskfile* PIO to the slowest of the master/slave */ | |
250 | if (pair->present) { | |
2134758d | 251 | u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); |
328dcbb6 BZ |
252 | |
253 | if (pair_pio < tf_pio) | |
254 | tf_pio = pair_pio; | |
1da177e4 | 255 | } |
075cb655 | 256 | |
328dcbb6 BZ |
257 | /* cheat for now and use the docs */ |
258 | speedp = data_speed[pio]; | |
259 | speedt = tf_speed[tf_pio]; | |
260 | ||
165701d9 BZ |
261 | sil_iowrite16(dev, speedp, addr); |
262 | sil_iowrite16(dev, speedt, tfaddr); | |
263 | ||
264 | /* now set up IORDY */ | |
265 | speedp = sil_ioread16(dev, tfaddr - 2); | |
266 | speedp &= ~0x200; | |
267 | if (pio > 2) | |
268 | speedp |= 0x200; | |
269 | sil_iowrite16(dev, speedp, tfaddr - 2); | |
270 | ||
271 | mode = sil_ioread8(dev, base + addr_mask); | |
272 | mode &= ~(unit ? 0x30 : 0x03); | |
7b255436 | 273 | mode |= unit ? 0x10 : 0x01; |
165701d9 | 274 | sil_iowrite8(dev, mode, base + addr_mask); |
1da177e4 LT |
275 | } |
276 | ||
1da177e4 | 277 | /** |
88b2b32b BZ |
278 | * sil_set_dma_mode - set host controller for DMA mode |
279 | * @drive: drive | |
280 | * @speed: DMA mode | |
1da177e4 | 281 | * |
88b2b32b | 282 | * Tune the SiI chipset for the desired DMA mode. |
1da177e4 | 283 | */ |
f212ff28 | 284 | |
88b2b32b | 285 | static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 286 | { |
7b255436 SS |
287 | static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; |
288 | static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
289 | static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
1da177e4 LT |
290 | |
291 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 292 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
293 | u16 ultra = 0, multi = 0; |
294 | u8 mode = 0, unit = drive->select.b.unit; | |
1da177e4 | 295 | unsigned long base = (unsigned long)hwif->hwif_data; |
13572144 BZ |
296 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
297 | u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) | |
298 | : (mmio ? 0xB4 : 0x80); | |
1da177e4 LT |
299 | unsigned long ma = siimage_seldev(drive, 0x08); |
300 | unsigned long ua = siimage_seldev(drive, 0x0C); | |
301 | ||
13572144 | 302 | scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A)); |
7b255436 | 303 | mode = sil_ioread8 (dev, base + addr_mask); |
165701d9 BZ |
304 | multi = sil_ioread16(dev, ma); |
305 | ultra = sil_ioread16(dev, ua); | |
1da177e4 | 306 | |
7b255436 | 307 | mode &= ~(unit ? 0x30 : 0x03); |
1da177e4 LT |
308 | ultra &= ~0x3F; |
309 | scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; | |
310 | ||
311 | scsc = is_sata(hwif) ? 1 : scsc; | |
312 | ||
4db90a14 | 313 | if (speed >= XFER_UDMA_0) { |
7b255436 SS |
314 | multi = dma[2]; |
315 | ultra |= scsc ? ultra6[speed - XFER_UDMA_0] : | |
316 | ultra5[speed - XFER_UDMA_0]; | |
317 | mode |= unit ? 0x30 : 0x03; | |
4db90a14 BZ |
318 | } else { |
319 | multi = dma[speed - XFER_MW_DMA_0]; | |
7b255436 | 320 | mode |= unit ? 0x20 : 0x02; |
1da177e4 LT |
321 | } |
322 | ||
7b255436 | 323 | sil_iowrite8 (dev, mode, base + addr_mask); |
165701d9 BZ |
324 | sil_iowrite16(dev, multi, ma); |
325 | sil_iowrite16(dev, ultra, ua); | |
1da177e4 LT |
326 | } |
327 | ||
1da177e4 | 328 | /* returns 1 if dma irq issued, 0 otherwise */ |
5e37bdc0 | 329 | static int siimage_io_dma_test_irq(ide_drive_t *drive) |
1da177e4 LT |
330 | { |
331 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 332 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
333 | u8 dma_altstat = 0; |
334 | unsigned long addr = siimage_selreg(hwif, 1); | |
335 | ||
336 | /* return 1 if INTR asserted */ | |
7b255436 | 337 | if (hwif->INB(hwif->dma_status) & 4) |
1da177e4 LT |
338 | return 1; |
339 | ||
340 | /* return 1 if Device INTR asserted */ | |
36501650 | 341 | pci_read_config_byte(dev, addr, &dma_altstat); |
1da177e4 | 342 | if (dma_altstat & 8) |
7b255436 SS |
343 | return 0; /* return 1; */ |
344 | ||
1da177e4 LT |
345 | return 0; |
346 | } | |
347 | ||
1da177e4 | 348 | /** |
5e37bdc0 | 349 | * siimage_mmio_dma_test_irq - check we caused an IRQ |
1da177e4 LT |
350 | * @drive: drive we are testing |
351 | * | |
352 | * Check if we caused an IDE DMA interrupt. We may also have caused | |
353 | * SATA status interrupts, if so we clean them up and continue. | |
354 | */ | |
5e37bdc0 BZ |
355 | |
356 | static int siimage_mmio_dma_test_irq(ide_drive_t *drive) | |
1da177e4 LT |
357 | { |
358 | ide_hwif_t *hwif = HWIF(drive); | |
1da177e4 | 359 | unsigned long addr = siimage_selreg(hwif, 0x1); |
835457de BZ |
360 | void __iomem *sata_error_addr |
361 | = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET]; | |
1da177e4 | 362 | |
835457de | 363 | if (sata_error_addr) { |
7b255436 SS |
364 | unsigned long base = (unsigned long)hwif->hwif_data; |
365 | u32 ext_stat = readl((void __iomem *)(base + 0x10)); | |
366 | u8 watchdog = 0; | |
835457de | 367 | |
1da177e4 | 368 | if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { |
835457de BZ |
369 | u32 sata_error = readl(sata_error_addr); |
370 | ||
371 | writel(sata_error, sata_error_addr); | |
1da177e4 | 372 | watchdog = (sata_error & 0x00680000) ? 1 : 0; |
1da177e4 LT |
373 | printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
374 | "watchdog = %d, %s\n", | |
7b255436 SS |
375 | drive->name, sata_error, watchdog, __func__); |
376 | } else | |
1da177e4 | 377 | watchdog = (ext_stat & 0x8000) ? 1 : 0; |
1da177e4 | 378 | |
7b255436 | 379 | ext_stat >>= 16; |
1da177e4 LT |
380 | if (!(ext_stat & 0x0404) && !watchdog) |
381 | return 0; | |
382 | } | |
383 | ||
384 | /* return 1 if INTR asserted */ | |
7b255436 | 385 | if (readb((void __iomem *)hwif->dma_status) & 0x04) |
1da177e4 LT |
386 | return 1; |
387 | ||
388 | /* return 1 if Device INTR asserted */ | |
7b255436 SS |
389 | if (readb((void __iomem *)addr) & 8) |
390 | return 0; /* return 1; */ | |
1da177e4 LT |
391 | |
392 | return 0; | |
393 | } | |
394 | ||
5e37bdc0 BZ |
395 | static int siimage_dma_test_irq(ide_drive_t *drive) |
396 | { | |
13572144 | 397 | if (drive->hwif->host_flags & IDE_HFLAG_MMIO) |
5e37bdc0 BZ |
398 | return siimage_mmio_dma_test_irq(drive); |
399 | else | |
400 | return siimage_io_dma_test_irq(drive); | |
401 | } | |
402 | ||
1da177e4 | 403 | /** |
438c4702 | 404 | * sil_sata_reset_poll - wait for SATA reset |
1da177e4 LT |
405 | * @drive: drive we are resetting |
406 | * | |
407 | * Poll the SATA phy and see whether it has come back from the dead | |
408 | * yet. | |
409 | */ | |
438c4702 BZ |
410 | |
411 | static int sil_sata_reset_poll(ide_drive_t *drive) | |
1da177e4 | 412 | { |
835457de BZ |
413 | ide_hwif_t *hwif = drive->hwif; |
414 | void __iomem *sata_status_addr | |
415 | = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET]; | |
416 | ||
417 | if (sata_status_addr) { | |
418 | /* SATA Status is available only when in MMIO mode */ | |
419 | u32 sata_stat = readl(sata_status_addr); | |
1da177e4 | 420 | |
835457de | 421 | if ((sata_stat & 0x03) != 0x03) { |
1da177e4 | 422 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", |
835457de | 423 | hwif->name, sata_stat); |
1da177e4 LT |
424 | HWGROUP(drive)->polling = 0; |
425 | return ide_started; | |
426 | } | |
1da177e4 | 427 | } |
438c4702 BZ |
428 | |
429 | return 0; | |
1da177e4 LT |
430 | } |
431 | ||
432 | /** | |
438c4702 | 433 | * sil_sata_pre_reset - reset hook |
1da177e4 LT |
434 | * @drive: IDE device being reset |
435 | * | |
436 | * For the SATA devices we need to handle recalibration/geometry | |
437 | * differently | |
438 | */ | |
1da177e4 | 439 | |
438c4702 BZ |
440 | static void sil_sata_pre_reset(ide_drive_t *drive) |
441 | { | |
442 | if (drive->media == ide_disk) { | |
1da177e4 LT |
443 | drive->special.b.set_geometry = 0; |
444 | drive->special.b.recalibrate = 0; | |
445 | } | |
446 | } | |
447 | ||
1da177e4 | 448 | /** |
7b255436 | 449 | * setup_mmio_siimage - switch controller into MMIO mode |
1da177e4 LT |
450 | * @dev: PCI device we are configuring |
451 | * @name: device name | |
452 | * | |
7b255436 SS |
453 | * Attempt to put the device into MMIO mode. There are some slight |
454 | * complications here with certain systems where the MMIO BAR isn't | |
455 | * mapped, so we have to be sure that we can fall back to I/O. | |
1da177e4 | 456 | */ |
7b255436 SS |
457 | |
458 | static unsigned int setup_mmio_siimage(struct pci_dev *dev, const char *name) | |
1da177e4 | 459 | { |
c976816b | 460 | resource_size_t bar5 = pci_resource_start(dev, 5); |
1da177e4 | 461 | unsigned long barsize = pci_resource_len(dev, 5); |
1da177e4 LT |
462 | void __iomem *ioaddr; |
463 | ||
464 | /* | |
7b255436 SS |
465 | * Drop back to PIO if we can't map the MMIO. Some systems |
466 | * seem to get terminally confused in the PCI spaces. | |
1da177e4 | 467 | */ |
165701d9 | 468 | if (!request_mem_region(bar5, barsize, name)) { |
7b255436 SS |
469 | printk(KERN_WARNING "siimage: IDE controller MMIO ports not " |
470 | "available.\n"); | |
1da177e4 LT |
471 | return 0; |
472 | } | |
165701d9 | 473 | |
1da177e4 | 474 | ioaddr = ioremap(bar5, barsize); |
165701d9 | 475 | if (ioaddr == NULL) { |
1da177e4 LT |
476 | release_mem_region(bar5, barsize); |
477 | return 0; | |
478 | } | |
479 | ||
480 | pci_set_master(dev); | |
481 | pci_set_drvdata(dev, (void *) ioaddr); | |
482 | ||
1da177e4 LT |
483 | return 1; |
484 | } | |
485 | ||
486 | /** | |
487 | * init_chipset_siimage - set up an SI device | |
488 | * @dev: PCI device | |
489 | * @name: device name | |
490 | * | |
491 | * Perform the initial PCI set up for this device. Attempt to switch | |
7b255436 | 492 | * to 133 MHz clocking if the system isn't already set up to do it. |
1da177e4 LT |
493 | */ |
494 | ||
7b255436 SS |
495 | static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, |
496 | const char *name) | |
1da177e4 | 497 | { |
165701d9 BZ |
498 | unsigned long base, scsc_addr; |
499 | void __iomem *ioaddr = NULL; | |
7b255436 | 500 | u8 rev = dev->revision, tmp, BA5_EN; |
1da177e4 | 501 | |
fc212bb1 | 502 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255); |
1da177e4 LT |
503 | |
504 | pci_read_config_byte(dev, 0x8A, &BA5_EN); | |
165701d9 | 505 | |
7b255436 | 506 | if ((BA5_EN & 0x01) || pci_resource_start(dev, 5)) |
165701d9 BZ |
507 | if (setup_mmio_siimage(dev, name)) |
508 | ioaddr = pci_get_drvdata(dev); | |
165701d9 BZ |
509 | |
510 | base = (unsigned long)ioaddr; | |
511 | ||
512 | if (ioaddr && pdev_is_sata(dev)) { | |
513 | u32 tmp32, irq_mask; | |
514 | ||
515 | /* make sure IDE0/1 interrupts are not masked */ | |
516 | irq_mask = (1 << 22) | (1 << 23); | |
517 | tmp32 = readl(ioaddr + 0x48); | |
518 | if (tmp32 & irq_mask) { | |
519 | tmp32 &= ~irq_mask; | |
520 | writel(tmp32, ioaddr + 0x48); | |
521 | readl(ioaddr + 0x48); /* flush */ | |
1da177e4 | 522 | } |
165701d9 BZ |
523 | writel(0, ioaddr + 0x148); |
524 | writel(0, ioaddr + 0x1C8); | |
1da177e4 LT |
525 | } |
526 | ||
165701d9 BZ |
527 | sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80); |
528 | sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84); | |
529 | ||
530 | scsc_addr = base ? (base + 0x4A) : 0x8A; | |
531 | tmp = sil_ioread8(dev, scsc_addr); | |
532 | ||
533 | switch (tmp & 0x30) { | |
534 | case 0x00: | |
7b255436 | 535 | /* On 100 MHz clocking, try and switch to 133 MHz */ |
165701d9 BZ |
536 | sil_iowrite8(dev, tmp | 0x10, scsc_addr); |
537 | break; | |
538 | case 0x30: | |
539 | /* Clocking is disabled, attempt to force 133MHz clocking. */ | |
540 | sil_iowrite8(dev, tmp & ~0x20, scsc_addr); | |
541 | case 0x10: | |
542 | /* On 133Mhz clocking. */ | |
543 | break; | |
544 | case 0x20: | |
545 | /* On PCIx2 clocking. */ | |
546 | break; | |
1da177e4 LT |
547 | } |
548 | ||
165701d9 | 549 | tmp = sil_ioread8(dev, scsc_addr); |
1da177e4 | 550 | |
7b255436 | 551 | sil_iowrite8 (dev, 0x72, base + 0xA1); |
165701d9 BZ |
552 | sil_iowrite16(dev, 0x328A, base + 0xA2); |
553 | sil_iowrite32(dev, 0x62DD62DD, base + 0xA4); | |
554 | sil_iowrite32(dev, 0x43924392, base + 0xA8); | |
555 | sil_iowrite32(dev, 0x40094009, base + 0xAC); | |
7b255436 | 556 | sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1); |
165701d9 BZ |
557 | sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2); |
558 | sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4); | |
559 | sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8); | |
560 | sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC); | |
561 | ||
562 | if (base && pdev_is_sata(dev)) { | |
563 | writel(0xFFFF0000, ioaddr + 0x108); | |
564 | writel(0xFFFF0000, ioaddr + 0x188); | |
565 | writel(0x00680000, ioaddr + 0x148); | |
566 | writel(0x00680000, ioaddr + 0x1C8); | |
567 | } | |
568 | ||
24cc434a BZ |
569 | /* report the clocking mode of the controller */ |
570 | if (!pdev_is_sata(dev)) { | |
571 | static const char *clk_str[] = | |
572 | { "== 100", "== 133", "== 2X PCI", "DISABLED!" }; | |
573 | ||
574 | tmp >>= 4; | |
575 | printk(KERN_INFO "%s: BASE CLOCK %s\n", name, clk_str[tmp & 3]); | |
576 | } | |
1da177e4 | 577 | |
1da177e4 LT |
578 | return 0; |
579 | } | |
580 | ||
581 | /** | |
582 | * init_mmio_iops_siimage - set up the iops for MMIO | |
583 | * @hwif: interface to set up | |
584 | * | |
585 | * The basic setup here is fairly simple, we can use standard MMIO | |
586 | * operations. However we do have to set the taskfile register offsets | |
7b255436 | 587 | * by hand as there isn't a standard defined layout for them this time. |
1da177e4 LT |
588 | * |
589 | * The hardware supports buffered taskfiles and also some rather nice | |
19c1ef5f | 590 | * extended PRD tables. For better SI3112 support use the libata driver |
1da177e4 LT |
591 | */ |
592 | ||
593 | static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) | |
594 | { | |
36501650 | 595 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
596 | void *addr = pci_get_drvdata(dev); |
597 | u8 ch = hwif->channel; | |
4c3032d8 | 598 | struct ide_io_ports *io_ports = &hwif->io_ports; |
7b255436 | 599 | unsigned long base; |
4c3032d8 | 600 | |
1da177e4 | 601 | /* |
7b255436 | 602 | * Fill in the basic hwif bits |
1da177e4 | 603 | */ |
c5dd43ec | 604 | hwif->host_flags |= IDE_HFLAG_MMIO; |
1da177e4 | 605 | default_hwif_mmiops(hwif); |
7b255436 | 606 | hwif->hwif_data = addr; |
1da177e4 LT |
607 | |
608 | /* | |
7b255436 SS |
609 | * Now set up the hw. We have to do this ourselves as the |
610 | * MMIO layout isn't the same as the standard port based I/O. | |
1da177e4 | 611 | */ |
4c3032d8 | 612 | memset(io_ports, 0, sizeof(*io_ports)); |
1da177e4 LT |
613 | |
614 | base = (unsigned long)addr; | |
615 | if (ch) | |
616 | base += 0xC0; | |
617 | else | |
618 | base += 0x80; | |
619 | ||
620 | /* | |
7b255436 SS |
621 | * The buffered task file doesn't have status/control, so we |
622 | * can't currently use it sanely since we want to use LBA48 mode. | |
623 | */ | |
4c3032d8 BZ |
624 | io_ports->data_addr = base; |
625 | io_ports->error_addr = base + 1; | |
626 | io_ports->nsect_addr = base + 2; | |
627 | io_ports->lbal_addr = base + 3; | |
628 | io_ports->lbam_addr = base + 4; | |
629 | io_ports->lbah_addr = base + 5; | |
630 | io_ports->device_addr = base + 6; | |
631 | io_ports->status_addr = base + 7; | |
632 | io_ports->ctl_addr = base + 10; | |
1da177e4 LT |
633 | |
634 | if (pdev_is_sata(dev)) { | |
635 | base = (unsigned long)addr; | |
636 | if (ch) | |
637 | base += 0x80; | |
638 | hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; | |
639 | hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; | |
640 | hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; | |
1da177e4 LT |
641 | } |
642 | ||
9239b333 | 643 | hwif->irq = dev->irq; |
1da177e4 | 644 | |
9239b333 | 645 | hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00); |
1da177e4 LT |
646 | } |
647 | ||
648 | static int is_dev_seagate_sata(ide_drive_t *drive) | |
649 | { | |
7b255436 SS |
650 | const char *s = &drive->id->model[0]; |
651 | unsigned len = strnlen(s, sizeof(drive->id->model)); | |
1da177e4 | 652 | |
7b255436 | 653 | if ((len > 4) && (!memcmp(s, "ST", 2))) |
1da177e4 LT |
654 | if ((!memcmp(s + len - 2, "AS", 2)) || |
655 | (!memcmp(s + len - 3, "ASL", 3))) { | |
656 | printk(KERN_INFO "%s: applying pessimistic Seagate " | |
657 | "errata fix\n", drive->name); | |
658 | return 1; | |
659 | } | |
7b255436 | 660 | |
1da177e4 LT |
661 | return 0; |
662 | } | |
663 | ||
664 | /** | |
f01393e4 BZ |
665 | * sil_quirkproc - post probe fixups |
666 | * @drive: drive | |
1da177e4 LT |
667 | * |
668 | * Called after drive probe we use this to decide whether the | |
669 | * Seagate fixup must be applied. This used to be in init_iops but | |
670 | * that can occur before we know what drives are present. | |
671 | */ | |
672 | ||
f01393e4 | 673 | static void __devinit sil_quirkproc(ide_drive_t *drive) |
1da177e4 | 674 | { |
f01393e4 BZ |
675 | ide_hwif_t *hwif = drive->hwif; |
676 | ||
7b255436 | 677 | /* Try and rise the rqsize */ |
f01393e4 | 678 | if (!is_sata(hwif) || !is_dev_seagate_sata(drive)) |
1da177e4 LT |
679 | hwif->rqsize = 128; |
680 | } | |
681 | ||
682 | /** | |
683 | * init_iops_siimage - set up iops | |
684 | * @hwif: interface to set up | |
685 | * | |
686 | * Do the basic setup for the SIIMAGE hardware interface | |
687 | * and then do the MMIO setup if we can. This is the first | |
688 | * look in we get for setting up the hwif so that we | |
689 | * can get the iops right before using them. | |
690 | */ | |
691 | ||
692 | static void __devinit init_iops_siimage(ide_hwif_t *hwif) | |
693 | { | |
36501650 BZ |
694 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
695 | ||
1da177e4 LT |
696 | hwif->hwif_data = NULL; |
697 | ||
698 | /* Pessimal until we finish probing */ | |
699 | hwif->rqsize = 15; | |
700 | ||
36501650 | 701 | if (pci_get_drvdata(dev) == NULL) |
1da177e4 | 702 | return; |
fc212bb1 | 703 | |
1da177e4 LT |
704 | init_mmio_iops_siimage(hwif); |
705 | } | |
706 | ||
707 | /** | |
ac95beed | 708 | * sil_cable_detect - cable detection |
1da177e4 LT |
709 | * @hwif: interface to check |
710 | * | |
7b255436 | 711 | * Check for the presence of an ATA66 capable cable on the interface. |
1da177e4 LT |
712 | */ |
713 | ||
ac95beed | 714 | static u8 __devinit sil_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 715 | { |
7b255436 SS |
716 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
717 | unsigned long addr = siimage_selreg(hwif, 0); | |
718 | u8 ata66 = sil_ioread8(dev, addr); | |
1da177e4 | 719 | |
49521f97 | 720 | return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
1da177e4 LT |
721 | } |
722 | ||
ac95beed BZ |
723 | static const struct ide_port_ops sil_pata_port_ops = { |
724 | .set_pio_mode = sil_set_pio_mode, | |
725 | .set_dma_mode = sil_set_dma_mode, | |
726 | .quirkproc = sil_quirkproc, | |
727 | .udma_filter = sil_pata_udma_filter, | |
728 | .cable_detect = sil_cable_detect, | |
729 | }; | |
730 | ||
731 | static const struct ide_port_ops sil_sata_port_ops = { | |
732 | .set_pio_mode = sil_set_pio_mode, | |
733 | .set_dma_mode = sil_set_dma_mode, | |
734 | .reset_poll = sil_sata_reset_poll, | |
735 | .pre_reset = sil_sata_pre_reset, | |
736 | .quirkproc = sil_quirkproc, | |
737 | .udma_filter = sil_sata_udma_filter, | |
738 | .cable_detect = sil_cable_detect, | |
739 | }; | |
740 | ||
b26b0c59 BH |
741 | static const struct ide_dma_ops sil_dma_ops = { |
742 | .dma_host_set = ide_dma_host_set, | |
743 | .dma_setup = ide_dma_setup, | |
744 | .dma_exec_cmd = ide_dma_exec_cmd, | |
745 | .dma_start = ide_dma_start, | |
746 | .dma_end = __ide_dma_end, | |
5e37bdc0 | 747 | .dma_test_irq = siimage_dma_test_irq, |
b26b0c59 BH |
748 | .dma_timeout = ide_dma_timeout, |
749 | .dma_lost_irq = ide_dma_lost_irq, | |
5e37bdc0 BZ |
750 | }; |
751 | ||
ac95beed | 752 | #define DECLARE_SII_DEV(name_str, p_ops) \ |
1da177e4 LT |
753 | { \ |
754 | .name = name_str, \ | |
755 | .init_chipset = init_chipset_siimage, \ | |
756 | .init_iops = init_iops_siimage, \ | |
ac95beed | 757 | .port_ops = p_ops, \ |
5e37bdc0 | 758 | .dma_ops = &sil_dma_ops, \ |
4099d143 | 759 | .pio_mask = ATA_PIO4, \ |
5f8b6c34 BZ |
760 | .mwdma_mask = ATA_MWDMA2, \ |
761 | .udma_mask = ATA_UDMA6, \ | |
1da177e4 LT |
762 | } |
763 | ||
85620436 | 764 | static const struct ide_port_info siimage_chipsets[] __devinitdata = { |
ac95beed BZ |
765 | /* 0 */ DECLARE_SII_DEV("SiI680", &sil_pata_port_ops), |
766 | /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA", &sil_sata_port_ops), | |
767 | /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA", &sil_sata_port_ops) | |
1da177e4 LT |
768 | }; |
769 | ||
770 | /** | |
7b255436 | 771 | * siimage_init_one - PCI layer discovery entry |
1da177e4 LT |
772 | * @dev: PCI device |
773 | * @id: ident table entry | |
774 | * | |
7b255436 | 775 | * Called by the PCI code when it finds an SiI680 or SiI3112 controller. |
1da177e4 LT |
776 | * We then use the IDE PCI generic helper to do most of the work. |
777 | */ | |
7b255436 SS |
778 | |
779 | static int __devinit siimage_init_one(struct pci_dev *dev, | |
780 | const struct pci_device_id *id) | |
1da177e4 | 781 | { |
5e37bdc0 BZ |
782 | struct ide_port_info d; |
783 | u8 idx = id->driver_data; | |
784 | ||
785 | d = siimage_chipsets[idx]; | |
786 | ||
787 | if (idx) { | |
788 | static int first = 1; | |
789 | ||
790 | if (first) { | |
791 | printk(KERN_INFO "siimage: For full SATA support you " | |
792 | "should use the libata sata_sil module.\n"); | |
793 | first = 0; | |
794 | } | |
795 | ||
796 | d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA; | |
797 | } | |
798 | ||
799 | return ide_setup_pci_device(dev, &d); | |
1da177e4 LT |
800 | } |
801 | ||
9cbcc5e3 BZ |
802 | static const struct pci_device_id siimage_pci_tbl[] = { |
803 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 }, | |
1da177e4 | 804 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
9cbcc5e3 BZ |
805 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 }, |
806 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 2 }, | |
1da177e4 LT |
807 | #endif |
808 | { 0, }, | |
809 | }; | |
810 | MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); | |
811 | ||
812 | static struct pci_driver driver = { | |
813 | .name = "SiI_IDE", | |
814 | .id_table = siimage_pci_tbl, | |
815 | .probe = siimage_init_one, | |
816 | }; | |
817 | ||
82ab1eec | 818 | static int __init siimage_ide_init(void) |
1da177e4 LT |
819 | { |
820 | return ide_pci_register_driver(&driver); | |
821 | } | |
822 | ||
823 | module_init(siimage_ide_init); | |
824 | ||
825 | MODULE_AUTHOR("Andre Hedrick, Alan Cox"); | |
826 | MODULE_DESCRIPTION("PCI driver module for SiI IDE"); | |
827 | MODULE_LICENSE("GPL"); |