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Commit | Line | Data |
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1da177e4 | 1 | /* |
328dcbb6 | 2 | * linux/drivers/ide/pci/siimage.c Version 1.15 Jun 29 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> | |
5 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
075cb655 | 6 | * Copyright (C) 2007 MontaVista Software, Inc. |
328dcbb6 | 7 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
8 | * |
9 | * May be copied or modified under the terms of the GNU General Public License | |
10 | * | |
bf4c796d JG |
11 | * Documentation for CMD680: |
12 | * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 | |
13 | * | |
14 | * Documentation for SiI 3112: | |
15 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
16 | * | |
17 | * Errata and other documentation only available under NDA. | |
1da177e4 LT |
18 | * |
19 | * | |
20 | * FAQ Items: | |
21 | * If you are using Marvell SATA-IDE adapters with Maxtor drives | |
22 | * ensure the system is set up for ATA100/UDMA5 not UDMA6. | |
23 | * | |
24 | * If you are using WD drives with SATA bridges you must set the | |
25 | * drive to "Single". "Master" will hang | |
26 | * | |
27 | * If you have strange problems with nVidia chipset systems please | |
28 | * see the SI support documentation and update your system BIOS | |
29 | * if neccessary | |
8693d3e4 AC |
30 | * |
31 | * The Dell DRAC4 has some interesting features including effectively hot | |
32 | * unplugging/replugging the virtual CD interface when the DRAC is reset. | |
33 | * This often causes drivers/ide/siimage to panic but is ok with the rather | |
34 | * smarter code in libata. | |
328dcbb6 BZ |
35 | * |
36 | * TODO: | |
37 | * - IORDY fixes | |
38 | * - VDMA support | |
1da177e4 LT |
39 | */ |
40 | ||
1da177e4 LT |
41 | #include <linux/types.h> |
42 | #include <linux/module.h> | |
43 | #include <linux/pci.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/hdreg.h> | |
46 | #include <linux/ide.h> | |
47 | #include <linux/init.h> | |
48 | ||
49 | #include <asm/io.h> | |
50 | ||
1da177e4 LT |
51 | /** |
52 | * pdev_is_sata - check if device is SATA | |
53 | * @pdev: PCI device to check | |
54 | * | |
55 | * Returns true if this is a SATA controller | |
56 | */ | |
57 | ||
58 | static int pdev_is_sata(struct pci_dev *pdev) | |
59 | { | |
60 | switch(pdev->device) | |
61 | { | |
62 | case PCI_DEVICE_ID_SII_3112: | |
63 | case PCI_DEVICE_ID_SII_1210SA: | |
64 | return 1; | |
65 | case PCI_DEVICE_ID_SII_680: | |
66 | return 0; | |
67 | } | |
68 | BUG(); | |
69 | return 0; | |
70 | } | |
71 | ||
72 | /** | |
73 | * is_sata - check if hwif is SATA | |
74 | * @hwif: interface to check | |
75 | * | |
76 | * Returns true if this is a SATA controller | |
77 | */ | |
78 | ||
79 | static inline int is_sata(ide_hwif_t *hwif) | |
80 | { | |
81 | return pdev_is_sata(hwif->pci_dev); | |
82 | } | |
83 | ||
84 | /** | |
85 | * siimage_selreg - return register base | |
86 | * @hwif: interface | |
87 | * @r: config offset | |
88 | * | |
89 | * Turn a config register offset into the right address in either | |
90 | * PCI space or MMIO space to access the control register in question | |
91 | * Thankfully this is a configuration operation so isnt performance | |
92 | * criticial. | |
93 | */ | |
94 | ||
95 | static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) | |
96 | { | |
97 | unsigned long base = (unsigned long)hwif->hwif_data; | |
98 | base += 0xA0 + r; | |
99 | if(hwif->mmio) | |
100 | base += (hwif->channel << 6); | |
101 | else | |
102 | base += (hwif->channel << 4); | |
103 | return base; | |
104 | } | |
105 | ||
106 | /** | |
107 | * siimage_seldev - return register base | |
108 | * @hwif: interface | |
109 | * @r: config offset | |
110 | * | |
111 | * Turn a config register offset into the right address in either | |
112 | * PCI space or MMIO space to access the control register in question | |
113 | * including accounting for the unit shift. | |
114 | */ | |
115 | ||
116 | static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) | |
117 | { | |
118 | ide_hwif_t *hwif = HWIF(drive); | |
119 | unsigned long base = (unsigned long)hwif->hwif_data; | |
120 | base += 0xA0 + r; | |
121 | if(hwif->mmio) | |
122 | base += (hwif->channel << 6); | |
123 | else | |
124 | base += (hwif->channel << 4); | |
125 | base |= drive->select.b.unit << drive->select.b.unit; | |
126 | return base; | |
127 | } | |
128 | ||
129 | /** | |
2d5eaa6d BZ |
130 | * sil_udma_filter - compute UDMA mask |
131 | * @drive: IDE device | |
132 | * | |
133 | * Compute the available UDMA speeds for the device on the interface. | |
1da177e4 | 134 | * |
1da177e4 | 135 | * For the CMD680 this depends on the clocking mode (scsc), for the |
2d5eaa6d | 136 | * SI3112 SATA controller life is a bit simpler. |
1da177e4 | 137 | */ |
2d5eaa6d BZ |
138 | |
139 | static u8 sil_udma_filter(ide_drive_t *drive) | |
1da177e4 | 140 | { |
2d5eaa6d | 141 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 | 142 | unsigned long base = (unsigned long) hwif->hwif_data; |
2d5eaa6d | 143 | u8 mask = 0, scsc = 0; |
1da177e4 LT |
144 | |
145 | if (hwif->mmio) | |
146 | scsc = hwif->INB(base + 0x4A); | |
147 | else | |
148 | pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc); | |
149 | ||
2d5eaa6d BZ |
150 | if (is_sata(hwif)) { |
151 | mask = strstr(drive->id->model, "Maxtor") ? 0x3f : 0x7f; | |
152 | goto out; | |
1da177e4 | 153 | } |
2d5eaa6d | 154 | |
1da177e4 | 155 | if ((scsc & 0x30) == 0x10) /* 133 */ |
2d5eaa6d | 156 | mask = 0x7f; |
1da177e4 | 157 | else if ((scsc & 0x30) == 0x20) /* 2xPCI */ |
2d5eaa6d | 158 | mask = 0x7f; |
1da177e4 | 159 | else if ((scsc & 0x30) == 0x00) /* 100 */ |
2d5eaa6d | 160 | mask = 0x3f; |
1da177e4 LT |
161 | else /* Disabled ? */ |
162 | BUG(); | |
2d5eaa6d BZ |
163 | out: |
164 | return mask; | |
1da177e4 LT |
165 | } |
166 | ||
167 | /** | |
328dcbb6 | 168 | * sil_tune_pio - tune a drive |
1da177e4 | 169 | * @drive: drive to tune |
328dcbb6 | 170 | * @pio: the desired PIO mode |
1da177e4 LT |
171 | * |
172 | * Load the timing settings for this device mode into the | |
173 | * controller. If we are in PIO mode 3 or 4 turn on IORDY | |
174 | * monitoring (bit 9). The TF timing is bits 31:16 | |
175 | */ | |
328dcbb6 BZ |
176 | |
177 | static void sil_tune_pio(ide_drive_t *drive, u8 pio) | |
1da177e4 | 178 | { |
328dcbb6 BZ |
179 | const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; |
180 | const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; | |
181 | ||
1da177e4 | 182 | ide_hwif_t *hwif = HWIF(drive); |
328dcbb6 | 183 | ide_drive_t *pair = &hwif->drives[drive->dn ^ 1]; |
1da177e4 LT |
184 | u32 speedt = 0; |
185 | u16 speedp = 0; | |
186 | unsigned long addr = siimage_seldev(drive, 0x04); | |
187 | unsigned long tfaddr = siimage_selreg(hwif, 0x02); | |
328dcbb6 BZ |
188 | u8 tf_pio = pio; |
189 | ||
190 | /* trim *taskfile* PIO to the slowest of the master/slave */ | |
191 | if (pair->present) { | |
192 | u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4, NULL); | |
193 | ||
194 | if (pair_pio < tf_pio) | |
195 | tf_pio = pair_pio; | |
1da177e4 | 196 | } |
075cb655 | 197 | |
328dcbb6 BZ |
198 | /* cheat for now and use the docs */ |
199 | speedp = data_speed[pio]; | |
200 | speedt = tf_speed[tf_pio]; | |
201 | ||
075cb655 SS |
202 | if (hwif->mmio) { |
203 | hwif->OUTW(speedp, addr); | |
204 | hwif->OUTW(speedt, tfaddr); | |
1da177e4 | 205 | /* Now set up IORDY */ |
328dcbb6 | 206 | if (pio > 2) |
1da177e4 LT |
207 | hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2); |
208 | else | |
209 | hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2); | |
075cb655 | 210 | } else { |
1da177e4 LT |
211 | pci_write_config_word(hwif->pci_dev, addr, speedp); |
212 | pci_write_config_word(hwif->pci_dev, tfaddr, speedt); | |
213 | pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp); | |
214 | speedp &= ~0x200; | |
215 | /* Set IORDY for mode 3 or 4 */ | |
328dcbb6 | 216 | if (pio > 2) |
1da177e4 LT |
217 | speedp |= 0x200; |
218 | pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp); | |
219 | } | |
220 | } | |
221 | ||
328dcbb6 | 222 | static void sil_tuneproc(ide_drive_t *drive, u8 pio) |
1da177e4 | 223 | { |
328dcbb6 BZ |
224 | pio = ide_get_best_pio_mode(drive, pio, 4, NULL); |
225 | sil_tune_pio(drive, pio); | |
226 | (void)ide_config_drive_speed(drive, XFER_PIO_0 + pio); | |
1da177e4 LT |
227 | } |
228 | ||
1da177e4 LT |
229 | /** |
230 | * siimage_tune_chipset - set controller timings | |
231 | * @drive: Drive to set up | |
232 | * @xferspeed: speed we want to achieve | |
233 | * | |
234 | * Tune the SII chipset for the desired mode. If we can't achieve | |
235 | * the desired mode then tune for a lower one, but ultimately | |
236 | * make the thing work. | |
237 | */ | |
238 | ||
239 | static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed) | |
240 | { | |
241 | u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; | |
242 | u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
243 | u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
244 | ||
245 | ide_hwif_t *hwif = HWIF(drive); | |
246 | u16 ultra = 0, multi = 0; | |
247 | u8 mode = 0, unit = drive->select.b.unit; | |
2d5eaa6d | 248 | u8 speed = ide_rate_filter(drive, xferspeed); |
1da177e4 LT |
249 | unsigned long base = (unsigned long)hwif->hwif_data; |
250 | u8 scsc = 0, addr_mask = ((hwif->channel) ? | |
251 | ((hwif->mmio) ? 0xF4 : 0x84) : | |
252 | ((hwif->mmio) ? 0xB4 : 0x80)); | |
253 | ||
254 | unsigned long ma = siimage_seldev(drive, 0x08); | |
255 | unsigned long ua = siimage_seldev(drive, 0x0C); | |
256 | ||
257 | if (hwif->mmio) { | |
258 | scsc = hwif->INB(base + 0x4A); | |
259 | mode = hwif->INB(base + addr_mask); | |
260 | multi = hwif->INW(ma); | |
261 | ultra = hwif->INW(ua); | |
262 | } else { | |
263 | pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc); | |
264 | pci_read_config_byte(hwif->pci_dev, addr_mask, &mode); | |
265 | pci_read_config_word(hwif->pci_dev, ma, &multi); | |
266 | pci_read_config_word(hwif->pci_dev, ua, &ultra); | |
267 | } | |
268 | ||
269 | mode &= ~((unit) ? 0x30 : 0x03); | |
270 | ultra &= ~0x3F; | |
271 | scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; | |
272 | ||
273 | scsc = is_sata(hwif) ? 1 : scsc; | |
274 | ||
275 | switch(speed) { | |
276 | case XFER_PIO_4: | |
277 | case XFER_PIO_3: | |
278 | case XFER_PIO_2: | |
279 | case XFER_PIO_1: | |
280 | case XFER_PIO_0: | |
328dcbb6 | 281 | sil_tune_pio(drive, speed - XFER_PIO_0); |
1da177e4 LT |
282 | mode |= ((unit) ? 0x10 : 0x01); |
283 | break; | |
284 | case XFER_MW_DMA_2: | |
285 | case XFER_MW_DMA_1: | |
286 | case XFER_MW_DMA_0: | |
287 | multi = dma[speed - XFER_MW_DMA_0]; | |
288 | mode |= ((unit) ? 0x20 : 0x02); | |
1da177e4 LT |
289 | break; |
290 | case XFER_UDMA_6: | |
291 | case XFER_UDMA_5: | |
292 | case XFER_UDMA_4: | |
293 | case XFER_UDMA_3: | |
294 | case XFER_UDMA_2: | |
295 | case XFER_UDMA_1: | |
296 | case XFER_UDMA_0: | |
297 | multi = dma[2]; | |
298 | ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) : | |
299 | (ultra5[speed - XFER_UDMA_0])); | |
300 | mode |= ((unit) ? 0x30 : 0x03); | |
1da177e4 LT |
301 | break; |
302 | default: | |
303 | return 1; | |
304 | } | |
305 | ||
306 | if (hwif->mmio) { | |
307 | hwif->OUTB(mode, base + addr_mask); | |
308 | hwif->OUTW(multi, ma); | |
309 | hwif->OUTW(ultra, ua); | |
310 | } else { | |
311 | pci_write_config_byte(hwif->pci_dev, addr_mask, mode); | |
312 | pci_write_config_word(hwif->pci_dev, ma, multi); | |
313 | pci_write_config_word(hwif->pci_dev, ua, ultra); | |
314 | } | |
315 | return (ide_config_drive_speed(drive, speed)); | |
316 | } | |
317 | ||
1da177e4 LT |
318 | /** |
319 | * siimage_configure_drive_for_dma - set up for DMA transfers | |
320 | * @drive: drive we are going to set up | |
321 | * | |
322 | * Set up the drive for DMA, tune the controller and drive as | |
323 | * required. If the drive isn't suitable for DMA or we hit | |
324 | * other problems then we will drop down to PIO and set up | |
325 | * PIO appropriately | |
326 | */ | |
327 | ||
328 | static int siimage_config_drive_for_dma (ide_drive_t *drive) | |
329 | { | |
4728d546 | 330 | if (ide_tune_dma(drive)) |
3608b5d7 | 331 | return 0; |
1da177e4 | 332 | |
d8f4469d | 333 | if (ide_use_fast_pio(drive)) |
328dcbb6 | 334 | sil_tuneproc(drive, 255); |
d8f4469d | 335 | |
3608b5d7 | 336 | return -1; |
1da177e4 LT |
337 | } |
338 | ||
339 | /* returns 1 if dma irq issued, 0 otherwise */ | |
340 | static int siimage_io_ide_dma_test_irq (ide_drive_t *drive) | |
341 | { | |
342 | ide_hwif_t *hwif = HWIF(drive); | |
343 | u8 dma_altstat = 0; | |
344 | unsigned long addr = siimage_selreg(hwif, 1); | |
345 | ||
346 | /* return 1 if INTR asserted */ | |
347 | if ((hwif->INB(hwif->dma_status) & 4) == 4) | |
348 | return 1; | |
349 | ||
350 | /* return 1 if Device INTR asserted */ | |
351 | pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat); | |
352 | if (dma_altstat & 8) | |
353 | return 0; //return 1; | |
354 | return 0; | |
355 | } | |
356 | ||
1da177e4 LT |
357 | /** |
358 | * siimage_mmio_ide_dma_test_irq - check we caused an IRQ | |
359 | * @drive: drive we are testing | |
360 | * | |
361 | * Check if we caused an IDE DMA interrupt. We may also have caused | |
362 | * SATA status interrupts, if so we clean them up and continue. | |
363 | */ | |
364 | ||
365 | static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive) | |
366 | { | |
367 | ide_hwif_t *hwif = HWIF(drive); | |
368 | unsigned long base = (unsigned long)hwif->hwif_data; | |
369 | unsigned long addr = siimage_selreg(hwif, 0x1); | |
370 | ||
371 | if (SATA_ERROR_REG) { | |
0ecdca26 | 372 | u32 ext_stat = readl((void __iomem *)(base + 0x10)); |
1da177e4 LT |
373 | u8 watchdog = 0; |
374 | if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { | |
0ecdca26 BZ |
375 | u32 sata_error = readl((void __iomem *)SATA_ERROR_REG); |
376 | writel(sata_error, (void __iomem *)SATA_ERROR_REG); | |
1da177e4 | 377 | watchdog = (sata_error & 0x00680000) ? 1 : 0; |
1da177e4 LT |
378 | printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
379 | "watchdog = %d, %s\n", | |
380 | drive->name, sata_error, watchdog, | |
381 | __FUNCTION__); | |
1da177e4 LT |
382 | |
383 | } else { | |
384 | watchdog = (ext_stat & 0x8000) ? 1 : 0; | |
385 | } | |
386 | ext_stat >>= 16; | |
387 | ||
388 | if (!(ext_stat & 0x0404) && !watchdog) | |
389 | return 0; | |
390 | } | |
391 | ||
392 | /* return 1 if INTR asserted */ | |
0ecdca26 | 393 | if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04) |
1da177e4 LT |
394 | return 1; |
395 | ||
396 | /* return 1 if Device INTR asserted */ | |
0ecdca26 | 397 | if ((readb((void __iomem *)addr) & 8) == 8) |
1da177e4 LT |
398 | return 0; //return 1; |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
403 | /** | |
404 | * siimage_busproc - bus isolation ioctl | |
405 | * @drive: drive to isolate/restore | |
406 | * @state: bus state to set | |
407 | * | |
408 | * Used by the SII3112 to handle bus isolation. As this is a | |
409 | * SATA controller the work required is quite limited, we | |
410 | * just have to clean up the statistics | |
411 | */ | |
412 | ||
413 | static int siimage_busproc (ide_drive_t * drive, int state) | |
414 | { | |
415 | ide_hwif_t *hwif = HWIF(drive); | |
416 | u32 stat_config = 0; | |
417 | unsigned long addr = siimage_selreg(hwif, 0); | |
418 | ||
0ecdca26 BZ |
419 | if (hwif->mmio) |
420 | stat_config = readl((void __iomem *)addr); | |
421 | else | |
1da177e4 LT |
422 | pci_read_config_dword(hwif->pci_dev, addr, &stat_config); |
423 | ||
424 | switch (state) { | |
425 | case BUSSTATE_ON: | |
426 | hwif->drives[0].failures = 0; | |
427 | hwif->drives[1].failures = 0; | |
428 | break; | |
429 | case BUSSTATE_OFF: | |
430 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
431 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
432 | break; | |
433 | case BUSSTATE_TRISTATE: | |
434 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
435 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
436 | break; | |
437 | default: | |
438 | return -EINVAL; | |
439 | } | |
440 | hwif->bus_state = state; | |
441 | return 0; | |
442 | } | |
443 | ||
444 | /** | |
445 | * siimage_reset_poll - wait for sata reset | |
446 | * @drive: drive we are resetting | |
447 | * | |
448 | * Poll the SATA phy and see whether it has come back from the dead | |
449 | * yet. | |
450 | */ | |
451 | ||
452 | static int siimage_reset_poll (ide_drive_t *drive) | |
453 | { | |
454 | if (SATA_STATUS_REG) { | |
455 | ide_hwif_t *hwif = HWIF(drive); | |
456 | ||
0ecdca26 BZ |
457 | /* SATA_STATUS_REG is valid only when in MMIO mode */ |
458 | if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) { | |
1da177e4 | 459 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", |
0ecdca26 | 460 | hwif->name, readl((void __iomem *)SATA_STATUS_REG)); |
1da177e4 LT |
461 | HWGROUP(drive)->polling = 0; |
462 | return ide_started; | |
463 | } | |
464 | return 0; | |
465 | } else { | |
466 | return 0; | |
467 | } | |
468 | } | |
469 | ||
470 | /** | |
471 | * siimage_pre_reset - reset hook | |
472 | * @drive: IDE device being reset | |
473 | * | |
474 | * For the SATA devices we need to handle recalibration/geometry | |
475 | * differently | |
476 | */ | |
477 | ||
478 | static void siimage_pre_reset (ide_drive_t *drive) | |
479 | { | |
480 | if (drive->media != ide_disk) | |
481 | return; | |
482 | ||
483 | if (is_sata(HWIF(drive))) | |
484 | { | |
485 | drive->special.b.set_geometry = 0; | |
486 | drive->special.b.recalibrate = 0; | |
487 | } | |
488 | } | |
489 | ||
490 | /** | |
491 | * siimage_reset - reset a device on an siimage controller | |
492 | * @drive: drive to reset | |
493 | * | |
494 | * Perform a controller level reset fo the device. For | |
495 | * SATA we must also check the PHY. | |
496 | */ | |
497 | ||
498 | static void siimage_reset (ide_drive_t *drive) | |
499 | { | |
500 | ide_hwif_t *hwif = HWIF(drive); | |
501 | u8 reset = 0; | |
502 | unsigned long addr = siimage_selreg(hwif, 0); | |
503 | ||
504 | if (hwif->mmio) { | |
505 | reset = hwif->INB(addr); | |
506 | hwif->OUTB((reset|0x03), addr); | |
507 | /* FIXME:posting */ | |
508 | udelay(25); | |
509 | hwif->OUTB(reset, addr); | |
510 | (void) hwif->INB(addr); | |
511 | } else { | |
512 | pci_read_config_byte(hwif->pci_dev, addr, &reset); | |
513 | pci_write_config_byte(hwif->pci_dev, addr, reset|0x03); | |
514 | udelay(25); | |
515 | pci_write_config_byte(hwif->pci_dev, addr, reset); | |
516 | pci_read_config_byte(hwif->pci_dev, addr, &reset); | |
517 | } | |
518 | ||
519 | if (SATA_STATUS_REG) { | |
0ecdca26 BZ |
520 | /* SATA_STATUS_REG is valid only when in MMIO mode */ |
521 | u32 sata_stat = readl((void __iomem *)SATA_STATUS_REG); | |
1da177e4 LT |
522 | printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n", |
523 | hwif->name, sata_stat, __FUNCTION__); | |
524 | if (!(sata_stat)) { | |
525 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", | |
526 | hwif->name, sata_stat); | |
527 | drive->failures++; | |
528 | } | |
529 | } | |
530 | ||
531 | } | |
532 | ||
533 | /** | |
534 | * proc_reports_siimage - add siimage controller to proc | |
535 | * @dev: PCI device | |
536 | * @clocking: SCSC value | |
537 | * @name: controller name | |
538 | * | |
539 | * Report the clocking mode of the controller and add it to | |
540 | * the /proc interface layer | |
541 | */ | |
542 | ||
543 | static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name) | |
544 | { | |
545 | if (!pdev_is_sata(dev)) { | |
546 | printk(KERN_INFO "%s: BASE CLOCK ", name); | |
547 | clocking &= 0x03; | |
548 | switch (clocking) { | |
549 | case 0x03: printk("DISABLED!\n"); break; | |
550 | case 0x02: printk("== 2X PCI\n"); break; | |
551 | case 0x01: printk("== 133\n"); break; | |
552 | case 0x00: printk("== 100\n"); break; | |
553 | } | |
554 | } | |
555 | } | |
556 | ||
557 | /** | |
558 | * setup_mmio_siimage - switch an SI controller into MMIO | |
559 | * @dev: PCI device we are configuring | |
560 | * @name: device name | |
561 | * | |
562 | * Attempt to put the device into mmio mode. There are some slight | |
563 | * complications here with certain systems where the mmio bar isnt | |
564 | * mapped so we have to be sure we can fall back to I/O. | |
565 | */ | |
566 | ||
567 | static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name) | |
568 | { | |
569 | unsigned long bar5 = pci_resource_start(dev, 5); | |
570 | unsigned long barsize = pci_resource_len(dev, 5); | |
571 | u8 tmpbyte = 0; | |
572 | void __iomem *ioaddr; | |
d868dd19 | 573 | u32 tmp, irq_mask; |
1da177e4 LT |
574 | |
575 | /* | |
576 | * Drop back to PIO if we can't map the mmio. Some | |
577 | * systems seem to get terminally confused in the PCI | |
578 | * spaces. | |
579 | */ | |
580 | ||
581 | if(!request_mem_region(bar5, barsize, name)) | |
582 | { | |
583 | printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n"); | |
584 | return 0; | |
585 | } | |
586 | ||
587 | ioaddr = ioremap(bar5, barsize); | |
588 | ||
589 | if (ioaddr == NULL) | |
590 | { | |
591 | release_mem_region(bar5, barsize); | |
592 | return 0; | |
593 | } | |
594 | ||
595 | pci_set_master(dev); | |
596 | pci_set_drvdata(dev, (void *) ioaddr); | |
597 | ||
598 | if (pdev_is_sata(dev)) { | |
d868dd19 JL |
599 | /* make sure IDE0/1 interrupts are not masked */ |
600 | irq_mask = (1 << 22) | (1 << 23); | |
601 | tmp = readl(ioaddr + 0x48); | |
602 | if (tmp & irq_mask) { | |
603 | tmp &= ~irq_mask; | |
604 | writel(tmp, ioaddr + 0x48); | |
605 | readl(ioaddr + 0x48); /* flush */ | |
606 | } | |
1da177e4 LT |
607 | writel(0, ioaddr + 0x148); |
608 | writel(0, ioaddr + 0x1C8); | |
609 | } | |
610 | ||
611 | writeb(0, ioaddr + 0xB4); | |
612 | writeb(0, ioaddr + 0xF4); | |
613 | tmpbyte = readb(ioaddr + 0x4A); | |
614 | ||
615 | switch(tmpbyte & 0x30) { | |
616 | case 0x00: | |
617 | /* In 100 MHz clocking, try and switch to 133 */ | |
618 | writeb(tmpbyte|0x10, ioaddr + 0x4A); | |
619 | break; | |
620 | case 0x10: | |
621 | /* On 133Mhz clocking */ | |
622 | break; | |
623 | case 0x20: | |
624 | /* On PCIx2 clocking */ | |
625 | break; | |
626 | case 0x30: | |
627 | /* Clocking is disabled */ | |
628 | /* 133 clock attempt to force it on */ | |
629 | writeb(tmpbyte & ~0x20, ioaddr + 0x4A); | |
630 | break; | |
631 | } | |
632 | ||
633 | writeb( 0x72, ioaddr + 0xA1); | |
634 | writew( 0x328A, ioaddr + 0xA2); | |
635 | writel(0x62DD62DD, ioaddr + 0xA4); | |
636 | writel(0x43924392, ioaddr + 0xA8); | |
637 | writel(0x40094009, ioaddr + 0xAC); | |
638 | writeb( 0x72, ioaddr + 0xE1); | |
639 | writew( 0x328A, ioaddr + 0xE2); | |
640 | writel(0x62DD62DD, ioaddr + 0xE4); | |
641 | writel(0x43924392, ioaddr + 0xE8); | |
642 | writel(0x40094009, ioaddr + 0xEC); | |
643 | ||
644 | if (pdev_is_sata(dev)) { | |
645 | writel(0xFFFF0000, ioaddr + 0x108); | |
646 | writel(0xFFFF0000, ioaddr + 0x188); | |
647 | writel(0x00680000, ioaddr + 0x148); | |
648 | writel(0x00680000, ioaddr + 0x1C8); | |
649 | } | |
650 | ||
651 | tmpbyte = readb(ioaddr + 0x4A); | |
652 | ||
653 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
654 | return 1; | |
655 | } | |
656 | ||
657 | /** | |
658 | * init_chipset_siimage - set up an SI device | |
659 | * @dev: PCI device | |
660 | * @name: device name | |
661 | * | |
662 | * Perform the initial PCI set up for this device. Attempt to switch | |
663 | * to 133MHz clocking if the system isn't already set up to do it. | |
664 | */ | |
665 | ||
666 | static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name) | |
667 | { | |
668 | u32 class_rev = 0; | |
669 | u8 tmpbyte = 0; | |
670 | u8 BA5_EN = 0; | |
671 | ||
672 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
673 | class_rev &= 0xff; | |
674 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255); | |
675 | ||
676 | pci_read_config_byte(dev, 0x8A, &BA5_EN); | |
677 | if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) { | |
678 | if (setup_mmio_siimage(dev, name)) { | |
679 | return 0; | |
680 | } | |
681 | } | |
682 | ||
683 | pci_write_config_byte(dev, 0x80, 0x00); | |
684 | pci_write_config_byte(dev, 0x84, 0x00); | |
685 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
686 | switch(tmpbyte & 0x30) { | |
687 | case 0x00: | |
688 | /* 133 clock attempt to force it on */ | |
689 | pci_write_config_byte(dev, 0x8A, tmpbyte|0x10); | |
690 | case 0x30: | |
691 | /* if clocking is disabled */ | |
692 | /* 133 clock attempt to force it on */ | |
693 | pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20); | |
694 | case 0x10: | |
695 | /* 133 already */ | |
696 | break; | |
697 | case 0x20: | |
698 | /* BIOS set PCI x2 clocking */ | |
699 | break; | |
700 | } | |
701 | ||
702 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
703 | ||
704 | pci_write_config_byte(dev, 0xA1, 0x72); | |
705 | pci_write_config_word(dev, 0xA2, 0x328A); | |
706 | pci_write_config_dword(dev, 0xA4, 0x62DD62DD); | |
707 | pci_write_config_dword(dev, 0xA8, 0x43924392); | |
708 | pci_write_config_dword(dev, 0xAC, 0x40094009); | |
709 | pci_write_config_byte(dev, 0xB1, 0x72); | |
710 | pci_write_config_word(dev, 0xB2, 0x328A); | |
711 | pci_write_config_dword(dev, 0xB4, 0x62DD62DD); | |
712 | pci_write_config_dword(dev, 0xB8, 0x43924392); | |
713 | pci_write_config_dword(dev, 0xBC, 0x40094009); | |
714 | ||
715 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
716 | return 0; | |
717 | } | |
718 | ||
719 | /** | |
720 | * init_mmio_iops_siimage - set up the iops for MMIO | |
721 | * @hwif: interface to set up | |
722 | * | |
723 | * The basic setup here is fairly simple, we can use standard MMIO | |
724 | * operations. However we do have to set the taskfile register offsets | |
725 | * by hand as there isnt a standard defined layout for them this | |
726 | * time. | |
727 | * | |
728 | * The hardware supports buffered taskfiles and also some rather nice | |
19c1ef5f | 729 | * extended PRD tables. For better SI3112 support use the libata driver |
1da177e4 LT |
730 | */ |
731 | ||
732 | static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) | |
733 | { | |
734 | struct pci_dev *dev = hwif->pci_dev; | |
735 | void *addr = pci_get_drvdata(dev); | |
736 | u8 ch = hwif->channel; | |
737 | hw_regs_t hw; | |
738 | unsigned long base; | |
739 | ||
740 | /* | |
741 | * Fill in the basic HWIF bits | |
742 | */ | |
743 | ||
744 | default_hwif_mmiops(hwif); | |
745 | hwif->hwif_data = addr; | |
746 | ||
747 | /* | |
748 | * Now set up the hw. We have to do this ourselves as | |
59c51591 | 749 | * the MMIO layout isnt the same as the standard port |
1da177e4 LT |
750 | * based I/O |
751 | */ | |
752 | ||
753 | memset(&hw, 0, sizeof(hw_regs_t)); | |
754 | ||
755 | base = (unsigned long)addr; | |
756 | if (ch) | |
757 | base += 0xC0; | |
758 | else | |
759 | base += 0x80; | |
760 | ||
761 | /* | |
762 | * The buffered task file doesn't have status/control | |
763 | * so we can't currently use it sanely since we want to | |
764 | * use LBA48 mode. | |
765 | */ | |
1da177e4 LT |
766 | hw.io_ports[IDE_DATA_OFFSET] = base; |
767 | hw.io_ports[IDE_ERROR_OFFSET] = base + 1; | |
768 | hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2; | |
769 | hw.io_ports[IDE_SECTOR_OFFSET] = base + 3; | |
770 | hw.io_ports[IDE_LCYL_OFFSET] = base + 4; | |
771 | hw.io_ports[IDE_HCYL_OFFSET] = base + 5; | |
772 | hw.io_ports[IDE_SELECT_OFFSET] = base + 6; | |
773 | hw.io_ports[IDE_STATUS_OFFSET] = base + 7; | |
774 | hw.io_ports[IDE_CONTROL_OFFSET] = base + 10; | |
775 | ||
776 | hw.io_ports[IDE_IRQ_OFFSET] = 0; | |
777 | ||
778 | if (pdev_is_sata(dev)) { | |
779 | base = (unsigned long)addr; | |
780 | if (ch) | |
781 | base += 0x80; | |
782 | hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; | |
783 | hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; | |
784 | hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; | |
785 | hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140; | |
786 | hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144; | |
787 | hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148; | |
788 | } | |
789 | ||
790 | hw.irq = hwif->pci_dev->irq; | |
791 | ||
792 | memcpy(&hwif->hw, &hw, sizeof(hw)); | |
793 | memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports)); | |
794 | ||
795 | hwif->irq = hw.irq; | |
796 | ||
797 | base = (unsigned long) addr; | |
798 | ||
1da177e4 | 799 | hwif->dma_base = base + (ch ? 0x08 : 0x00); |
2ad1e558 BZ |
800 | |
801 | hwif->mmio = 1; | |
1da177e4 LT |
802 | } |
803 | ||
804 | static int is_dev_seagate_sata(ide_drive_t *drive) | |
805 | { | |
806 | const char *s = &drive->id->model[0]; | |
807 | unsigned len; | |
808 | ||
809 | if (!drive->present) | |
810 | return 0; | |
811 | ||
812 | len = strnlen(s, sizeof(drive->id->model)); | |
813 | ||
814 | if ((len > 4) && (!memcmp(s, "ST", 2))) { | |
815 | if ((!memcmp(s + len - 2, "AS", 2)) || | |
816 | (!memcmp(s + len - 3, "ASL", 3))) { | |
817 | printk(KERN_INFO "%s: applying pessimistic Seagate " | |
818 | "errata fix\n", drive->name); | |
819 | return 1; | |
820 | } | |
821 | } | |
822 | return 0; | |
823 | } | |
824 | ||
825 | /** | |
826 | * siimage_fixup - post probe fixups | |
827 | * @hwif: interface to fix up | |
828 | * | |
829 | * Called after drive probe we use this to decide whether the | |
830 | * Seagate fixup must be applied. This used to be in init_iops but | |
831 | * that can occur before we know what drives are present. | |
832 | */ | |
833 | ||
834 | static void __devinit siimage_fixup(ide_hwif_t *hwif) | |
835 | { | |
836 | /* Try and raise the rqsize */ | |
837 | if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0])) | |
838 | hwif->rqsize = 128; | |
839 | } | |
840 | ||
841 | /** | |
842 | * init_iops_siimage - set up iops | |
843 | * @hwif: interface to set up | |
844 | * | |
845 | * Do the basic setup for the SIIMAGE hardware interface | |
846 | * and then do the MMIO setup if we can. This is the first | |
847 | * look in we get for setting up the hwif so that we | |
848 | * can get the iops right before using them. | |
849 | */ | |
850 | ||
851 | static void __devinit init_iops_siimage(ide_hwif_t *hwif) | |
852 | { | |
853 | struct pci_dev *dev = hwif->pci_dev; | |
854 | u32 class_rev = 0; | |
855 | ||
856 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
857 | class_rev &= 0xff; | |
858 | ||
859 | hwif->hwif_data = NULL; | |
860 | ||
861 | /* Pessimal until we finish probing */ | |
862 | hwif->rqsize = 15; | |
863 | ||
864 | if (pci_get_drvdata(dev) == NULL) | |
865 | return; | |
866 | init_mmio_iops_siimage(hwif); | |
867 | } | |
868 | ||
869 | /** | |
870 | * ata66_siimage - check for 80 pin cable | |
871 | * @hwif: interface to check | |
872 | * | |
873 | * Check for the presence of an ATA66 capable cable on the | |
874 | * interface. | |
875 | */ | |
876 | ||
49521f97 | 877 | static u8 __devinit ata66_siimage(ide_hwif_t *hwif) |
1da177e4 LT |
878 | { |
879 | unsigned long addr = siimage_selreg(hwif, 0); | |
49521f97 BZ |
880 | u8 ata66 = 0; |
881 | ||
882 | if (pci_get_drvdata(hwif->pci_dev) == NULL) | |
1da177e4 | 883 | pci_read_config_byte(hwif->pci_dev, addr, &ata66); |
49521f97 BZ |
884 | else |
885 | ata66 = hwif->INB(addr); | |
1da177e4 | 886 | |
49521f97 | 887 | return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
1da177e4 LT |
888 | } |
889 | ||
890 | /** | |
891 | * init_hwif_siimage - set up hwif structs | |
892 | * @hwif: interface to set up | |
893 | * | |
894 | * We do the basic set up of the interface structure. The SIIMAGE | |
895 | * requires several custom handlers so we override the default | |
896 | * ide DMA handlers appropriately | |
897 | */ | |
898 | ||
899 | static void __devinit init_hwif_siimage(ide_hwif_t *hwif) | |
900 | { | |
901 | hwif->autodma = 0; | |
902 | ||
903 | hwif->resetproc = &siimage_reset; | |
904 | hwif->speedproc = &siimage_tune_chipset; | |
328dcbb6 | 905 | hwif->tuneproc = &sil_tuneproc; |
1da177e4 LT |
906 | hwif->reset_poll = &siimage_reset_poll; |
907 | hwif->pre_reset = &siimage_pre_reset; | |
2d5eaa6d | 908 | hwif->udma_filter = &sil_udma_filter; |
1da177e4 | 909 | |
19c1ef5f AC |
910 | if(is_sata(hwif)) { |
911 | static int first = 1; | |
912 | ||
1da177e4 LT |
913 | hwif->busproc = &siimage_busproc; |
914 | ||
19c1ef5f AC |
915 | if (first) { |
916 | printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n"); | |
917 | first = 0; | |
918 | } | |
919 | } | |
328dcbb6 BZ |
920 | |
921 | hwif->drives[0].autotune = hwif->drives[1].autotune = 1; | |
922 | ||
923 | if (hwif->dma_base == 0) | |
1da177e4 | 924 | return; |
1da177e4 LT |
925 | |
926 | hwif->ultra_mask = 0x7f; | |
927 | hwif->mwdma_mask = 0x07; | |
1da177e4 LT |
928 | |
929 | if (!is_sata(hwif)) | |
930 | hwif->atapi_dma = 1; | |
931 | ||
932 | hwif->ide_dma_check = &siimage_config_drive_for_dma; | |
49521f97 BZ |
933 | |
934 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) | |
935 | hwif->cbl = ata66_siimage(hwif); | |
1da177e4 LT |
936 | |
937 | if (hwif->mmio) { | |
938 | hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq; | |
939 | } else { | |
940 | hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq; | |
941 | } | |
942 | ||
943 | /* | |
944 | * The BIOS often doesn't set up DMA on this controller | |
945 | * so we always do it. | |
946 | */ | |
947 | ||
948 | hwif->autodma = 1; | |
949 | hwif->drives[0].autodma = hwif->autodma; | |
950 | hwif->drives[1].autodma = hwif->autodma; | |
951 | } | |
952 | ||
953 | #define DECLARE_SII_DEV(name_str) \ | |
954 | { \ | |
955 | .name = name_str, \ | |
956 | .init_chipset = init_chipset_siimage, \ | |
957 | .init_iops = init_iops_siimage, \ | |
958 | .init_hwif = init_hwif_siimage, \ | |
959 | .fixup = siimage_fixup, \ | |
1da177e4 LT |
960 | .autodma = AUTODMA, \ |
961 | .bootable = ON_BOARD, \ | |
962 | } | |
963 | ||
964 | static ide_pci_device_t siimage_chipsets[] __devinitdata = { | |
965 | /* 0 */ DECLARE_SII_DEV("SiI680"), | |
966 | /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"), | |
967 | /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA") | |
968 | }; | |
969 | ||
970 | /** | |
971 | * siimage_init_one - pci layer discovery entry | |
972 | * @dev: PCI device | |
973 | * @id: ident table entry | |
974 | * | |
975 | * Called by the PCI code when it finds an SI680 or SI3112 controller. | |
976 | * We then use the IDE PCI generic helper to do most of the work. | |
977 | */ | |
978 | ||
979 | static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
980 | { | |
981 | return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]); | |
982 | } | |
983 | ||
984 | static struct pci_device_id siimage_pci_tbl[] = { | |
28a2a3f5 | 985 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1da177e4 | 986 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
28a2a3f5 AC |
987 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
988 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
1da177e4 LT |
989 | #endif |
990 | { 0, }, | |
991 | }; | |
992 | MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); | |
993 | ||
994 | static struct pci_driver driver = { | |
995 | .name = "SiI_IDE", | |
996 | .id_table = siimage_pci_tbl, | |
997 | .probe = siimage_init_one, | |
998 | }; | |
999 | ||
82ab1eec | 1000 | static int __init siimage_ide_init(void) |
1da177e4 LT |
1001 | { |
1002 | return ide_pci_register_driver(&driver); | |
1003 | } | |
1004 | ||
1005 | module_init(siimage_ide_init); | |
1006 | ||
1007 | MODULE_AUTHOR("Andre Hedrick, Alan Cox"); | |
1008 | MODULE_DESCRIPTION("PCI driver module for SiI IDE"); | |
1009 | MODULE_LICENSE("GPL"); |