[mirror_ubuntu-zesty-kernel.git] / drivers / ide / pci / sis5513.c

/*
 * Copyright (C) 1999-2000	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2002		Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
 * Copyright (C) 2003		Vojtech Pavlik <vojtech@suse.cz>
 * Copyright (C) 2007		Bartlomiej Zolnierkiewicz
 *
 * May be copied or modified under the terms of the GNU General Public License
 *
 *
 * Thanks :
 *
 * SiS Taiwan		: for direct support and hardware.
 * Daniela Engert	: for initial ATA100 advices and numerous others.
 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt	:
 *			  for checking code correctness, providing patches.
 *
 *
 * Original tests and design on the SiS620 chipset.
 * ATA100 tests and design on the SiS735 chipset.
 * ATA16/33 support from specs
 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
 * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
 *
 * Documentation:
 *	SiS chipset documentation available under NDA to companies only
 *      (not to individuals).
 */

/*
 * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
 * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
 * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
 *
 * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
 * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
 * can figure out that we have a more modern and more capable 5513 by looking
 * for the respective NorthBridge IDs.
 *
 * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
 * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
 * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
 * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
 * bits, changing its device id to the true one - 5517 for 961 and 5518 for
 * 962/963.
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include "ide-timing.h"

/* registers layout and init values are chipset family dependant */

#define ATA_16		0x01
#define ATA_33		0x02
#define ATA_66		0x03
#define ATA_100a	0x04 /* SiS730/SiS550 is ATA100 with ATA66 layout */
#define ATA_100		0x05
#define ATA_133a	0x06 /* SiS961b with 133 support */
#define ATA_133		0x07 /* SiS962/963 */

static u8 chipset_family;

/*
 * Devices supported
 */
static const struct {
	const char *name;
	u16 host_id;
	u8 chipset_family;
	u8 flags;
} SiSHostChipInfo[] = {
	{ "SiS968",	PCI_DEVICE_ID_SI_968,	ATA_133  },
	{ "SiS966",	PCI_DEVICE_ID_SI_966,	ATA_133  },
	{ "SiS965",	PCI_DEVICE_ID_SI_965,	ATA_133  },
	{ "SiS745",	PCI_DEVICE_ID_SI_745,	ATA_100  },
	{ "SiS735",	PCI_DEVICE_ID_SI_735,	ATA_100  },
	{ "SiS733",	PCI_DEVICE_ID_SI_733,	ATA_100  },
	{ "SiS635",	PCI_DEVICE_ID_SI_635,	ATA_100  },
	{ "SiS633",	PCI_DEVICE_ID_SI_633,	ATA_100  },

	{ "SiS730",	PCI_DEVICE_ID_SI_730,	ATA_100a },
	{ "SiS550",	PCI_DEVICE_ID_SI_550,	ATA_100a },

	{ "SiS640",	PCI_DEVICE_ID_SI_640,	ATA_66   },
	{ "SiS630",	PCI_DEVICE_ID_SI_630,	ATA_66   },
	{ "SiS620",	PCI_DEVICE_ID_SI_620,	ATA_66   },
	{ "SiS540",	PCI_DEVICE_ID_SI_540,	ATA_66   },
	{ "SiS530",	PCI_DEVICE_ID_SI_530,	ATA_66   },

	{ "SiS5600",	PCI_DEVICE_ID_SI_5600,	ATA_33   },
	{ "SiS5598",	PCI_DEVICE_ID_SI_5598,	ATA_33   },
	{ "SiS5597",	PCI_DEVICE_ID_SI_5597,	ATA_33   },
	{ "SiS5591/2",	PCI_DEVICE_ID_SI_5591,	ATA_33   },
	{ "SiS5582",	PCI_DEVICE_ID_SI_5582,	ATA_33   },
	{ "SiS5581",	PCI_DEVICE_ID_SI_5581,	ATA_33   },

	{ "SiS5596",	PCI_DEVICE_ID_SI_5596,	ATA_16   },
	{ "SiS5571",	PCI_DEVICE_ID_SI_5571,	ATA_16   },
	{ "SiS5517",	PCI_DEVICE_ID_SI_5517,	ATA_16   },
	{ "SiS551x",	PCI_DEVICE_ID_SI_5511,	ATA_16   },
};

/* Cycle time bits and values vary across chip dma capabilities
   These three arrays hold the register layout and the values to set.
   Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */

/* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
static u8 cycle_time_offset[] = { 0, 0, 5, 4, 4, 0, 0 };
static u8 cycle_time_range[]  = { 0, 0, 2, 3, 3, 4, 4 };
static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
	{  0,  0, 0, 0, 0, 0, 0 }, /* no UDMA */
	{  0,  0, 0, 0, 0, 0, 0 }, /* no UDMA */
	{  3,  2, 1, 0, 0, 0, 0 }, /* ATA_33 */
	{  7,  5, 3, 2, 1, 0, 0 }, /* ATA_66 */
	{  7,  5, 3, 2, 1, 0, 0 }, /* ATA_100a (730 specific),
				      different cycle_time range and offset */
	{ 11,  7, 5, 4, 2, 1, 0 }, /* ATA_100 */
	{ 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133a (earliest 691 southbridges) */
	{ 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133 */
};
/* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
   See SiS962 data sheet for more detail */
static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
	{ 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
	{ 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
	{ 2, 1, 1, 0, 0, 0, 0 },
	{ 4, 3, 2, 1, 0, 0, 0 },
	{ 4, 3, 2, 1, 0, 0, 0 },
	{ 6, 4, 3, 1, 1, 1, 0 },
	{ 9, 6, 4, 2, 2, 2, 2 },
	{ 9, 6, 4, 2, 2, 2, 2 },
};
/* Initialize time, Active time, Recovery time vary across
   IDE clock settings. These 3 arrays hold the register value
   for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
static u8 ini_time_value[][8] = {
	{ 0, 0, 0, 0, 0, 0, 0, 0 },
	{ 0, 0, 0, 0, 0, 0, 0, 0 },
	{ 2, 1, 0, 0, 0, 1, 0, 0 },
	{ 4, 3, 1, 1, 1, 3, 1, 1 },
	{ 4, 3, 1, 1, 1, 3, 1, 1 },
	{ 6, 4, 2, 2, 2, 4, 2, 2 },
	{ 9, 6, 3, 3, 3, 6, 3, 3 },
	{ 9, 6, 3, 3, 3, 6, 3, 3 },
};
static u8 act_time_value[][8] = {
	{  0,  0,  0,  0, 0,  0,  0, 0 },
	{  0,  0,  0,  0, 0,  0,  0, 0 },
	{  9,  9,  9,  2, 2,  7,  2, 2 },
	{ 19, 19, 19,  5, 4, 14,  5, 4 },
	{ 19, 19, 19,  5, 4, 14,  5, 4 },
	{ 28, 28, 28,  7, 6, 21,  7, 6 },
	{ 38, 38, 38, 10, 9, 28, 10, 9 },
	{ 38, 38, 38, 10, 9, 28, 10, 9 },
};
static u8 rco_time_value[][8] = {
	{  0,  0, 0,  0, 0,  0,  0, 0 },
	{  0,  0, 0,  0, 0,  0,  0, 0 },
	{  9,  2, 0,  2, 0,  7,  1, 1 },
	{ 19,  5, 1,  5, 2, 16,  3, 2 },
	{ 19,  5, 1,  5, 2, 16,  3, 2 },
	{ 30,  9, 3,  9, 4, 25,  6, 4 },
	{ 40, 12, 4, 12, 5, 34, 12, 5 },
	{ 40, 12, 4, 12, 5, 34, 12, 5 },
};

/*
 * Printing configuration
 */
/* Used for chipset type printing at boot time */
static char *chipset_capability[] = {
	"ATA", "ATA 16",
	"ATA 33", "ATA 66",
	"ATA 100 (1st gen)", "ATA 100 (2nd gen)",
	"ATA 133 (1st gen)", "ATA 133 (2nd gen)"
};

/*
 * Configuration functions
 */

static u8 sis_ata133_get_base(ide_drive_t *drive)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	u32 reg54 = 0;

	pci_read_config_dword(dev, 0x54, &reg54);

	return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
}

static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	u16 t1 = 0;
	u8 drive_pci = 0x40 + drive->dn * 2;

	const u16 pio_timings[]   = { 0x000, 0x607, 0x404, 0x303, 0x301 };
	const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };

	pci_read_config_word(dev, drive_pci, &t1);

	/* clear active/recovery timings */
	t1 &= ~0x070f;
	if (mode >= XFER_MW_DMA_0) {
		if (chipset_family > ATA_16)
			t1 &= ~0x8000;	/* disable UDMA */
		t1 |= mwdma_timings[mode - XFER_MW_DMA_0];
	} else
		t1 |= pio_timings[mode - XFER_PIO_0];

	pci_write_config_word(dev, drive_pci, t1);
}

static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	u8 t1, drive_pci = 0x40 + drive->dn * 2;

	/* timing bits: 7:4 active 3:0 recovery */
	const u8 pio_timings[]   = { 0x00, 0x67, 0x44, 0x33, 0x31 };
	const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 };

	if (mode >= XFER_MW_DMA_0) {
		u8 t2 = 0;

		pci_read_config_byte(dev, drive_pci, &t2);
		t2 &= ~0x80;	/* disable UDMA */
		pci_write_config_byte(dev, drive_pci, t2);

		t1 = mwdma_timings[mode - XFER_MW_DMA_0];
	} else
		t1 = pio_timings[mode - XFER_PIO_0];

	pci_write_config_byte(dev, drive_pci + 1, t1);
}

static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	u32 t1 = 0;
	u8 drive_pci = sis_ata133_get_base(drive), clk, idx;

	pci_read_config_dword(dev, drive_pci, &t1);

	t1 &= 0xc0c00fff;
	clk = (t1 & 0x08) ? ATA_133 : ATA_100;
	if (mode >= XFER_MW_DMA_0) {
		t1 &= ~0x04;	/* disable UDMA */
		idx = mode - XFER_MW_DMA_0 + 5;
	} else
		idx = mode - XFER_PIO_0;
	t1 |= ini_time_value[clk][idx] << 12;
	t1 |= act_time_value[clk][idx] << 16;
	t1 |= rco_time_value[clk][idx] << 24;

	pci_write_config_dword(dev, drive_pci, t1);
}

static void sis_program_timings(ide_drive_t *drive, const u8 mode)
{
	if (chipset_family < ATA_100)		/* ATA_16/33/66/100a */
		sis_ata16_program_timings(drive, mode);
	else if (chipset_family < ATA_133)	/* ATA_100/133a */
		sis_ata100_program_timings(drive, mode);
	else					/* ATA_133 */
		sis_ata133_program_timings(drive, mode);
}

static void config_drive_art_rwp(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 reg4bh		= 0;
	u8 rw_prefetch		= 0;

	pci_read_config_byte(dev, 0x4b, &reg4bh);

	if (drive->media == ide_disk)
		rw_prefetch = 0x11 << drive->dn;

	if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch)
		pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
}

static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	config_drive_art_rwp(drive);
	sis_program_timings(drive, XFER_PIO_0 + pio);
}

static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	u32 regdw = 0;
	u8 drive_pci = sis_ata133_get_base(drive), clk, idx;

	pci_read_config_dword(dev, drive_pci, &regdw);

	regdw |= 0x04;
	regdw &= 0xfffff00f;
	/* check if ATA133 enable */
	clk = (regdw & 0x08) ? ATA_133 : ATA_100;
	idx = mode - XFER_UDMA_0;
	regdw |= cycle_time_value[clk][idx] << 4;
	regdw |= cvs_time_value[clk][idx] << 8;

	pci_write_config_dword(dev, drive_pci, regdw);
}

static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family;

	pci_read_config_byte(dev, drive_pci + 1, &reg);

	/* force the UDMA bit on if we want to use UDMA */
	reg |= 0x80;
	/* clean reg cycle time bits */
	reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]);
	/* set reg cycle time bits */
	reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i];

	pci_write_config_byte(dev, drive_pci + 1, reg);
}

static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
{
	if (chipset_family >= ATA_133)	/* ATA_133 */
		sis_ata133_program_udma_timings(drive, mode);
	else				/* ATA_33/66/100a/100/133a */
		sis_ata33_program_udma_timings(drive, mode);
}

static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	if (speed >= XFER_UDMA_0)
		sis_program_udma_timings(drive, speed);
	else
		sis_program_timings(drive, speed);
}

static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	u32 regdw = 0;
	u8 drive_pci = sis_ata133_get_base(drive);

	pci_read_config_dword(dev, drive_pci, &regdw);

	/* if ATA133 disable, we should not set speed above UDMA5 */
	return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5;
}

/* Chip detection and general config */
static unsigned int __devinit init_chipset_sis5513(struct pci_dev *dev,
						   const char *name)
{
	struct pci_dev *host;
	int i = 0;

	chipset_family = 0;

	for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {

		host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);

		if (!host)
			continue;

		chipset_family = SiSHostChipInfo[i].chipset_family;

		/* Special case for SiS630 : 630S/ET is ATA_100a */
		if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
			if (host->revision >= 0x30)
				chipset_family = ATA_100a;
		}
		pci_dev_put(host);

		printk(KERN_INFO "SIS5513: %s %s controller\n",
			 SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
	}

	if (!chipset_family) { /* Belongs to pci-quirks */

			u32 idemisc;
			u16 trueid;

			/* Disable ID masking and register remapping */
			pci_read_config_dword(dev, 0x54, &idemisc);
			pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
			pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
			pci_write_config_dword(dev, 0x54, idemisc);

			if (trueid == 0x5518) {
				printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
				chipset_family = ATA_133;

				/* Check for 5513 compability mapping
				 * We must use this, else the port enabled code will fail,
				 * as it expects the enablebits at 0x4a.
				 */
				if ((idemisc & 0x40000000) == 0) {
					pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
					printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
				}
			}
	}

	if (!chipset_family) { /* Belongs to pci-quirks */

			struct pci_dev *lpc_bridge;
			u16 trueid;
			u8 prefctl;
			u8 idecfg;

			pci_read_config_byte(dev, 0x4a, &idecfg);
			pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
			pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
			pci_write_config_byte(dev, 0x4a, idecfg);

			if (trueid == 0x5517) { /* SiS 961/961B */

				lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
				pci_read_config_byte(dev, 0x49, &prefctl);
				pci_dev_put(lpc_bridge);

				if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
					printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
					chipset_family = ATA_133a;
				} else {
					printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
					chipset_family = ATA_100;
				}
			}
	}

	if (!chipset_family)
		return -1;

	/* Make general config ops here
	   1/ tell IDE channels to operate in Compatibility mode only
	   2/ tell old chips to allow per drive IDE timings */

	{
	u8 reg;
	u16 regw;

	switch (chipset_family) {
	case ATA_133:
		/* SiS962 operation mode */
		pci_read_config_word(dev, 0x50, &regw);
		if (regw & 0x08)
			pci_write_config_word(dev, 0x50, regw&0xfff7);
		pci_read_config_word(dev, 0x52, &regw);
		if (regw & 0x08)
			pci_write_config_word(dev, 0x52, regw&0xfff7);
		break;
	case ATA_133a:
	case ATA_100:
		/* Fixup latency */
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
		/* Set compatibility bit */
		pci_read_config_byte(dev, 0x49, &reg);
		if (!(reg & 0x01))
			pci_write_config_byte(dev, 0x49, reg|0x01);
		break;
	case ATA_100a:
	case ATA_66:
		/* Fixup latency */
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);

		/* On ATA_66 chips the bit was elsewhere */
		pci_read_config_byte(dev, 0x52, &reg);
		if (!(reg & 0x04))
			pci_write_config_byte(dev, 0x52, reg|0x04);
		break;
	case ATA_33:
		/* On ATA_33 we didn't have a single bit to set */
		pci_read_config_byte(dev, 0x09, &reg);
		if ((reg & 0x0f) != 0x00)
			pci_write_config_byte(dev, 0x09, reg&0xf0);
	case ATA_16:
		/* force per drive recovery and active timings
		   needed on ATA_33 and below chips */
		pci_read_config_byte(dev, 0x52, &reg);
		if (!(reg & 0x08))
			pci_write_config_byte(dev, 0x52, reg|0x08);
		break;
	}
	}

	return 0;
}

struct sis_laptop {
	u16 device;
	u16 subvendor;
	u16 subdevice;
};

static const struct sis_laptop sis_laptop[] = {
	/* devid, subvendor, subdev */
	{ 0x5513, 0x1043, 0x1107 },	/* ASUS A6K */
	{ 0x5513, 0x1734, 0x105f },	/* FSC Amilo A1630 */
	{ 0x5513, 0x1071, 0x8640 },     /* EasyNote K5305 */
	/* end marker */
	{ 0, }
};

static u8 __devinit ata66_sis5513(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	const struct sis_laptop *lap = &sis_laptop[0];
	u8 ata66 = 0;

	while (lap->device) {
		if (lap->device == pdev->device &&
		    lap->subvendor == pdev->subsystem_vendor &&
		    lap->subdevice == pdev->subsystem_device)
			return ATA_CBL_PATA40_SHORT;
		lap++;
	}

	if (chipset_family >= ATA_133) {
		u16 regw = 0;
		u16 reg_addr = hwif->channel ? 0x52: 0x50;
		pci_read_config_word(pdev, reg_addr, &regw);
		ata66 = (regw & 0x8000) ? 0 : 1;
	} else if (chipset_family >= ATA_66) {
		u8 reg48h = 0;
		u8 mask = hwif->channel ? 0x20 : 0x10;
		pci_read_config_byte(pdev, 0x48, &reg48h);
		ata66 = (reg48h & mask) ? 0 : 1;
	}

	return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
}

static void __devinit init_hwif_sis5513(ide_hwif_t *hwif)
{
	u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };

	hwif->set_pio_mode = &sis_set_pio_mode;
	hwif->set_dma_mode = &sis_set_dma_mode;

	if (chipset_family >= ATA_133)
		hwif->udma_filter = sis5513_ata133_udma_filter;

	hwif->cable_detect = ata66_sis5513;

	if (hwif->dma_base == 0)
		return;

	hwif->ultra_mask = udma_rates[chipset_family];
}

static const struct ide_port_info sis5513_chipset __devinitdata = {
	.name		= "SIS5513",
	.init_chipset	= init_chipset_sis5513,
	.init_hwif	= init_hwif_sis5513,
	.enablebits	= { {0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04} },
	.host_flags	= IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
};

static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &sis5513_chipset);
}

static const struct pci_device_id sis5513_pci_tbl[] = {
	{ PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 },
	{ PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 },
	{ PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);

static struct pci_driver driver = {
	.name		= "SIS_IDE",
	.id_table	= sis5513_pci_tbl,
	.probe		= sis5513_init_one,
};

static int __init sis5513_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(sis5513_ide_init);

MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
MODULE_DESCRIPTION("PCI driver module for SIS IDE");
MODULE_LICENSE("GPL");

/*
 * TODO:
 *	- CLEANUP
 *	- Use drivers/ide/ide-timing.h !
 *	- More checks in the config registers (force values instead of
 *	  relying on the BIOS setting them correctly).
 *	- Further optimisations ?
 *	  . for example ATA66+ regs 0x48 & 0x4A
 */
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
	3	* Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
	4	* Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
6b8cf772 BZ	5	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6b8cf772 BZ	6	*
1da177e4 LT	7	* May be copied or modified under the terms of the GNU General Public License
	8	*
	9	*
	10	* Thanks :
	11	*
	12	* SiS Taiwan : for direct support and hardware.
	13	* Daniela Engert : for initial ATA100 advices and numerous others.
	14	* John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
	15	* for checking code correctness, providing patches.
	16	*
	17	*
	18	* Original tests and design on the SiS620 chipset.
	19	* ATA100 tests and design on the SiS735 chipset.
	20	* ATA16/33 support from specs
	21	* ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
	22	* ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
	23	*
	24	* Documentation:
	25	* SiS chipset documentation available under NDA to companies only
	26	* (not to individuals).
	27	*/
	28
	29	/*
	30	* The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
	31	* SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
	32	* or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
	33	*
	34	* Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
	35	* starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
	36	* can figure out that we have a more modern and more capable 5513 by looking
	37	* for the respective NorthBridge IDs.
	38	*
	39	* Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
	40	* into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
	41	* ID, while the now ATA-133 capable 5513 still has the same PCI ID.
	42	* Fortunately the 5513 can be 'unmasked' by fiddling with some config space
	43	* bits, changing its device id to the true one - 5517 for 961 and 5518 for
	44	* 962/963.
	45	*/
	46
1da177e4 LT	47	#include <linux/types.h>
	48	#include <linux/module.h>
	49	#include <linux/kernel.h>
1da177e4	50	#include <linux/hdreg.h>
1da177e4 LT	51	#include <linux/pci.h>
	52	#include <linux/init.h>
	53	#include <linux/ide.h>
	54
1da177e4 LT	55	#include "ide-timing.h"
1da177e4 LT	56
1da177e4 LT	57	/* registers layout and init values are chipset family dependant */
	58
	59	#define ATA_16 0x01
	60	#define ATA_33 0x02
	61	#define ATA_66 0x03
1eb3c2ee	62	#define ATA_100a 0x04 /* SiS730/SiS550 is ATA100 with ATA66 layout */
1da177e4	63	#define ATA_100 0x05
1eb3c2ee PC	64	#define ATA_133a 0x06 /* SiS961b with 133 support */
1eb3c2ee PC	65	#define ATA_133 0x07 /* SiS962/963 */
1da177e4 LT	66
	67	static u8 chipset_family;
	68
	69	/*
	70	* Devices supported
	71	*/
	72	static const struct {
	73	const char *name;
	74	u16 host_id;
	75	u8 chipset_family;
	76	u8 flags;
	77	} SiSHostChipInfo[] = {
47d4b906 DW	78	{ "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 },
47d4b906 DW	79	{ "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 },
14351f8e	80	{ "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 },
1da177e4 LT	81	{ "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
	82	{ "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
	83	{ "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
	84	{ "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
	85	{ "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
	86
	87	{ "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
	88	{ "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
	89
	90	{ "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
	91	{ "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
	92	{ "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
	93	{ "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
	94	{ "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
	95
	96	{ "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
	97	{ "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
	98	{ "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
	99	{ "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
	100	{ "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
	101	{ "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
	102
	103	{ "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
	104	{ "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
d266ab88	105	{ "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 },
1da177e4 LT	106	{ "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
	107	};
	108
	109	/* Cycle time bits and values vary across chip dma capabilities
	110	These three arrays hold the register layout and the values to set.
	111	Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
	112
	113	/* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
1eb3c2ee PC	114	static u8 cycle_time_offset[] = { 0, 0, 5, 4, 4, 0, 0 };
1eb3c2ee PC	115	static u8 cycle_time_range[] = { 0, 0, 2, 3, 3, 4, 4 };
1da177e4	116	static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
1eb3c2ee PC	117	{ 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
	118	{ 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
	119	{ 3, 2, 1, 0, 0, 0, 0 }, /* ATA_33 */
	120	{ 7, 5, 3, 2, 1, 0, 0 }, /* ATA_66 */
	121	{ 7, 5, 3, 2, 1, 0, 0 }, /* ATA_100a (730 specific),
	122	different cycle_time range and offset */
	123	{ 11, 7, 5, 4, 2, 1, 0 }, /* ATA_100 */
	124	{ 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133a (earliest 691 southbridges) */
	125	{ 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133 */
1da177e4 LT	126	};
	127	/* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
	128	See SiS962 data sheet for more detail */
	129	static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
1eb3c2ee PC	130	{ 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
	131	{ 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
	132	{ 2, 1, 1, 0, 0, 0, 0 },
	133	{ 4, 3, 2, 1, 0, 0, 0 },
	134	{ 4, 3, 2, 1, 0, 0, 0 },
	135	{ 6, 4, 3, 1, 1, 1, 0 },
	136	{ 9, 6, 4, 2, 2, 2, 2 },
	137	{ 9, 6, 4, 2, 2, 2, 2 },
1da177e4 LT	138	};
	139	/* Initialize time, Active time, Recovery time vary across
	140	IDE clock settings. These 3 arrays hold the register value
	141	for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
	142	static u8 ini_time_value[][8] = {
1eb3c2ee PC	143	{ 0, 0, 0, 0, 0, 0, 0, 0 },
	144	{ 0, 0, 0, 0, 0, 0, 0, 0 },
	145	{ 2, 1, 0, 0, 0, 1, 0, 0 },
	146	{ 4, 3, 1, 1, 1, 3, 1, 1 },
	147	{ 4, 3, 1, 1, 1, 3, 1, 1 },
	148	{ 6, 4, 2, 2, 2, 4, 2, 2 },
	149	{ 9, 6, 3, 3, 3, 6, 3, 3 },
	150	{ 9, 6, 3, 3, 3, 6, 3, 3 },
1da177e4 LT	151	};
1da177e4 LT	152	static u8 act_time_value[][8] = {
1eb3c2ee PC	153	{ 0, 0, 0, 0, 0, 0, 0, 0 },
	154	{ 0, 0, 0, 0, 0, 0, 0, 0 },
	155	{ 9, 9, 9, 2, 2, 7, 2, 2 },
	156	{ 19, 19, 19, 5, 4, 14, 5, 4 },
	157	{ 19, 19, 19, 5, 4, 14, 5, 4 },
	158	{ 28, 28, 28, 7, 6, 21, 7, 6 },
	159	{ 38, 38, 38, 10, 9, 28, 10, 9 },
	160	{ 38, 38, 38, 10, 9, 28, 10, 9 },
1da177e4 LT	161	};
1da177e4 LT	162	static u8 rco_time_value[][8] = {
1eb3c2ee PC	163	{ 0, 0, 0, 0, 0, 0, 0, 0 },
	164	{ 0, 0, 0, 0, 0, 0, 0, 0 },
	165	{ 9, 2, 0, 2, 0, 7, 1, 1 },
	166	{ 19, 5, 1, 5, 2, 16, 3, 2 },
	167	{ 19, 5, 1, 5, 2, 16, 3, 2 },
	168	{ 30, 9, 3, 9, 4, 25, 6, 4 },
	169	{ 40, 12, 4, 12, 5, 34, 12, 5 },
	170	{ 40, 12, 4, 12, 5, 34, 12, 5 },
1da177e4 LT	171	};
	172
	173	/*
	174	* Printing configuration
	175	*/
	176	/* Used for chipset type printing at boot time */
1eb3c2ee	177	static char *chipset_capability[] = {
1da177e4 LT	178	"ATA", "ATA 16",
	179	"ATA 33", "ATA 66",
	180	"ATA 100 (1st gen)", "ATA 100 (2nd gen)",
	181	"ATA 133 (1st gen)", "ATA 133 (2nd gen)"
	182	};
	183
1da177e4 LT	184	/*
	185	* Configuration functions
	186	*/
c77a89cd BZ	187
	188	static u8 sis_ata133_get_base(ide_drive_t *drive)
	189	{
36501650	190	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
c77a89cd BZ	191	u32 reg54 = 0;
	192
	193	pci_read_config_dword(dev, 0x54, &reg54);
	194
	195	return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
	196	}
	197
	198	static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
	199	{
36501650	200	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
c77a89cd BZ	201	u16 t1 = 0;
	202	u8 drive_pci = 0x40 + drive->dn * 2;
	203
	204	const u16 pio_timings[] = { 0x000, 0x607, 0x404, 0x303, 0x301 };
	205	const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };
	206
	207	pci_read_config_word(dev, drive_pci, &t1);
	208
	209	/* clear active/recovery timings */
	210	t1 &= ~0x070f;
	211	if (mode >= XFER_MW_DMA_0) {
	212	if (chipset_family > ATA_16)
	213	t1 &= ~0x8000; /* disable UDMA */
	214	t1 \|= mwdma_timings[mode - XFER_MW_DMA_0];
	215	} else
	216	t1 \|= pio_timings[mode - XFER_PIO_0];
	217
	218	pci_write_config_word(dev, drive_pci, t1);
	219	}
	220
	221	static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode)
	222	{
36501650	223	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
c77a89cd BZ	224	u8 t1, drive_pci = 0x40 + drive->dn * 2;
	225
	226	/* timing bits: 7:4 active 3:0 recovery */
	227	const u8 pio_timings[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
	228	const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 };
	229
	230	if (mode >= XFER_MW_DMA_0) {
	231	u8 t2 = 0;
	232
	233	pci_read_config_byte(dev, drive_pci, &t2);
	234	t2 &= ~0x80; /* disable UDMA */
	235	pci_write_config_byte(dev, drive_pci, t2);
	236
	237	t1 = mwdma_timings[mode - XFER_MW_DMA_0];
	238	} else
	239	t1 = pio_timings[mode - XFER_PIO_0];
	240
	241	pci_write_config_byte(dev, drive_pci + 1, t1);
	242	}
	243
	244	static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
	245	{
36501650	246	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
c77a89cd BZ	247	u32 t1 = 0;
	248	u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
	249
	250	pci_read_config_dword(dev, drive_pci, &t1);
	251
	252	t1 &= 0xc0c00fff;
	253	clk = (t1 & 0x08) ? ATA_133 : ATA_100;
	254	if (mode >= XFER_MW_DMA_0) {
	255	t1 &= ~0x04; /* disable UDMA */
	256	idx = mode - XFER_MW_DMA_0 + 5;
3dfd6433	257	} else
c77a89cd BZ	258	idx = mode - XFER_PIO_0;
	259	t1 \|= ini_time_value[clk][idx] << 12;
	260	t1 \|= act_time_value[clk][idx] << 16;
	261	t1 \|= rco_time_value[clk][idx] << 24;
	262
	263	pci_write_config_dword(dev, drive_pci, t1);
	264	}
	265
	266	static void sis_program_timings(ide_drive_t *drive, const u8 mode)
	267	{
	268	if (chipset_family < ATA_100) /* ATA_16/33/66/100a */
	269	sis_ata16_program_timings(drive, mode);
	270	else if (chipset_family < ATA_133) /* ATA_100/133a */
	271	sis_ata100_program_timings(drive, mode);
	272	else /* ATA_133 */
	273	sis_ata133_program_timings(drive, mode);
	274	}
	275
1eb3c2ee	276	static void config_drive_art_rwp(ide_drive_t *drive)
1da177e4 LT	277	{
1da177e4 LT	278	ide_hwif_t *hwif = HWIF(drive);
36501650	279	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	280	u8 reg4bh = 0;
d83fca58	281	u8 rw_prefetch = 0;
1da177e4	282
1da177e4 LT	283	pci_read_config_byte(dev, 0x4b, &reg4bh);
1da177e4 LT	284
d83fca58 BZ	285	if (drive->media == ide_disk)
	286	rw_prefetch = 0x11 << drive->dn;
	287
	288	if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch)
1da177e4 LT	289	pci_write_config_byte(dev, 0x4b, reg4bh\|rw_prefetch);
	290	}
	291
88b2b32b	292	static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	293	{
1da177e4	294	config_drive_art_rwp(drive);
c77a89cd	295	sis_program_timings(drive, XFER_PIO_0 + pio);
1da177e4 LT	296	}
1da177e4 LT	297
428c6440	298	static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
1da177e4	299	{
36501650	300	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
428c6440 BZ	301	u32 regdw = 0;
	302	u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
	303
	304	pci_read_config_dword(dev, drive_pci, &regdw);
	305
	306	regdw \|= 0x04;
	307	regdw &= 0xfffff00f;
	308	/* check if ATA133 enable */
	309	clk = (regdw & 0x08) ? ATA_133 : ATA_100;
	310	idx = mode - XFER_UDMA_0;
	311	regdw \|= cycle_time_value[clk][idx] << 4;
	312	regdw \|= cvs_time_value[clk][idx] << 8;
	313
	314	pci_write_config_dword(dev, drive_pci, regdw);
	315	}
	316
	317	static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode)
	318	{
36501650	319	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
428c6440 BZ	320	u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family;
	321
	322	pci_read_config_byte(dev, drive_pci + 1, &reg);
	323
	324	/* force the UDMA bit on if we want to use UDMA */
	325	reg \|= 0x80;
	326	/* clean reg cycle time bits */
	327	reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]);
	328	/* set reg cycle time bits */
	329	reg \|= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i];
	330
	331	pci_write_config_byte(dev, drive_pci + 1, reg);
	332	}
1da177e4	333
428c6440 BZ	334	static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
	335	{
	336	if (chipset_family >= ATA_133) /* ATA_133 */
	337	sis_ata133_program_udma_timings(drive, mode);
	338	else /* ATA_33/66/100a/100/133a */
	339	sis_ata33_program_udma_timings(drive, mode);
	340	}
	341
	342	static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
	343	{
4db90a14 BZ	344	if (speed >= XFER_UDMA_0)
	345	sis_program_udma_timings(drive, speed);
	346	else
	347	sis_program_timings(drive, speed);
1da177e4 LT	348	}
1da177e4 LT	349
3160d541 BZ	350	static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
3160d541 BZ	351	{
36501650	352	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
c77a89cd BZ	353	u32 regdw = 0;
c77a89cd BZ	354	u8 drive_pci = sis_ata133_get_base(drive);
3160d541	355
3160d541 BZ	356	pci_read_config_dword(dev, drive_pci, &regdw);
	357
	358	/* if ATA133 disable, we should not set speed above UDMA5 */
	359	return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5;
	360	}
	361
1da177e4	362	/* Chip detection and general config */
1eb3c2ee PC	363	static unsigned int __devinit init_chipset_sis5513(struct pci_dev *dev,
1eb3c2ee PC	364	const char *name)
1da177e4 LT	365	{
	366	struct pci_dev *host;
	367	int i = 0;
	368
	369	chipset_family = 0;
	370
	371	for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
	372
40cddf2c	373	host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
1da177e4 LT	374
	375	if (!host)
	376	continue;
	377
	378	chipset_family = SiSHostChipInfo[i].chipset_family;
	379
	380	/* Special case for SiS630 : 630S/ET is ATA_100a */
	381	if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
44c10138	382	if (host->revision >= 0x30)
1da177e4 LT	383	chipset_family = ATA_100a;
1da177e4 LT	384	}
40cddf2c	385	pci_dev_put(host);
1eb3c2ee	386
1da177e4 LT	387	printk(KERN_INFO "SIS5513: %s %s controller\n",
	388	SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
	389	}
	390
	391	if (!chipset_family) { /* Belongs to pci-quirks */
	392
	393	u32 idemisc;
	394	u16 trueid;
	395
	396	/* Disable ID masking and register remapping */
	397	pci_read_config_dword(dev, 0x54, &idemisc);
	398	pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
	399	pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
	400	pci_write_config_dword(dev, 0x54, idemisc);
	401
	402	if (trueid == 0x5518) {
	403	printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
	404	chipset_family = ATA_133;
	405
	406	/* Check for 5513 compability mapping
	407	* We must use this, else the port enabled code will fail,
	408	* as it expects the enablebits at 0x4a.
	409	*/
	410	if ((idemisc & 0x40000000) == 0) {
	411	pci_write_config_dword(dev, 0x54, idemisc \| 0x40000000);
	412	printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
	413	}
	414	}
	415	}
	416
	417	if (!chipset_family) { /* Belongs to pci-quirks */
	418
	419	struct pci_dev *lpc_bridge;
	420	u16 trueid;
	421	u8 prefctl;
	422	u8 idecfg;
1da177e4 LT	423
	424	pci_read_config_byte(dev, 0x4a, &idecfg);
	425	pci_write_config_byte(dev, 0x4a, idecfg \| 0x10);
	426	pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
	427	pci_write_config_byte(dev, 0x4a, idecfg);
	428
	429	if (trueid == 0x5517) { /* SiS 961/961B */
	430
b1489009	431	lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
1da177e4	432	pci_read_config_byte(dev, 0x49, &prefctl);
b1489009	433	pci_dev_put(lpc_bridge);
1da177e4	434
44c10138	435	if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
1da177e4 LT	436	printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
	437	chipset_family = ATA_133a;
	438	} else {
	439	printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
	440	chipset_family = ATA_100;
	441	}
	442	}
	443	}
	444
	445	if (!chipset_family)
	446	return -1;
	447
	448	/* Make general config ops here
	449	1/ tell IDE channels to operate in Compatibility mode only
	450	2/ tell old chips to allow per drive IDE timings */
	451
	452	{
1eb3c2ee PC	453	u8 reg;
	454	u16 regw;
	455
	456	switch (chipset_family) {
	457	case ATA_133:
	458	/* SiS962 operation mode */
	459	pci_read_config_word(dev, 0x50, &regw);
	460	if (regw & 0x08)
	461	pci_write_config_word(dev, 0x50, regw&0xfff7);
	462	pci_read_config_word(dev, 0x52, &regw);
	463	if (regw & 0x08)
	464	pci_write_config_word(dev, 0x52, regw&0xfff7);
	465	break;
	466	case ATA_133a:
	467	case ATA_100:
	468	/* Fixup latency */
	469	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
	470	/* Set compatibility bit */
	471	pci_read_config_byte(dev, 0x49, &reg);
	472	if (!(reg & 0x01))
	473	pci_write_config_byte(dev, 0x49, reg\|0x01);
	474	break;
	475	case ATA_100a:
	476	case ATA_66:
	477	/* Fixup latency */
	478	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
	479
	480	/* On ATA_66 chips the bit was elsewhere */
	481	pci_read_config_byte(dev, 0x52, &reg);
	482	if (!(reg & 0x04))
	483	pci_write_config_byte(dev, 0x52, reg\|0x04);
	484	break;
	485	case ATA_33:
	486	/* On ATA_33 we didn't have a single bit to set */
	487	pci_read_config_byte(dev, 0x09, &reg);
	488	if ((reg & 0x0f) != 0x00)
	489	pci_write_config_byte(dev, 0x09, reg&0xf0);
	490	case ATA_16:
	491	/* force per drive recovery and active timings
	492	needed on ATA_33 and below chips */
	493	pci_read_config_byte(dev, 0x52, &reg);
	494	if (!(reg & 0x08))
	495	pci_write_config_byte(dev, 0x52, reg\|0x08);
	496	break;
	497	}
1da177e4 LT	498	}
	499
	500	return 0;
	501	}
	502
f2befd9e BZ	503	struct sis_laptop {
	504	u16 device;
	505	u16 subvendor;
	506	u16 subdevice;
	507	};
	508
	509	static const struct sis_laptop sis_laptop[] = {
	510	/* devid, subvendor, subdev */
	511	{ 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
1955f681	512	{ 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */
a1d85864	513	{ 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
f2befd9e BZ	514	/* end marker */
	515	{ 0, }
	516	};
	517
49521f97	518	static u8 __devinit ata66_sis5513(ide_hwif_t *hwif)
1da177e4	519	{
36501650	520	struct pci_dev *pdev = to_pci_dev(hwif->dev);
f2befd9e	521	const struct sis_laptop *lap = &sis_laptop[0];
1da177e4 LT	522	u8 ata66 = 0;
1da177e4 LT	523
f2befd9e BZ	524	while (lap->device) {
	525	if (lap->device == pdev->device &&
	526	lap->subvendor == pdev->subsystem_vendor &&
	527	lap->subdevice == pdev->subsystem_device)
	528	return ATA_CBL_PATA40_SHORT;
	529	lap++;
	530	}
	531
1da177e4 LT	532	if (chipset_family >= ATA_133) {
	533	u16 regw = 0;
	534	u16 reg_addr = hwif->channel ? 0x52: 0x50;
36501650	535	pci_read_config_word(pdev, reg_addr, &regw);
1da177e4 LT	536	ata66 = (regw & 0x8000) ? 0 : 1;
	537	} else if (chipset_family >= ATA_66) {
	538	u8 reg48h = 0;
	539	u8 mask = hwif->channel ? 0x20 : 0x10;
36501650	540	pci_read_config_byte(pdev, 0x48, &reg48h);
1da177e4 LT	541	ata66 = (reg48h & mask) ? 0 : 1;
1da177e4 LT	542	}
49521f97 BZ	543
49521f97 BZ	544	return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
1da177e4 LT	545	}
1da177e4 LT	546
1eb3c2ee	547	static void __devinit init_hwif_sis5513(ide_hwif_t *hwif)
1da177e4	548	{
18137207 BZ	549	u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
18137207 BZ	550
26bcb879	551	hwif->set_pio_mode = &sis_set_pio_mode;
88b2b32b	552	hwif->set_dma_mode = &sis_set_dma_mode;
1da177e4	553
3160d541 BZ	554	if (chipset_family >= ATA_133)
	555	hwif->udma_filter = sis5513_ata133_udma_filter;
	556
bfa14b42 BZ	557	hwif->cable_detect = ata66_sis5513;
bfa14b42 BZ	558
4960ab7c	559	if (hwif->dma_base == 0)
1da177e4	560	return;
1da177e4	561
18137207	562	hwif->ultra_mask = udma_rates[chipset_family];
1da177e4 LT	563	}
1da177e4 LT	564
85620436	565	static const struct ide_port_info sis5513_chipset __devinitdata = {
1da177e4 LT	566	.name = "SIS5513",
	567	.init_chipset = init_chipset_sis5513,
	568	.init_hwif = init_hwif_sis5513,
1eb3c2ee	569	.enablebits = { {0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04} },
5e71d9c5	570	.host_flags = IDE_HFLAG_LEGACY_IRQS \| IDE_HFLAG_NO_AUTODMA,
4099d143	571	.pio_mask = ATA_PIO4,
5f8b6c34	572	.mwdma_mask = ATA_MWDMA2,
1da177e4 LT	573	};
	574
	575	static int __devinit sis5513_init_one(struct pci_dev dev, const struct pci_device_id id)
	576	{
	577	return ide_setup_pci_device(dev, &sis5513_chipset);
	578	}
	579
9cbcc5e3 BZ	580	static const struct pci_device_id sis5513_pci_tbl[] = {
	581	{ PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 },
	582	{ PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 },
	583	{ PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 },
1da177e4 LT	584	{ 0, },
	585	};
	586	MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
	587
	588	static struct pci_driver driver = {
	589	.name = "SIS_IDE",
	590	.id_table = sis5513_pci_tbl,
	591	.probe = sis5513_init_one,
	592	};
	593
82ab1eec	594	static int __init sis5513_ide_init(void)
1da177e4 LT	595	{
	596	return ide_pci_register_driver(&driver);
	597	}
	598
	599	module_init(sis5513_ide_init);
	600
	601	MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
	602	MODULE_DESCRIPTION("PCI driver module for SIS IDE");
	603	MODULE_LICENSE("GPL");
	604
	605	/*
	606	* TODO:
	607	* - CLEANUP
	608	* - Use drivers/ide/ide-timing.h !
	609	* - More checks in the config registers (force values instead of
	610	* relying on the BIOS setting them correctly).
	611	* - Further optimisations ?
	612	* . for example ATA66+ regs 0x48 & 0x4A
	613	*/